Semiconductor device, fabrication method, three-dimensional memory, and storage system

Abstract

The application provides a semiconductor device, a manufacturing method, a three-dimensional memory and a storage system. The manufacturing method of the semiconductor device comprises the following steps: forming a stack layer by alternately stacking a sacrificial layer and an insulating layer on a substrate, and the stack layer comprises a top select gate stack layer located away from the substrate; forming a step region in the stack layer, the step region comprises a plurality of steps, each step has a step top surface layer and a step longitudinal surface, and the step region is provided with a first groove which at least partially penetrates the step top surface layer; forming a second groove in the step top surface layer close to the step longitudinal surface; forming a top select gate trench in the top select gate stack layer; and the projection of the top select gate trench and the second groove on the step top surface layer at least partially overlaps. By forming the second groove in the stack layer, the aggregation of the polymer during the subsequent formation of the top select gate trench is improved, the process of forming the top select gate trench is optimized, and the yield and reliability of the device are improved.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method for fabricating the semiconductor device includes: A stacked layer is formed by alternately stacking sacrificial layers and insulating layers on a substrate, and the stacked layer includes a top selected gate stack located on the side away from the substrate; A step region is formed in the stacked layer, the step region including a plurality of steps, each step having a step top surface layer and a step longitudinal surface, and a first groove extending in a second direction is formed in the step top surface layer; A second groove is formed in the top layer of each step near the longitudinal surface of the step, and the projection of the second groove onto the substrate at least partially overlaps with the projection of the first groove onto the substrate. A top selection gate slot is formed in the top selection gate stack, the top selection gate slot extending along a first direction parallel to the substrate, the first direction intersecting with a second direction; Wherein, the projection of the top selected grid groove and the second groove on the top surface layer of the step at least partially overlaps.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein The step of forming the second groove further includes that the second groove extends along the first direction, and the top selected grid cut has an overlapping portion with the projection of the first groove on the top surface layer of the step, the overlapping portion being located within the projection of the second groove on the top surface layer of the step.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the second groove further includes forming a plurality of sub-second grooves spaced apart along the first direction, wherein the top selected grid cut groove and the projection of the first groove on the top surface layer of the step have an overlapping portion, and the overlapping portion is located within the projection of the second groove on the top surface layer of the step.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the second groove further includes the second groove extending along the second direction, wherein the top selected grid cut has an overlapping portion with the projection of the first groove on the top surface layer of the step, and the overlapping portion is located within the projection of the second groove on the top surface layer of the step.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The method for manufacturing the semiconductor device further includes: A protective layer is formed on the stacked layers, and a portion of the protective layer is located near the outer periphery of the stacked layers; Remove the protective layer located in the peripheral area; The protective layer located in the outer perimeter area is formed simultaneously with the top surface layer of the step, and the remaining protective layer in the step area forms the top surface layer of the step.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The step of removing the protective layer located in the peripheral area and the step of forming the second groove are formed using the same mask.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the second groove further includes that the depth of the single second groove in a third direction perpendicular to the substrate is greater than or equal to the depth of the single first groove in that third direction.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the second groove further includes the second groove penetrating the top surface layer of the step and the sacrificial layer, and extending to the corresponding insulating layers.

9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of forming the top surface layer of the step further includes that the sacrificial layer and the top surface layer of the step are made of the same material.

10. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor layer; A stacked structure comprising alternating gate layers and insulating layers located on the semiconductor layer, the stacked structure including a top select gate structure located on the side away from the semiconductor layer; Multiple steps are provided in the stacked structure, each step having a top surface layer and a longitudinal surface, and a first groove structure extending in a second direction is formed in the top surface layer of the step. A second groove structure is provided in the top layer of each step near the longitudinal surface of the step, and the projection of the second groove structure onto the substrate at least partially overlaps with the projection of the first groove structure. A top selection gate slot structure is provided in the top selection gate structure, the top selection gate slot structure extends along a first direction parallel to the semiconductor layer, the first direction intersects with the second direction; Wherein, the projection of the top selected grid groove structure and the second groove structure on the top surface layer of the step at least partially overlaps.

11. The semiconductor device as claimed in claim 10, characterized in that, The second groove structure extends along the first direction, and the top selected grid groove structure and the projection of the first groove structure on the top surface layer of the step have an overlapping portion, the overlapping portion being located within the projection of the second groove structure on the top surface layer of the step.

12. The semiconductor device as claimed in claim 10, characterized in that, The second groove structure includes a plurality of sub-second groove structures spaced apart along the first direction. The top selected grid groove structure and the projection of the first groove structure on the top surface layer of the step have an overlapping portion, and the overlapping portion is located within the projection of the second groove structure on the top surface layer of the step.

13. The semiconductor device as claimed in claim 10, characterized in that, The second groove structure extends along the second direction, and the top selected grid groove structure and the projection of the first groove structure on the top surface layer of the step have an overlapping portion, the overlapping portion being located within the projection of the second groove structure on the top surface layer of the step.

14. The semiconductor device as claimed in claim 10, characterized in that, The depth of a single second groove structure in a third direction perpendicular to the semiconductor layer is greater than or equal to the depth of a single first groove structure in that third direction.

15. The semiconductor device as claimed in claim 10, characterized in that, The second groove passes through the stepped top surface layer and the gate layer, and extends to the corresponding insulating layer.

16. A three-dimensional memory, characterized in that, The three-dimensional memory includes an array memory structure and peripheral circuitry, wherein the array memory structure includes a semiconductor device as described in any one of claims 10 to 15.

17. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory including a semiconductor device as described in any one of claims 10 to 15.

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