A pulse power multiplier type microwave power amplifier

Abstract

The present invention discloses a pulse power multiplier type microwave power amplifier, which includes a pre-stage amplification matching circuit, a final-stage transistor, a bias circuit, a matching circuit, and a time delay circuit. The pre-stage amplification matching circuit, the final-stage transistor, the matching circuit, and the time delay circuit are connected in sequence along the microwave signal transmission direction. The matching circuit provides matching between the final-stage transistor and the time delay circuit, and the time delay circuit has a time delay effect on the signal with a step of one pulse period. When adjacent k pulse signals pass through the time delay circuit, time delays with a decreasing period of one cycle are sequentially generated, so that the peaks of consecutive k pulses are superimposed at the output end, and a saturated output power k times the original is output. Different saturated output powers are output when k takes different values. The present invention has the characteristics of high saturated output power and adjustable saturated output power, which helps to reduce the complexity and volume of components and is worthy of promotion in the industry.

Description

Technical Field:

[0001] The present invention belongs to the technical field of microwave integrated circuits, and relates to a microwave power amplifier. Background Art:

[0002] Microwave power amplifiers are usually used in transmitters to amplify microwave signals and are core components in systems such as phased array radars, microwave communications, and interstellar aerospace. Microwave power amplifiers based on GaAs and GaN processes in China have made great progress, and higher efficiency, greater power, and better signal amplification capabilities are the goals they pursue.

[0003] The microwave power amplifier is used at the end of the transmitter. It amplifies the modulated signal to a large enough level so that the modulated signal can reach the target distance after being radiated by the antenna. Pulse radars measure the target distance by measuring the time difference between the transmitted and received pulse signals. According to the radar equation P r =(P t G 2 λ 2 σ) / (64π 3 R 4 ), it can be seen that the maximum detection distance R max ∝P t 1 / 4 , that is, when the receiver sensitivity, target scattering interface, antenna gain, and effective area remain unchanged, if the transmit power P t doubles, the maximum detection distance R max becomes about 1.2 times the original. Increasing the saturated output power P o of a single microwave power amplifier can increase the transmit power P t and reduce the number of synthesis paths of microwave power amplifiers in the component. Microwave power amplifiers usually adopt a 2 - 4 - stage amplification structure, which can not only obtain sufficient amplification factors but also maintain stability. Figure 1 The traditional typical 3 - stage amplification structure is shown in o . The output power of the microwave power amplifier gradually exhibits gain compression as the input power increases. When the output power reaches the maximum, it is called the saturated output power P o , and it will not exceed the maximum output power of the last - stage transistor. Limited by factors such as the power density, breakdown voltage, heat dissipation, and size of the last - stage transistor, it is difficult to further increase P o after it reaches a certain value. For example, it is difficult for a pulsed - working Ku - band power amplifier chip based on GaAs process fabricated by MMIC to achieve P o of 15W, and it is difficult for a pulsed - working Ku - band power amplifier chip based on GaN process to achieve P

[0004] At present, the methods for increasing the saturated output power of pulsed microwave power amplifiers are as follows: 1. Increase the operating voltage. For example, by using die chips with high-voltage processes or the Cascode (common-source common-gate) die chip structure to increase the operating voltage of the amplifier, so that the saturated output power is greater under the same current conditions. However, the former relies on process improvement, and the latter increases the design difficulty and the size of the amplifier, both of which will reduce the reliability to a certain extent; 2. Use more transistors in the final stage of the microwave power amplifier, but the design difficulty is greater, the synthesis efficiency is affected, the size becomes larger, and the heat dissipation increases, resulting in poor reliability. The methods currently used are all to increase the saturated output power by increasing the output power of the final-stage transistors of the microwave power amplifier. Summary of the Invention:

[0005] Technical Objective: The objective of the present invention is to increase the saturated output power of pulsed microwave power amplifiers on the premise of the same transistor power density and reliability, thereby increasing the signal transmission distance, reducing the component complexity and volume.

[0006] Technical Solution: The present invention is implemented by the following technical means:

[0007] A pulsed power multiplier microwave power amplifier, characterized in that it includes a pre-stage amplification and matching circuit, a final-stage transistor, a bias circuit, a matching circuit, and a time-delay circuit, which are fabricated using MMIC or HMIC. The pre-stage amplification and matching circuit, the final-stage transistor, the matching circuit, and the time-delay circuit are connected in sequence along the microwave signal transmission direction. The bias circuit provides the pulsed operating voltage required by the final-stage transistor. The pre-stage amplification and matching circuit provides the drive signal for the final-stage transistor. The final-stage transistor amplifies the signal and outputs a high-power pulsed modulation signal. The matching circuit provides the matching between the final-stage transistor and the time-delay circuit. The time-delay circuit has a time-delay effect on the signal, with a step of one pulse period, and the delay time length is controlled by an external signal;

[0008] For the high-power pulsed modulation signal output after being amplified by the final-stage transistor, before the rising edge of the previous pulse reaches the time-delay circuit, the time-delay circuit is set to the mode with a long delay time and remains so until the end of the peak value of this pulse. Then, before the rising edge of the next pulse reaches the time-delay circuit, the delay time of the time-delay circuit is reduced by one step and remains so until the end of the peak value of this pulse. This is continuously repeated. Starting from every k times, a cycle is formed. Then, for k adjacent pulse signals, time delays with a delay time reduced by one period are sequentially generated. Their pulse peak values will reach the output end simultaneously and be superimposed. The microwave power amplifier outputs k times the saturated output power, where k is a positive integer. When k takes different values, different saturated output powers are output.

[0009] Furthermore, the final-stage transistor includes one or more microwave power transistors, and the quantity is determined according to the output power value and the transistor power density.

[0010] Further, the microwave power transistor is an FET or HEMT based on GaAs or GaN technology.

[0011] Further, the time delay circuit is an n-bit time delay device for delaying signal release, and the delay time is adjustable in multiple steps.

[0012] Further, it takes a certain switching time for the time delay circuit to switch to different time delay modes, and this switching time is less than the difference between the pulse period and the pulse width.

[0013] Advantages of the present invention:

[0014] The present invention not only doubles the saturated output power of the pulsed operating microwave power amplifier on the premise of the same transistor power density and reliability, but also enables the microwave power amplifier to output 1, 2,... m (m is a positive integer) times the saturated output power by controlling the time delay circuit. It has the characteristics of large saturated output power and adjustable saturated output power, which helps to reduce the component complexity and volume and is worthy of promotion in the industry. Description of the drawings:

[0015] Figure 1 It is a typical three-stage amplification structure diagram of a traditional power amplifier;

[0016] Figure 2 It is a structural block diagram of the pulsed power multiplier microwave power amplifier proposed by the present invention;

[0017] Figure 3 It is a structural block diagram of Embodiment 1;

[0018] Figure 4 It is a schematic diagram of the matching circuit;

[0019] Figure 5 It is a schematic diagram of the time delay circuit;

[0020] Figure 6 It is an analysis diagram of the working process of Embodiment 1;

[0021] Figure 7 It is a structural block diagram of Embodiment 2;

[0022] Figure 8 It is an analysis diagram of the working process of Embodiment 2;

[0023] Description of the reference numerals: 1 - pre-stage amplification and matching circuit; 2 - final-stage transistor; 3 - bias circuit; 4 - matching circuit; 5 - time delay circuit. Detailed implementation manners:

[0024] The present invention proposes a pulsed power multiplier microwave power amplifier, and the structure is as Figure 2As shown in the figure. The amplifier of the present invention includes a pre-stage amplification and matching circuit 1, a final-stage transistor 2, a bias circuit 3, a matching circuit 4, and a time-delay circuit 5, which are fabricated in the form of MMIC or HMIC. The pre-stage amplification and matching circuit 1, the final-stage transistor 2, the matching circuit 4, and the time-delay circuit 5 are connected in sequence along the microwave signal transmission direction. The bias circuit 3 provides the pulsed operating voltage required by the final-stage transistor 2; the pre-stage amplification and matching circuit 1 provides the drive signal for the final-stage transistor 2; the final-stage transistor 2 amplifies the signal and outputs a high-power pulsed modulation signal; the matching circuit 4 realizes the matching from the final-stage transistor 2 to the time-delay circuit 5 and should have the characteristics of low loss and wide frequency band. The time-delay circuit 5 has a time-delay effect on the signal. Different time-delay path combinations of the time-delay circuit 5 realize multiple time-delay modes, with a step of one pulse period. The time-delay path is selected by an externally applied TTL signal to control the length of the delay time.

[0025] The pulsed modulation signal amplified by the final-stage transistor 2 reaches the time-delay circuit 5 before the rising edge of the previous pulse. Before that, the time-delay circuit 5 has been switched to the mode with a long delay time and remains so until the peak of this pulse ends. Then, before the rising edge of the next pulse reaches the time-delay circuit 5, the delay time of the time-delay circuit 5 decreases by one step and remains so until the peak of this pulse ends. This process is repeated continuously. Every k (k is a positive integer) times, a cycle starts. In this way, adjacent k pulsed signals successively generate a time delay with a delay time reduced by one period. Their pulse peaks will reach the output end simultaneously and be superimposed. The amplifier outputs k times the saturated output power (peak value). When k takes different values, different saturated output powers are output.

[0026] The working principle of the present invention: The microwave signal is amplified by the pre-stage amplification and matching circuit and the final-stage transistor, and then reaches the time-delay circuit through the matching circuit. The DC pulsed voltage is applied to the power amplifier through the bias circuit to control whether it works, realizing pulsed modulation. The pulsed modulation signal amplified by the final-stage transistor reaches the time-delay circuit 5 before the rising edge of the previous pulse. Before that, the time-delay circuit 5 has been set to the mode with a long delay time and remains so until the peak of this pulse ends. Then, before the rising edge of the next pulse reaches the time-delay circuit 5, the delay time of the time-delay circuit 5 decreases by one step and remains so until the peak of this pulse ends. This process is repeated continuously. Every k (k is a positive integer) times, a cycle starts. In this way, adjacent k pulsed signals successively generate a time delay with a delay time reduced by one period. Their pulse peaks will reach the output end simultaneously and be superimposed, so that the amplifier outputs k times the saturated output power (peak value). The time-delay circuit has multiple time-delay modes and can perform the above operations on m (m is a positive integer) consecutive pulses. In this way, the peak values of 1, 2,..., m consecutive pulses can be superimposed by controlling the signal, realizing m-level adjustable saturated output power.

[0027] Embodiment 1:

[0028] The structural block diagram of Embodiment 1 is shown in Figure 3The amplifier operates under a pulsed voltage with a period T and a pulse width τ = T / 2. The microwave input signal is jointly processed by the pre-stage amplification and matching circuit 1, the final-stage transistor 2, the bias circuit 3, and the matching circuit 4, and the output power is P out of the pulsed modulation signal with a period T and a pulse width τ. The schematic diagram of the matching circuit 4 is as shown in Figure 4 which is a passive matching circuit, realizing the matching from the final-stage transistor 2 with four cells to the delay circuit 5, with low loss and wide frequency band. The delay circuit 5 is implemented by switching different delay paths as shown in Figure 5 . The delay circuit sub-unit is an SPDT switch-type constant-resistance network. When the switch selects the λ / 4 constant-resistance network, it works in the delay state, having good delay accuracy and amplitude fluctuation; when the switch selects the common path, it works in the reference state. Multiple such sub-units constitute the delay circuit. The switching time t s between the delay state and the reference state is ≤ T - τ. When the delay circuit works in the delay state, the delay time is 3T / 2, including a delay network with a delay time of T, a switch response time of T / 2, and the common path; when the delay circuit works in the reference state, the delay time is T / 2, including the switch response time and the common path. In this way, the signal transmission time in the delay state lags behind that in the reference state by one cycle T

[0029] The working process analysis of the first embodiment is as shown in Figure 6 . The initial pulsed modulation signal between the final-stage transistor 2 and the delay circuit 5 has a period of T, a pulse width of τ, and a peak power of P out . Before the rising edge of the first pulse C1 (appearing at T / 2) reaches the delay circuit 5, the delay circuit 5 works in the delay state and reaches the output end at 4T / 2, with a duration of τ; when the falling edge of the first pulse C1 appears, the input of the delay circuit 5 switches to the reference state, and the switching time is less than T - τ. In this way, the second pulse C2 (the rising edge appears at 3T / 2) passes through a delay of T / 2 and reaches the output end at 4T / 2, with a duration of τ. When the falling edge of the second pulse C2 appears, the input of the delay circuit 5 switches back to the delay state again, and the switch switching time is less than T - τ. The third pulse C3 (the rising edge appears at 5T / 2) passes through a delay of 3T / 2 and reaches the output end at 8 / 2T, with a duration of τ... and so on. The peaks of the (2N - 1)-th pulse C 2N-1 and the 2N-th pulse C 2N always reach the output end simultaneously, and the output power is 2P out , with a period of 2T and a pulse width of τ. If the delay circuit 5 always works in the reference state or the delay state, the output power at the output end is P out , with a period of T and a pulse width of τ. It realizes that under the premise of the same transistor power density and reliability, the saturated output power of the pulsed working microwave power amplifier doubles, and the saturated output power can be adjusted in two gears

[0030] Embodiment 2:

[0031] The structural block diagram of Embodiment 2 is shown in Figure 7 . The implementation manners of the pre-stage amplification matching circuit 1, the final-stage transistor 2, the bias circuit 3, and the matching circuit 4 in Embodiment 2 are the same as those in Embodiment 1, and the working voltage is still a pulse voltage with a period T and a pulse width τ = T / 2. The time-delay circuit 5 is a three-bit time-delay circuit, which is composed of three identical time-delay modules a1, a2, and a3 connected in series. In each time-delay module, the reference-state delay is T / 4, the delay-state delay is 5T / 4 (including the common-path delay), and the mode conversion time is T / 4. In this way, the signal transmission time of the delay state of each time-delay module lags behind that of the reference state by one period T.

[0032] The working process analysis of Embodiment 2 is as follows Figure 8 shown. The initial pulse modulation signal between the final-stage transistor 2 and the time-delay circuit 5 has a period of T, a pulse width of τ, and a peak power of P out . Before the rising edge of the first pulse C1 (appearing at T / 2) reaches the time-delay circuit 5, a1, a2, and a3 are all in the delay state. After being delayed by 5T / 4 by a1, it reaches a2 at 7T / 4, and the falling edge of C1 leaves a1 and enters a2 at 9T / 4; at 5T / 4, the input of a1 switches to the reference state (at this time, the peak value of the first pulse C1 has been transmitted in the delay path of a1), and the rising edge of the second pulse C2 (appearing at 3T / 2) is delayed by T / 4 by a1 and reaches a2 at 7T / 4, and the falling edge of C1 leaves a1 and enters a2 at 9T / 4; at 10T / 4, the input of a2 switches to the reference state (at this time, the peak values of C1 and C2 have been transmitted in the delay path of a2), and the rising edge of the third pulse C3 (appearing at 5T / 2) is delayed by T / 4 by a1 and reaches a2 at 11T / 4, and reaches a3 at 12T / 4 after being delayed by T / 4 in the reference state of a2. C1 and C2 also reach a3 at 12T / 4 after being delayed by 5T / 4 in the delay state of a2, and their falling edges all reach a3 at 14T / 4; at 15T / 4, the input of a3 switches to the reference state (at this time, the peak values of C1, C2, and C3 have been transmitted in the delay path of a3), and the rising edge of the fourth pulse C4 (appearing at 7T / 2) is delayed by 2T / 4 by a1 and a2 and reaches a3 at 16T / 4, and reaches the output end at 17T / 4 after being delayed by T / 4 in the reference state of a3. C1, C2, and C3 also reach the output end at 17T / 4 after being delayed by 5T / 4 in the delay state of a3, and the output power is 4P out。At 20T / 4, the a1 input switches to the delay state, and at 25T / 4, the a2 input switches to the delay state, and so on, repeating continuously. In this way, the peak values of the 4N-3rd, 4N-2nd, 4N-1st, and 4Nth (N is a positive integer) pulses can all complete the path switching before the rising edge arrives, and the complete pulse transmission is not blocked. Four consecutive pulses will pass through 3 delay states, 1 reference state, 2 delay states, 2 reference states, 1 delay state, and 3 reference states in sequence and reach the output terminal simultaneously, outputting 4P out 。Specifically, if the delay circuit 5 only performs mode switching between adjacent two delay modules, the output power at the output terminal is 3P out , with a period of 3T and a pulse width of τ, and so on. In the second embodiment, on the premise of the same transistor power density and reliability, the saturated output power of the pulsed operating microwave power amplifier becomes 4 times, 3 times, 2 times, and 1 time of the original respectively, and the saturated output power is adjustable in four gears.

[0033] It should be noted that: The amplifier disclosed in the present invention is not limited to the embodiments. The specific parameters given in the embodiments are only given as a definite value for convenience of explanation, and they can be other values that satisfy the principles described in the present invention. For example, the pulse width τ does not have to be T / 2 necessarily, and can be any positive value smaller than T; the delay of the delay circuit does not have to be 3T / 4 necessarily, and can be any positive value.

[0034] It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content described in the present invention, those skilled in the art can make various improvements or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

Claims

1. A pulse power multiplication type microwave power amplifier, characterized in that: It includes a pre - amplifier matching circuit (1), a final - stage transistor (2), a bias circuit (3), a matching circuit (4) and a time - delay circuit (5), which are fabricated using MMIC or HMIC. The pre - amplifier matching circuit (1), the final - stage transistor (2), the matching circuit (4) and the time - delay circuit (5) are connected in sequence along the microwave signal transmission direction. The bias circuit (3) provides the pulsed operating voltage required by the final - stage transistor (2). The pre - amplifier matching circuit (1) provides the drive signal for the final - stage transistor (2). The final - stage transistor (2) amplifies the signal and outputs a high - power pulsed modulation signal. The matching circuit (4) provides the matching between the final - stage transistor (2) and the time - delay circuit (5). The time - delay circuit (5) has a time - delay effect on the signal, with a step of one pulse period, and the delay time length is controlled by an external signal. For the high - power pulsed modulation signal output after being amplified by the final - stage transistor (2), before the rising edge of the previous pulse reaches the time - delay circuit (5), the time - delay circuit (5) is set to the mode with a long delay time and remains in this state until the peak of this pulse ends. Then, before the rising edge of the next pulse reaches the time - delay circuit (5), the delay time of the time - delay circuit (5) decreases by one step and remains in this state until the peak of this pulse ends. This process is repeated continuously. Starting to cycle every k times, the adjacent k pulsed signals will successively generate a time - delay with the delay time decreasing by one period. Their pulse peaks will reach the output end simultaneously and be superimposed. The microwave power amplifier outputs k times the saturated output power, where k is a positive integer. When k takes different values, different saturated output powers are output.

2. The pulse power multiplier type microwave power amplifier according to claim 1, wherein: The final - stage transistor (2) includes one or more microwave power transistors, and the quantity is determined according to the output power value and the transistor power density.

3. The pulse power multiplier type microwave power amplifier according to claim 2, characterized in that: The microwave power transistor is an FET or HEMT based on GaAs or GaN technology.

4. The pulse power multiplication type microwave power amplifier according to claim 1, characterized in that: The time - delay circuit (5) is an n - bit time - delay device for delaying the signal release, and the delay time is adjustable in multiple steps.

5. The pulse power multiplier type microwave power amplifier according to claim 1 or 4, characterized in that: The time - delay circuit (5) requires a certain switching time to switch to different time - delay modes, and this switching time is less than the difference between the pulse period and the pulse width.

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