GOS substrate, short-wave infrared focal plane pixel and preparation method thereof

Abstract

The present invention relates to a GOS substrate, a short-wave infrared focal plane pixel and a preparation method thereof. A GOS substrate comprises SiN x layer, doped polysilicon layer, sapphire substrate, dielectric stack layer, selective epitaxial growth germanium layer, wherein x≠0. The preparation method comprises: forming a first dielectric layer on a silicon substrate; forming a plurality of grooves on the first dielectric layer; after forming the plurality of grooves, sequentially forming a low-temperature germanium layer and a high-temperature germanium layer on the first dielectric layer until the grooves are covered to a certain thickness; forming a second dielectric layer to obtain a sacrificial substrate; forming a doped polysilicon layer, SiN on the front side of the sapphire substrate; x The invention solves the problems of large lattice mismatch and high thermal mismatch in epitaxial growth of III-V materials, improves device responsiveness and reduces dark current.

Description

Technical Field

[0001] The invention relates to the field of semiconductors, and in particular to a GOS substrate, a short-wave infrared focal plane pixel and a preparation method thereof. Background Art

[0002] The short-wave infrared focal plane based on the III-V short-wave infrared material system has the characteristics of high sensitivity, high uniformity, and high stability, and its response band can cover the range of 0.9 to 3.0 μm. However, the commercialized III-V short-wave infrared focal plane faces the disadvantages of small wafer size, high manufacturing cost, and small array scale. It is an inevitable trend to replace the high-cost small-size substrate with a low-cost large-size substrate. Sapphire substrates not only have the characteristics of large size and mature manufacturing process, but also have the advantages of low cost. Therefore, realizing high-performance III-V short-wave infrared focal planes on sapphire substrates is one of the important technical approaches to support the development of low-cost short-wave infrared imaging technology. The technical difficulty lies in the large lattice mismatch and high thermal mismatch faced by epitaxial III-V short-wave infrared materials directly on sapphire substrates.

[0003] To this end, the present invention is proposed. Summary of the invention

[0004] The main purpose of the present invention is to provide a GOS substrate, a short-wave infrared focal plane pixel and a method for preparing the two, which solves the problems of large lattice mismatch and high thermal mismatch in the epitaxial growth of III-V materials, improves the quality of III-V epitaxial materials and the responsiveness of devices such as short-wave infrared focal plane pixels based thereon, and reduces the dark current of the device.

[0005] In order to achieve the above objectives, the present invention provides the following technical solutions.

[0006] The first aspect of the present invention provides a GOS substrate, comprising a SiN x layer, doped polysilicon layer, sapphire substrate, dielectric stack layer, selective epitaxial growth germanium layer, where x≠0.

[0007] Whether compared with an ordinary GOI substrate or a III-V-OI substrate, the GOS substrate provided by the present invention can improve the quality of the III-V materials epitaxially grown thereon due to its high crystal quality, reduce the defect density, and avoid the problems of large lattice mismatch and high thermal mismatch.

[0008] In addition, the present invention can also achieve the following effects due to the above-mentioned specific laminated structure:

[0009] On the one hand, the dielectric stack layer in the GOS substrate provided by the present invention has a resonant cavity effect, which can significantly improve the responsivity when used for short-wave infrared focal plane pixels;

[0010] On the other hand, adding a doped polysilicon layer on the sapphire substrate can give it optical and electrical properties similar to those of silicon wafers. These properties can be recognized by device processing equipment using silicon wafers as substrates, thus avoiding the incompatibility problem of processing equipment.

[0011] On the other hand, since semiconductor devices such as short-wave infrared focal plane pixels involve wet etching or other corrosion steps during processing, the corrosion is likely to damage the doped polysilicon layer, and the present invention adds SiN x The layer can avoid the above damage problems and improve the quality and reliability of the device.

[0012] The dielectric stack layer in the present invention can be a stack of multiple dielectric materials, or a multi-layer stack of the same dielectric material.

[0013] For example, in some embodiments, the dielectric stack layer is a stack of multiple silicon oxide layers, or a cross stack of silicon oxide and aluminum oxide, or a stack of multiple aluminum oxide layers.

[0014] In some embodiments, the dielectric stack layer includes a silicon oxide layer and an aluminum oxide layer, and the silicon oxide layer is close to the sapphire substrate.

[0015] In some embodiments, the thickness of the selective epitaxially grown germanium layer is 100-500 nm.

[0016] In some embodiments, the thickness of the doped polysilicon layer is greater than 2000 nm, and the resistance is preferably 0.001-1000 Ohm·cm. Polysilicon layers of this nature can be accurately identified by existing wafer processing equipment.

[0017] In some embodiments, the SiN x The thickness of the layer is 50 to 500 nm, which can fully protect the doped polysilicon from corrosion.

[0018] A second aspect of the present invention provides a method for preparing a GOS substrate, comprising:

[0019] providing a silicon substrate;

[0020] forming a first dielectric layer on the silicon substrate;

[0021] forming a plurality of grooves on the first dielectric layer;

[0022] After forming a plurality of grooves, forming a low-temperature germanium layer and a high-temperature germanium layer in sequence on the first dielectric layer until the grooves are covered to a certain thickness;

[0023] forming a second dielectric layer on the high temperature germanium layer to obtain a sacrificial substrate;

[0024] Providing a sapphire substrate;

[0025] On the front side of the sapphire substrate, a doped polysilicon layer, a SiN x layer, and forming a third dielectric layer on the back side of the sapphire substrate to obtain a supporting substrate;

[0026] Bonding the sacrificial substrate to the supporting substrate using the second dielectric layer and the third dielectric layer as bonding surfaces;

[0027] Then, the silicon substrate, the first dielectric layer, and the low-temperature germanium layer are removed in sequence;

[0028] Optionally, the surface of the high temperature germanium layer is subjected to CMP treatment.

[0029] The above method achieves the effect of epitaxially growing a germanium layer on an ordinary silicon substrate by influencing crystal growth through deep trenches. By reasonably controlling the size of the trenches, etc., the crystal quality of germanium can be greatly improved, providing a prerequisite for the subsequent epitaxial growth of high-quality III-V materials.

[0030] On the other hand, the present invention transfers the germanium layer to the silicon-free substrate by forming a bond, which can greatly improve the quality of the high-temperature germanium layer and greatly reduce the defect density.

[0031] At the same time, as mentioned above, the process may also have the following advantages: it is adaptable to processing equipment for silicon wafers and the doped polysilicon layer is not easily corroded.

[0032] In some embodiments, the aspect ratio of the trench is ≤2.

[0033] In some embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer are each independently made of at least one of silicon oxide, aluminum oxide, or TEOS;

[0034] And / or, the third dielectric layer is a stacked layer of multiple layers of materials.

[0035] All the above-mentioned dielectric stacking layers in various forms have good resonant cavity effects.

[0036] The third dielectric layer is also a stack of multiple layers of materials, which can further reduce the adverse effects of bonding on the high temperature germanium layer and improve the resonant cavity effect. The first dielectric layer is also used for the groove, so the groove etching factor is also required when selecting the material.

[0037] In some embodiments, the second dielectric layer is formed by ALD method; for example, aluminum oxide is formed as the second dielectric layer by ALD method.

[0038] And / or, the third dielectric layer is formed by at least one of thermal oxidation and CVD. When the third dielectric layer is a multi-layer material stack, a silicon oxide layer can be first formed by thermal oxidation on a silicon substrate, and then a silicon oxide or other material layer can be formed by CVD.

[0039] In some embodiments, the silicon substrate is removed by grading or dry etching;

[0040] And / or, the low temperature germanium layer is removed by TMAH etching.

[0041] The above embodiments adopt appropriate methods for removing different materials, which is beneficial to reducing the adverse effects on the substrate and improving the process efficiency.

[0042] In some embodiments, the growth temperature of the high temperature germanium layer is 550-750°C, and the growth temperature of the low temperature germanium layer is 350-450°C.

[0043] A third aspect of the present invention provides a short-wave infrared focal plane pixel, comprising:

[0044] The GOS substrate described above;

[0045] a GaAs buffer layer disposed on the substrate;

[0046] The PIN stack structure located on the GaAs buffer layer, and the PIN stack structure adopts III-V group materials, mainly preferably including: N + -InGaAs / I-InGaAs / P + -InGaAs, N + -InP / I-InGaAs / P + -InP,P + -GaAsSb / I-InGaAs / N + -InP,N + -GaAs / I-AlGaAs / InGaAs multiple quantum well / P + -GaAs, N + -GaAs / I-AlGaAs / InGaAs multiple quantum dots / P + -GaAs, etc.;

[0047] And an N-type contact structure and a P-type contact structure which respectively realize ohmic contact with the N layer and the P layer in the PIN stack structure.

[0048] The short-wave infrared focal plane pixel uses the GOS substrate mentioned above as the substrate, so the grown III-V PIN stack structure must have high quality, without large lattice mismatch, high thermal mismatch and other problems, and the response is improved and the dark current is reduced. At the same time, GaAs is used as a buffer layer in this scheme to further improve the crystal quality.

[0049] In some embodiments, the PIN stacking structure is a vertical stacking structure.

[0050] Of course, the present invention does not exclude a horizontally stacked PIN structure.

[0051] In addition, the order of the PIN vertical stacking structure can be PIN from bottom to top, or NIP.

[0052] A fourth aspect of the present invention provides a method for preparing the above-mentioned short-wave infrared focal plane pixel, comprising:

[0053] First, a GOS substrate is obtained by using the GOS substrate preparation method described above;

[0054] forming a GaAs buffer layer on the GOS substrate;

[0055] forming a PIN stack structure on the GaAs buffer layer;

[0056] The N-type contact structure and the P-type contact structure are formed respectively.

[0057] In some embodiments, a GaAs buffer layer is formed by a three-step method of low temperature-medium temperature-high temperature, and the ranges of low temperature, medium temperature and high temperature are 390-410°C, 580-610°C and 660-680°C respectively, and the ranges of low temperature, medium temperature and high temperature are preferably 400°C, 600°C and 670°C.

[0058] In some embodiments, after forming the N-type contact structure and the P-type contact structure, the method further includes: forming a two-dimensional crystal. The two-dimensional crystal can improve the responsiveness.

[0059] In some embodiments, before forming the N-type contact structure and the P-type contact structure, the method further includes: patterning the PIN stack structure to form a mesa; the mesa exposes the layer of the PIN stack structure close to the GaAs buffer layer. The device patterning process of this structure is simpler, and there is no need to etch structures that are prone to defects such as contact holes.

[0060] In summary, compared with the prior art, the present invention achieves the following technical effects: on the one hand, a high-quality GOS substrate is obtained by influencing crystal growth through grooves; on the other hand, a high-quality epitaxial III-V short-wave infrared focal plane pixel is obtained based on this substrate, which has a higher responsivity and a smaller dark current; on the other hand, all process flows and structures are compatible with the process equipment of existing silicon wafer devices, and have the advantages of low cost and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the following detailed description of the preferred embodiment.The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the invention.

[0062] Figure 1-12 A schematic diagram of the structure obtained by each step of the preparation method of the GOS substrate provided by the present invention;

[0063] Figure 13-17 This is a schematic diagram of the structure obtained by each step of the method for preparing a short-wave infrared focal plane pixel provided by the present invention. DETAILED DESCRIPTION

[0064] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0065] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0066] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0067] Currently, III-V short-wave infrared focal plane pixels are limited by the quality of the substrate crystal and cannot avoid problems such as large lattice mismatch and high thermal mismatch, resulting in poor key indicators such as device responsiveness and dark current.

[0068] To this end, the present invention provides a GOS substrate and a preparation method thereof, as well as a short-wave infrared focal plane pixel based on the substrate and a preparation method thereof.

[0069] The key to the structure of the GOS substrate provided by the present invention is the crystal quality of the germanium layer, and its structure includes SiN x layer, doped polysilicon layer, sapphire substrate, dielectric stack layer, selective epitaxial growth germanium layer, where x≠0.

[0070] In order to obtain the above high-quality GOS substrate, the preparation process provided by the present invention mainly includes four key stages: making a sacrificial substrate, making a supporting substrate, bonding, and removing excess layers, which are specifically as follows.

[0071] 1. Making a sacrificial substrate

[0072] First, a silicon substrate is provided.

[0073] Then, a first dielectric layer, preferably a silicon oxide layer, is formed on the silicon substrate for etching trenches.

[0074] Next, a plurality of trenches are formed in the first dielectric layer.

[0075] Afterwards, a low-temperature germanium layer and a high-temperature germanium layer are formed on the groove until the groove is covered to a certain thickness. In this step, the growth temperatures of the low-temperature germanium layer and the high-temperature germanium layer can refer to the range of 350-450°C and 550-750°C, respectively. At the same time, if high-temperature annealing or cyclic annealing is added, the crystal quality can be further improved. Of course, annealing can be performed after the formation of the subsequent second dielectric layer. The annealing temperature is preferably controlled at 820°C, the annealing time is 10 minutes, and the annealing atmosphere is H2. In addition, since the groove will be completely removed after bonding, the high-temperature germanium layer should have sufficient thickness.

[0076] Next, a second dielectric layer is formed on the high temperature germanium layer to obtain a sacrificial substrate. The second dielectric layer can be an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer, or a stack of these layers. When selecting its material, the resonant cavity effect should be considered on the one hand, and the difficulty and stability when bonding to the supporting substrate should also be considered on the other hand. For this reason, the present invention preferably uses aluminum oxide.

[0077] 2. Making the Supporting Substrate

[0078] First, provide sapphire substrates. Sapphire substrates have the characteristics of large size and mature manufacturing process, as well as high resistivity, low radio frequency (RF) loss, strong crosstalk suppression capability, and strong radiation resistance.

[0079] Then, a doped polysilicon layer, a SiN layer, and a xA layer is formed, and a third dielectric layer is formed on the back of the sapphire substrate to obtain a supporting substrate. x The ratio of silicon to nitrogen can be adjusted adaptively to meet different mask requirements.

[0080] In the preparation of the above-mentioned sacrificial substrate and supporting substrate, the means of forming each dielectric layer include but are not limited to CVD, ALD, PCVD, PECVD, thermal oxidation and the like.

[0081] 3. Bonding

[0082] The sacrificial substrate and the supporting substrate are bonded with the second dielectric layer and the third dielectric layer as bonding surfaces, usually by melt bonding.

[0083] 4. Remove extra layers

[0084] The silicon substrate, the first dielectric layer, and the low-temperature germanium layer are removed in sequence. The removal means include but are not limited to CMP, dry etching, wet etching, etc. or a combination of multiple means. It is preferred to use different means for different materials, such as using grading or dry etching to remove the silicon substrate, and using TMAH etching to remove the first dielectric layer and the low-temperature germanium layer.

[0085] Afterwards, the surface of the high temperature germanium layer is optionally planarized to reduce the roughness, usually by means of CMP.

[0086] When the GOS substrate obtained above is used to make short-wave infrared focal plane pixels, the subsequent process also includes the following main steps:

[0087] First, a GaAs buffer layer is formed on the GOS substrate. The GaAs buffer layer is preferably formed by a three-step method of low temperature-medium temperature-high temperature, and the ranges of low temperature, medium temperature and high temperature are 390-410°C, 580-610°C and 660-680°C respectively, and the ranges of low temperature, medium temperature and high temperature are preferably 400°C, 600°C and 670°C.

[0088] Then, a PIN stacking structure is formed on the GaAs buffer layer. The stacking structure can be horizontal or vertical, and the order of the P-type layer and the N-type layer is arbitrary. Meanwhile, the PIN stacking structure of the present invention adopts III-V group materials.

[0089] Then, the N-type contact structure and the P-type contact structure are formed respectively. The contact structure is an ohmic contact, which can be in the form of a table or a contact hole, preferably a table.

[0090] Finally, a two-dimensional crystal is optionally formed.

[0091] Based on the core of the solution described above, the present invention also provides the following preferred embodiments.

[0092] Example 1 Preparation of GOS substrate

[0093] Making sacrificial substrate stage:

[0094] Step S1, forming a silicon oxide layer 2 on a silicon substrate 1, such as Figure 1 shown.

[0095] Step S2, etching the silicon oxide layer 2 to form a plurality of grooves 2a, such as Figure 2 As shown. Etching can be performed by typical means in the art. The depth-to-width ratio of the groove is ≤2.

[0096] Step S3, first grow low-temperature germanium in the trench 2a, then grow high-temperature germanium to form a germanium layer 3, such as Figure 3 The growth temperatures of low temperature and high temperature are 350-450℃ and 550-750℃ respectively.

[0097] Step S4, forming an aluminum oxide layer 4 on the germanium layer 3 by using an ALD method to obtain a sacrificial substrate, such as Figure 4 shown.

[0098] Making supporting substrate stage:

[0099] Step S5, forming a polysilicon layer on the front side of the sapphire substrate 5, and then doping it to form a doped polysilicon layer 6, such as Figure 5 The doping concentration, depth and type are not limited, as long as the electrical properties and optical shape can be recognized by silicon wafer processing. The doping type can be N-type or P-type. The thickness of the polysilicon layer can be selected to be above 2000nm to meet the recognition requirements of most equipment, and the resistance after doping can reach 0.001~1000Ohm·cm.

[0100] Step S6, as Figure 6 , SiN is formed on the doped polysilicon layer 6 x Layer 7, which may have a thickness of 50 to 500 nm, is used to protect polysilicon.

[0101] Step S7, forming a silicon oxide layer on the back of the sapphire substrate 5, can be deposited first a layer of silicon 8, such as Figure 7 Then a silicon oxide layer 9 is formed by thermal oxidation, such as Figure 8 shown.

[0102] Step S8, forming a TEOS layer 10 on the silicon oxide layer 9 by using a TEOS method to obtain a supporting substrate, such as Fig. 9 shown.

[0103] Bonding and removal of excess layers:

[0104] Step S9, using the aluminum oxide layer 4 and the TEOS layer 10 as bonding surfaces, melt-bonding the sacrificial substrate and the supporting substrate, as shown in FIG. Fig.10 shown.

[0105] Step S10, then polishing or dry etching to remove the silicon substrate 1, such as Fig.11 shown.

[0106] Step S11, the low temperature germanium layer and the silicon oxide layer 2 in the germanium layer are removed by TMAH etching. Fig.12 As shown;

[0107] Step S12, CMP treatment is performed on the surface of the germanium layer 3 until the thickness reaches 100-500 nm, and the defect density can be as low as 10 7 cm -2 Magnitude.

[0108] Example 2: Making short-wave infrared focal plane pixels

[0109] In the first step, a GaAs buffer layer 11 is formed on the GOS substrate obtained in Example 1. Fig.13 As shown; the formation method is a three-step process of low temperature (400°C) - medium temperature (600°C) - high temperature (670°C).

[0110] In the second step, a PIN stack structure is formed on the GaAs buffer layer 11: from bottom to top: a P-type III-V group material layer 12, a III-V group short-wave infrared absorption layer 13, and an N-type III-V group material layer 14, such as Fig.14 shown.

[0111] The third step is to graphically process the PIN stack structure, such as Fig.15 As shown, a table is formed.

[0112] The fourth step is to perform surface passivation treatment on the formed PIN stacking table, and the passivation layer is 15, such as Fig.16 shown.

[0113] The fifth step is to form the N-type contact structure and the P-type contact structure respectively: a contact hole is etched in the passivation layer, so as to deposit metals 16 and 17 at the exposed parts of the P-type III-V material layer 12 and the N-type III-V material layer 14, as shown in FIG. Fig.17 shown.

[0114] The sixth step is to form a two-dimensional crystal, which is not shown in the figure and can be adjusted appropriately according to actual needs.

[0115] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for preparing a GOS substrate, characterized in that: include: providing a silicon substrate; forming a first dielectric layer on the silicon substrate; forming a plurality of grooves on the first dielectric layer; After forming a plurality of grooves, a low-temperature germanium layer and a high-temperature germanium layer are sequentially formed on the first dielectric layer by a selective epitaxial growth method until the grooves are covered to a certain thickness; the growth temperature of the high-temperature germanium layer is 550-750° C., and the growth temperature of the low-temperature germanium layer is 350-450° C.; forming a second dielectric layer on the high temperature germanium layer to obtain a sacrificial substrate; Providing a sapphire substrate; On the front side of the sapphire substrate, a doped polysilicon layer, a SiN x layer, and forming a third dielectric layer on the back side of the sapphire substrate to obtain a supporting substrate; Bonding the sacrificial substrate to the supporting substrate using the second dielectric layer and the third dielectric layer as bonding surfaces; Then, the silicon substrate, the first dielectric layer and the low-temperature germanium layer are removed in sequence.

2. The preparation method according to claim 1, characterized in that: The surface of the high temperature germanium layer is subjected to CMP treatment.

3. The preparation method according to claim 1, characterized in that: The aspect ratio of the groove is ≤2.

4. The preparation method according to claim 1, characterized in that: The first dielectric layer, the second dielectric layer, and the third dielectric layer are each independently made of at least one of silicon oxide, aluminum oxide, or TEOS; And / or, the third dielectric layer is a stacked layer of multiple layers of materials.

5. The preparation method according to claim 1, characterized in that: forming the second dielectric layer by adopting ALD method; And / or, the third dielectric layer is formed by at least one of a thermal oxidation method and a CVD method.

6. The preparation method according to claim 1, characterized in that: removing the silicon substrate by grinding and polishing or dry etching; And / or, the first dielectric layer and the low-temperature germanium layer are removed by TMAH etching.

7. A GOS substrate obtained by the preparation method according to claim 1, characterized in that: Including bottom-up SiN x layer, doped polysilicon layer, sapphire substrate, dielectric stack layer, selective epitaxial growth germanium layer, where x≠0.

8. The GOS substrate according to claim 7, characterized in that: The dielectric stack layer is a stack of multiple layers of silicon oxide, or a cross stack of silicon oxide and aluminum oxide, or a stack of multiple layers of aluminum oxide.

9. The GOS substrate according to claim 7, characterized in that: The thickness of the doped polysilicon layer is above 2000nm, and the resistance reaches 0.001-1000Ohm·cm.

10. The GOS substrate according to any one of claims 7 to 9, characterized in that: The SiN x The thickness of the layer is 50 to 500 nm.

11. A short-wave infrared focal plane pixel, characterized in that: include: The GOS substrate according to any one of claims 7 to 10; a GaAs buffer layer located on the substrate; A PIN stack structure is located on the GaAs buffer layer, and the PIN stack structure adopts III-V group materials.

12. The shortwave infrared focal plane pixel according to claim 11, characterized in that: The PIN stacking structure is: N + -InGaAs / I-InGaAs / P + -InGaAs,N + -InP / I-InGaAs / P + -InP,P + -GaAsSb / I-InGaAs / N + -InP,N + -GaAs / I-AlGaAs / InGaAs multi-quantum well / P + -GaAs,N + -GaAs / I-AlGaAs / InGaAs multi-quantum dots / P + -GaAs; And an N-type contact structure and a P-type contact structure which respectively realize electrical contact with the N layer and the P layer in the PIN stack structure.

13. The shortwave infrared focal plane pixel according to claim 11, characterized in that: The PIN stacking structure is a vertical stacking structure.

14. A method for preparing a short-wave infrared focal plane pixel according to claim 11, 12 or 13, characterized in that: include: Obtaining a GOS substrate using the preparation method described in any one of claims 1 to 6; forming a GaAs buffer layer on the GOS substrate; forming a PIN stack structure on the GaAs buffer layer; An N-type contact structure and a P-type contact structure are formed respectively.

15. The preparation method according to claim 14, characterized in that: The GaAs buffer layer is formed by a three-step method of low temperature, medium temperature and high temperature, and the ranges of the low temperature, medium temperature and high temperature are 390-410° C., 580-610° C. and 660-680° C. respectively.

16. The preparation method according to claim 15, characterized in that: The low temperature, medium temperature and high temperature are 400° C., 600° C. and 670° C. respectively.

17. The preparation method according to claim 14, characterized in that: After forming the N-type contact structure and the P-type contact structure, the method further includes: forming a two-dimensional crystal.

18. The preparation method according to claim 14, characterized in that: Before forming the N-type contact structure and the P-type contact structure, the method further includes: patterning the PIN stack structure to form a mesa; the mesa exposes a layer of the PIN stack structure close to the GaAs buffer layer.

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