A DMD maskless lithography superconducting quantum chip method, device, system and medium

Abstract

The invention belongs to the technical field of chip manufacturing, and relates to a DMD maskless lithography superconducting quantum chip method, comprising the following steps: importing a chip layout, and arranging a plurality of chip layouts in an array to obtain a cutting file; selecting a first exposure time range based on a substrate material and a size of the chip layout, and based on the first exposure time range, respectively specifying different exposure dwell times for the chip layouts in the cutting file, performing first exposure and development, and obtaining a first group of chip graphics; observing the first group of chip graphics, judging the exposure effect, and optimizing the first exposure time range to obtain a second exposure time range; based on the second exposure time range, re-specifying different exposure dwell times for the chip layouts in the cutting file, performing second exposure and development, and obtaining a second group of chip graphics; observing the second group of chip graphics, judging the exposure effect, and determining the exposure dwell time.

Description

Technical Field

[0001] The invention belongs to the technical field of chip manufacturing, and relates to a DMD maskless photolithography superconducting quantum chip method, device, system and medium. Background Art

[0002] At present, the basic process of pattern production in the process of superconducting quantum chip processing is as follows: substrate coating, baking and curing, exposure, development, washing, and etching. In the prior art, common photolithography methods are ultraviolet exposure technology and laser direct writing technology. Ultraviolet exposure requires a mask. The parallelism between the mask and the substrate, mask defects, etc. will affect the accuracy of the exposure pattern. The mask cost is high, and the mask production process is not environmentally friendly. The laser direct writing equipment is expensive, the exposure time is long, the edge of the substrate is not easy to focus, and the substrate flatness and coating uniformity affect the exposure accuracy.

[0003] In the photolithography process, different substrates, photoresists, etc. will affect the exposure effect. During the research and development and processing process, the above technical methods have disadvantages such as long exposure time and high equipment or mask costs, which are not conducive to the rapid development and iteration of chips. Summary of the invention

[0004] The purpose of the present invention is to provide a DMD maskless lithography method, device, system and medium for superconducting quantum chip in view of the deficiencies in the prior art. The DMD maskless lithography technology used in the production of micron-level structural patterns in superconducting quantum chips can meet the requirements of fast exposure of large-area and large-size patterns through process optimization, and under certain parameter control, can also meet the requirements of small-size exposure accuracy at the same time, which is more conducive to the research and development and iteration of superconducting quantum chips.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A DMD maskless lithography superconducting quantum chip method comprises the following steps:

[0007] Import the chip layout and arrange multiple chip layouts in an array to obtain a cutting file;

[0008] Based on the substrate material and the size of the chip layout, a first exposure time range is selected, and based on the first exposure time range, different exposure dwell times are respectively specified for the chip layout in the cutting file, and a first exposure and development are performed to obtain a first set of chip patterns;

[0009] Observe the first group of chip patterns, determine the exposure effect, and optimize the first exposure time range to obtain a second exposure time range;

[0010] Based on the second exposure time range, re-specify a different exposure dwell time for the chip layout in the cutting file, perform a second exposure and development, and obtain a second set of chip patterns;

[0011] Observe the second group of chip patterns, judge the exposure effect, and determine the exposure dwell time.

[0012] Furthermore, the cutting file may include a plurality of different chip layouts.

[0013] Furthermore, the first exposure and the second exposure are both performed using a DMD maskless lithography machine.

[0014] Furthermore, observing the first group of chip patterns, determining the exposure effect, and optimizing the first exposure time range to obtain the second exposure time range includes the following steps:

[0015] Observe the patterns corresponding to different exposure dwell times in the first group of chip patterns to determine whether there is incomplete exposure or a long exposure time;

[0016] Taking the time nodes adjacent to the incomplete exposure and the overexposure of the graphic as the upper and lower bounds of the second exposure time interval, respectively, to obtain the second exposure time interval;

[0017] According to the second exposure time interval, a different exposure dwell time is re-specified for the chip layout of the cut file, and exposure and development are performed to obtain a second set of chip patterns;

[0018] Observe the patterns corresponding to different exposure dwell times in the second group of chip patterns to determine the exposure dwell time of the chip layout.

[0019] Further, observing the patterns corresponding to different exposure dwell times in the first group of chip patterns to determine whether there is incomplete exposure or a long exposure time includes the following steps:

[0020] Acquire images of the first group of chip patterns, and sequentially observe patterns corresponding to different exposure dwell times in the first group of chip patterns;

[0021] If the position of the graphic is incomplete, the edges are blurred or stripes appear, it is judged that the graphic is not fully exposed. If the graphic size is out of tolerance and there are no complete edges at the small intervals between the graphics, it is judged that the graphic is overexposed.

[0022] Furthermore, if the position of the pattern is incomplete, the edge is blurred or stripes appear, it is determined that the pattern is incompletely exposed; if the size of the pattern is out of tolerance, and there is no complete edge at the small interval between the patterns, it is determined that the pattern is overexposed, including the following steps:

[0023] Binarize and denoise the first set of chip graphics images, use recognition software to identify the image edges, and verify whether the image size is consistent with the chip pattern. Figure 1 To;

[0024] Observe whether the line contour pixels of the binary image are coherent and determine whether the image is blurred;

[0025] Analyze the image spectrum of the original image to see if there are color spots of residual glue;

[0026] If the position of the graphic is incomplete, the edges are blurred or stripes appear, it is judged that the graphic is not fully exposed. If the graphic size is out of tolerance and there are no complete edges at the small intervals between the graphics, it is judged that the graphic is overexposed.

[0027] Furthermore, the step of observing the second group of chip patterns, judging the exposure effect, and determining the exposure dwell time further includes the following steps:

[0028] After determining the exposure dwell time, a display time is initially proposed to carry out a development process on the exposed substrate;

[0029] Obtaining an image of the substrate after development for observation to determine the uniformity of the development process of the substrate after exposure;

[0030] If insufficient development results in incomplete removal of the photoresist, increase the unit development time. If a long development time results in uneven edges of the graphics, reduce the unit development time.

[0031] Another embodiment of the present invention further provides a DMD maskless lithography superconducting quantum chip device, the device comprising:

[0032] A mapping module is used to import chip layouts and arrange multiple chip layouts in an array to obtain a cutting file;

[0033] The photolithography module is used to specify different exposure dwell times for the chip layout in the cut file, and perform the first exposure and the second exposure:

[0034] An exposure optimization module, used to observe the first group of chip patterns and the second group of chip patterns, determine the exposure effect, and optimize the exposure time;

[0035] The development optimization module is used to develop and rinse the exposed substrate and optimize the development and rinsing time.

[0036] Another embodiment of the present invention further provides a DMD maskless lithography superconducting quantum chip system, the system comprising at least one processor; and

[0037] a memory communicatively connected to the at least one processor; wherein,

[0038] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned DMD maskless lithography superconducting quantum chip method.

[0039] Another embodiment of the present invention further provides a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by one or more processors, the one or more processors can execute the above-mentioned DMD maskless lithography superconducting quantum chip method.

[0040] By applying the technical solution of the present invention, the DMD maskless lithography technology is used to produce micron-scale structural patterns in superconducting quantum chips. Through the optimization of equipment parameters and processes, it can not only meet the rapid exposure of large-area, large-size patterns, but also meet the exposure accuracy of small sizes under certain parameter control, which is more conducive to the research and development and iteration of superconducting quantum chips. And when optimizing the exposure time, by setting multiple exposure times on one substrate, the optimization efficiency is greatly improved, and the time cost and material cost of remaking the substrate are reduced. Because more patterns are produced in one exposure and the substrate covers a wide area, the uniformity of the whole development process can be judged and the development time can be optimized during the process parameter optimization process.

[0041] Other features and advantages of the invention will be described in the following description, and partly become apparent from the description, or understood by practicing the invention. The purpose and other advantages of the invention can be realized and obtained by the structures particularly pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present invention is described in detail below in conjunction with the accompanying drawings to make the above advantages of the present invention more clear.

[0043] Figure 1 It is a flow chart of a DMD maskless photolithography superconducting quantum chip method of the present invention;

[0044] Figure 2 It is a process schematic diagram of a DMD maskless photolithography superconducting quantum chip method of the present invention;

[0045] Figure 3 It is a schematic diagram of a stripe-shaped underexposure pattern appearing in a DMD maskless photolithography superconducting quantum chip method of the present invention;

[0046] Figure 4 It is a schematic diagram of insufficient exposure of glue residue at the edge position of a DMD maskless photolithography superconducting quantum chip method of the present invention;

[0047] Figure 5 It is a schematic diagram of a chip layout of a DMD maskless lithography superconducting quantum chip method of the present invention;

[0048] Figure 6 It is a schematic diagram of overexposure in which unexposed positions at small pitches are blurred in a DMD maskless lithography superconducting quantum chip method of the present invention;

[0049] Figure 7 It is a schematic diagram of the cut-out file of the first exposure and the second exposure of a DMD maskless lithography superconducting quantum chip method of the present invention;

[0050] Figure 8 It is a functional module schematic diagram of a DMD maskless lithography superconducting quantum chip device of the present invention;

[0051] Fig. 9 It is a schematic diagram of the hardware structure of a DMD maskless lithography superconducting quantum chip system of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] Reference Figure 1-2 As shown, a DMD maskless lithography superconducting quantum chip method comprises the following steps:

[0054] S100, importing a chip layout, and arranging multiple chip layouts in an array to obtain a cutting file;

[0055] S200, selecting a first exposure time range based on the substrate material and the size of the chip layout, and specifying different exposure dwell times for the chip layout in the cutting file based on the first exposure time range, performing a first exposure and development, and obtaining a first set of chip patterns;

[0056] During exposure, the most important factor affecting the pattern accuracy is: exposure dwell time, unit: μs. When the exposure dwell time is insufficient, the pattern is not fully exposed, the pattern position is incomplete after development, the edge is blurred or stripes appear; when the exposure time is long, the pattern is overexposed, the pattern size is out of tolerance, and there is also exposure at the small intervals between the patterns. After development, there is no complete edge at the small intervals between the patterns.

[0057] S300, observing the first group of chip graphics, determining the exposure effect, optimizing the first exposure time range to obtain the second exposure time range; when the exposure dwell time is within a certain range, there is no underexposure or overexposure, but within this range, different exposure dwell times, with a minimum interval of 1μs, still have differences in graphics accuracy.

[0058] S400, based on the second exposure time range, re-specifying a different exposure dwell time for the chip layout in the cut file, performing a second exposure and development, and obtaining a second set of chip patterns;

[0059] S500, observing the second group of chip patterns, judging the exposure effect, and determining the exposure dwell time.

[0060] When the exposure dwell time is within a certain range, there is no underexposure or overexposure. However, within this range, different exposure dwell times with a minimum interval of 1μs still result in differences in graphic accuracy.

[0061] In order to quickly optimize equipment and process parameters, DMD maskless exposure can use an array to set different exposure dwell times on a substrate. During the first exposure, a larger exposure dwell time interval can be selected to determine a smaller parameter optimization range; during the second exposure, within the parameter optimization range determined for the first time, optimization is continued at 1μs intervals. The required pattern exposure dwell time can be determined by the second exposure.

[0062] In this embodiment, the cutting file may include multiple different chip layouts. In order to improve efficiency, multiple different chip layouts can be arrayed and different exposure dwell times can be specified respectively. Through the optimization of equipment parameters and processes, it can not only meet the fast exposure of large-area and large-size graphics, but also meet the exposure accuracy of small sizes under certain parameter control, which is more conducive to the research and development and iteration of superconducting quantum chips.

[0063] In this embodiment, the first exposure and the second exposure are both performed using a DMD maskless lithography machine. In order to achieve rapid optimization of equipment and process parameters, the DMD maskless lithography technology used can meet the requirements of rapid exposure of large-area and large-size graphics through the optimization of equipment parameters and processes. Under certain parameter control, it can also meet the requirements of small-size exposure accuracy at the same time, which is more conducive to the research and development and iteration of superconducting quantum chips.

[0064] In this embodiment, the step S300 of observing the first group of chip patterns, determining the exposure effect, and optimizing the first exposure time range to obtain the second exposure time range includes the following steps:

[0065] S310, observing the patterns corresponding to different exposure dwelling times in the first group of chip patterns to determine whether there is incomplete exposure or a long exposure time; manually measuring and observing using a microscope or measuring and observing by visual recognition to identify the edge and size of the pattern after development, and determine whether the exposure dwelling time is too short or too long.

[0066] S320, taking the time nodes adjacent to the incomplete exposure and the overexposure of the pattern as the upper and lower bounds of the second exposure time interval respectively, to obtain the second exposure time interval; judging the exposure result according to the development results of different patterns and the corresponding exposure dwell time, the first exposure time interval can be further optimized to obtain a second exposure time interval with higher accuracy.

[0067] S330, according to the second exposure time interval, re-specify different exposure dwell times for the chip layout of the cut file, and perform exposure and development to obtain a second set of chip graphics; when the exposure dwell time is within a certain range, there is no underexposure or overexposure, but there are still differences in graphics accuracy between different exposure dwell times within the range, and a larger exposure dwell time interval can be selected for the first exposure to determine a smaller parameter optimization range; during the second exposure, within the parameter optimization range determined for the first time, continue to optimize at 1μs intervals. The required graphics exposure dwell time can be determined by the second exposure.

[0068] S340, observing the graphics corresponding to different exposure dwell times in the second group of chip graphics, and determining the exposure dwell time of the chip layout. The edges and sizes of the graphics after development are identified by manual measurement and observation using a microscope, or by visual recognition, to determine whether the exposure dwell time is too short or too long.

[0069] In the second exposure, in order to more accurately screen the exposure results, a group of chip layouts are set to correspond to each exposure time. In the second group of chip graphics, the size of each group of graphics is measured in turn, and the average or weighted average is taken. Finally, the time corresponding to the group of graphics with the smallest average value error is the exposure residence time of the chip layout.

[0070] In this embodiment, the S310 of observing the patterns corresponding to different exposure dwell times in the first group of chip patterns and determining whether there is incomplete exposure or a long exposure time includes the following steps:

[0071] S311 acquires images of the first group of chip patterns, and sequentially observes patterns corresponding to different exposure dwell times in the first group of chip patterns;

[0072] S312: If the position of the pattern is incomplete, the edge is blurred or stripes appear, it is determined that the pattern is not fully exposed. If the size of the pattern exceeds the tolerance and there is no complete edge at the small interval between the patterns, it is determined that the pattern is overexposed.

[0073] Through manual observation, directly using an electron microscope for observation, the patterns corresponding to different exposure dwell times in the first group of chip patterns are observed in turn, and the exposure results of the patterns are determined.

[0074] The first set of chip graphics images are acquired by the CCD camera as follows:

[0075] 1. Perform binary denoising on the first set of chip graphics images, use recognition software to identify the image edges, and verify whether the image size is consistent with the chip pattern. Figure 1 To.

[0076] 2. Observe whether the line contour pixels of the binary graphics are continuous and determine whether the graphics are blurred.

[0077] 3. Analyze the image spectrum of the original image to see if there are any colored spots of residual glue.

[0078] Combine the above data results to determine whether the exposure dwell time is too long or too short.

[0079] When the exposure dwell time is within a certain range, there is no underexposure or overexposure, but there are still differences in graphic accuracy between different exposure dwell times within this range. During the second exposure, within the parameter optimization range determined for the first time, optimization is continued at 1μs intervals. The required graphic exposure dwell time can be determined by the second exposure.

[0080] Take the use of sapphire substrate to make a resonant cavity as an example:

[0081] The first exposure dwell time settings are: 35μs, 40μs, 45μs, 50μs, 55μs. After the exposure, the graphics were observed. The 35-40μs graphics were underexposed, with blurred edges and color stripes. The 45-50μs graphics were overexposed. The further optimization range was determined to be 40-45μs.

[0082] The second exposure dwell time settings are: 40μs, 41μs, 42μs, 43μs, 44μs, 45μs. According to the measurement of the graphic size after exposure, it is determined that the graphic accuracy is best at 45μs.

[0083] In this embodiment, after observing the second group of chip patterns, judging the exposure effect, and determining the exposure dwell time in S500, the following steps are also included:

[0084] S600, developing and rinsing the exposed substrate and optimizing the developing and rinsing time. After the pattern exposure parameters are determined, the developing and rinsing process can be optimized. When optimizing the exposure time, by setting multiple exposure times on one substrate, the optimization efficiency is greatly improved, and the time cost and material cost of remaking the substrate are reduced. Because more patterns are produced in one exposure and the substrate covers a wide area, the uniformity of the whole development process can be judged during the process parameter optimization process to optimize the development time.

[0085] In this embodiment, developing and rinsing the exposed substrate after determining the exposure dwell time and optimizing the development time comprises the following steps:

[0086] S610, after determining the exposure dwell time, preliminarily setting a display time to perform a developing process on the exposed substrate;

[0087] S620, obtaining an image of the substrate after development for observation, and determining the uniformity of the development process of the substrate after exposure;

[0088] S630, if insufficient development results in incomplete removal of the photoresist, increase the unit development time; if a long development time results in uneven edges of the pattern, reduce the unit development time.

[0089] The development process can be optimized by observing the removal of the photoresist. When insufficient development leads to incomplete removal of the photoresist, the development time can be appropriately increased in units of 5s. When the development time is too long and the edges of the pattern are uneven, the development time can be appropriately reduced in units of 5s. Development process optimization: The initial development time is set to 45s. Through observation, it is found that the development effect in the middle of the substrate is normal, but the development effect at the edge is not good. After increasing the development time by 5s, the development effect in the middle and edge positions is consistent.

[0090] The rinsing process can be optimized by observing the photoresist removal before and after rinsing and adjusting the rinsing time to an appropriate level.

[0091] Another embodiment of the present invention further provides a DMD maskless lithography superconducting quantum chip device, the device comprising:

[0092] A mapping module is used to import chip layouts and arrange multiple chip layouts in an array to obtain a cutting file;

[0093] The cutting file may include multiple different chip layouts. In order to improve efficiency, multiple different chip layouts can be arranged in an array and different exposure dwell times can be specified respectively. Through the optimization of equipment parameters and processes, it can not only meet the fast exposure of large-area and large-size graphics, but also meet the exposure accuracy of small sizes under certain parameter control, which is more conducive to the research and development and iteration of superconducting quantum chips.

[0094] During the second exposure, the cut file can be adjusted. In order to more accurately screen the exposure results, each exposure time in the cut file is set to correspond to a group of chip layouts. In the second group of chip graphics, the size of each group of graphics is measured in turn, and the average or weighted average is taken. Finally, the time corresponding to the group of graphics with the smallest average value error is the exposure dwell time of the chip layout.

[0095] The photolithography module is used to specify different exposure dwell times for the chip layout in the cutting file, and perform the first exposure and the second exposure: the first exposure and the second exposure are both performed using a DMD maskless photolithography machine. In order to quickly optimize the equipment and process parameters, the DMD maskless photolithography technology used can meet the requirements of fast exposure of large-area and large-size graphics through the optimization of equipment parameters and processes. Under certain parameter control, it can also meet the requirements of small-size exposure accuracy at the same time, which is more conducive to the research and development and iteration of superconducting quantum chips.

[0096] The exposure optimization module is used to observe the first group of chip patterns and the second group of chip patterns, determine the exposure effect, and optimize the exposure time; the image of the first group of chip patterns and the second group of chip patterns are obtained by the CCD camera, and the method is as follows:

[0097] Binarize and denoise the first set of chip graphics images, use recognition software to identify the image edges, and verify whether the image size is consistent with the chip pattern. Figure 1 To.

[0098] Observe whether the line contour pixels of the binary graphics are continuous to determine whether the graphics are blurred.

[0099] Analyze the image spectrum of the original image to see if there are any colored spots of residual glue.

[0100] Combine the above data results to determine whether the exposure dwell time is too long or too short.

[0101] The development optimization module is used to develop and rinse the exposed substrate and optimize the development and rinsing time.

[0102] Another embodiment of the present invention provides a DMD maskless lithography superconducting quantum chip system, such as Figure 8 As shown, the system 50 includes:

[0103] Reference Figure 7 As shown, one or more processors 510 and a memory 520 are described by taking one processor 510 as an example. The processor 510 and the memory 520 can be connected via a bus or other means. Fig. 9 The example of connecting through bus is taken in the following.

[0104] Processor 510 is used to complete various control logics of system 50, and it can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a single-chip microcomputer, an ARM (Acorn RISC Machine) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component or any combination of these components. In addition, processor 510 can also be any traditional processor, microprocessor or state machine. Processor 510 can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP and / or any other such configuration.

[0105] The memory 520 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions corresponding to the DMD maskless photolithography superconducting quantum chip method in the embodiment of the present invention. The processor 510 executes various functional applications and data processing of the system 50 by running the non-volatile software programs, instructions and units stored in the memory 520, that is, the DMD maskless photolithography superconducting quantum chip method in the above method embodiment is implemented.

[0106] The memory 520 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store data created according to the use of the system 50, etc. In addition, the memory 520 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 520 may optionally include a memory remotely arranged relative to the processor 510, and these remote memories may be connected to the system 50 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0107] One or more units are stored in the memory 520, and when executed by one or more processors 510, the DMD maskless lithography superconducting quantum chip method in any of the above method embodiments is executed, for example, the above described Figure 1The method comprises steps S100 to S500.

[0108] An embodiment of the present invention provides a non-volatile computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors, for example, to execute the above-described Figure 1 The method comprises steps S100 to S500.

[0109] As an example, non-volatile storage media can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) as external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms such as synchronous RAM (SRAM), dynamic RAM, (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM) and direct Rambus RAM (DRRAM). The disclosed memory components or memories of the operating environment described herein are intended to include one or more of these and / or any other suitable types of memories.

[0110] Another embodiment of the present invention provides a computer program product, the computer program product includes a computer program stored on a non-volatile computer-readable storage medium, the computer program includes program instructions, when the program instructions are executed by a processor, the processor executes the DMD maskless lithography superconducting quantum chip method of the above method embodiment. For example, executing the above described Figure 1 The method comprises steps S100 to S500.

[0111] In summary, the present invention discloses a DMD maskless lithography superconducting quantum chip method, device, system and medium. The method not only lightweights the skeleton model, but also binds the skeleton model to the skin model, and provides tools such as skeleton fine-tuning, action fine-tuning, and skin fine-tuning to create a natural and smooth three-dimensional virtual object, strictly control the volume and transmission volume of data, greatly reduce the loading waiting time and program budget, and finally transfer the file to a universal file, which is suitable for different three-dimensional model application platforms and has strong versatility.

[0112] The embodiments described above are merely illustrative, in which the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can exist in a computer-readable storage medium, such as ROM / RAM, a base disk, an optical disk, etc., including several instructions for enabling a computer electronic device (which can be a personal computer, a server, or a network electronic device, etc.) to execute various embodiments or certain parts of the embodiments.

[0114] Conditional language such as "can," "can," "might," or "may," among other things, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that a particular embodiment can include (while other embodiments do not) a particular feature, element, and / or operation. Thus, such conditional language is also generally intended to imply that a feature, element, and / or operation is required for one or more embodiments anyway or that one or more embodiments must include logic for determining whether such features, elements, and / or operations are included or will be performed in any particular embodiment, with or without input or prompting.

[0115] The content described in this specification and the accompanying drawings herein includes an example that a DMD maskless lithography superconducting quantum chip method, device, system and medium can be provided. Of course, it is not possible to describe each conceivable combination of elements and / or methods for the purpose of describing the various features of the present disclosure, but it can be recognized that many other combinations and permutations of the disclosed features are possible. Therefore, it is obvious that various modifications can be made to the present disclosure without departing from the scope or spirit of the present disclosure. In addition, or in an alternative, other embodiments of the present disclosure may be obvious from consideration of the present specification and the accompanying drawings and the practice of the present disclosure as presented herein. It is intended that the examples proposed in the present specification and the accompanying drawings are considered to be illustrative and non-restrictive in all respects. Although specific terms are adopted in this article, they are used in a general and descriptive sense and are not used for the purpose of limitation.

Claims

1. A DMD maskless lithography superconducting quantum chip method, characterized in that: The following steps are involved: Import the chip layout and arrange multiple chip layouts in an array to obtain a cutting file; Based on the substrate material and the size of the chip layout, a first exposure time range is selected, and based on the first exposure time range, different exposure dwell times are respectively specified for the chip layout in the cutting file, and a first exposure and development are performed to obtain a first set of chip patterns; Observe the first group of chip patterns, determine the exposure effect, and optimize the first exposure time range to obtain a second exposure time range; Based on the second exposure time range, re-specify a different exposure dwell time for the chip layout in the cut file, perform a second exposure and development, and obtain a second set of chip patterns; Observe the second group of chip patterns, judge the exposure effect, and determine the exposure dwell time.

2. The DMD maskless lithography superconducting quantum chip method according to claim 1, characterized in that: The cutting file may include a plurality of different chip layouts.

3. The DMD maskless lithography superconducting quantum chip method according to claim 1, characterized in that: The first exposure and the second exposure are both performed using a DMD maskless lithography machine.

4. The DMD maskless lithography superconducting quantum chip method according to claim 1, characterized in that: The step of observing the first group of chip patterns, determining the exposure effect, and optimizing the first exposure time range to obtain the second exposure time range comprises the following steps: Observe the patterns corresponding to different exposure dwell times in the first group of chip patterns to determine whether there is incomplete exposure or a long exposure time; Taking the time nodes adjacent to the incomplete exposure and the overexposure of the graphic as the upper and lower bounds of the second exposure time interval, respectively, to obtain the second exposure time interval; According to the second exposure time interval, a different exposure dwell time is re-specified for the chip layout of the cut file, and exposure and development are performed to obtain a second set of chip patterns; Observe the patterns corresponding to different exposure dwell times in the second group of chip patterns to determine the exposure dwell time of the chip layout.

5. The DMD maskless lithography superconducting quantum chip method according to claim 4, characterized in that: Observing the patterns corresponding to different exposure dwell times in the first group of chip patterns to determine whether there is incomplete exposure or a long exposure time includes the following steps: Acquire images of the first group of chip patterns, and sequentially observe patterns corresponding to different exposure dwell times in the first group of chip patterns; If the position of the graphic is incomplete, the edges are blurred or stripes appear, it is judged that the graphic is not fully exposed. If the size of the graphic is out of tolerance and there are no complete edges in the small intervals between the graphics, it is judged that the graphic is overexposed.

6. The DMD maskless lithography superconducting quantum chip method according to claim 5, characterized in that: If the position of the pattern is incomplete, the edge is blurred or stripes appear, it is determined that the pattern is not fully exposed; if the size of the pattern is out of tolerance, and there is no complete edge at the small interval between the patterns, it is determined that the pattern is overexposed, including the following steps: The first group of chip pattern images were subjected to binary denoising, and the image edges were identified using recognition software to verify whether the image size was consistent with the chip layout; Observe whether the line outline pixels of the binary image are coherent and determine whether the image is blurred; Analyze the image spectrum of the original image to see if there are color spots of residual glue; If the position of the graphic is incomplete, the edges are blurred or stripes appear, it is judged that the graphic is not fully exposed. If the size of the graphic is out of tolerance and there are no complete edges in the small intervals between the graphics, it is judged that the graphic is overexposed.

7. The DMD maskless lithography superconducting quantum chip method according to claim 1, characterized in that: After observing the second group of chip patterns, judging the exposure effect, and determining the exposure dwell time, the following steps are also included: After determining the exposure dwell time, a display time is initially proposed to carry out a development process on the exposed substrate; Obtaining an image of the substrate after development for observation to determine the uniformity of the development process of the substrate after exposure; If insufficient development results in incomplete removal of the photoresist, increase the unit development time. If a long development time results in uneven edges of the graphics, reduce the unit development time.

8. A DMD maskless lithography superconducting quantum chip device, characterized in that: The device comprises: A mapping module is used to import chip layouts and arrange multiple chip layouts in an array to obtain a cutting file; The photolithography module is used to specify different exposure dwell times for the chip layout in the cut file, and perform the first exposure and the second exposure: An exposure optimization module, used to observe the first group of chip patterns and the second group of chip patterns, determine the exposure effect, and optimize the exposure time; The development optimization module is used to develop and rinse the exposed substrate and optimize the development and rinsing time.

9. A DMD maskless lithography superconducting quantum chip system, characterized in that: The system includes at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the DMD maskless lithography superconducting quantum chip method according to any one of claims 1 to 7.

10. A non-volatile computer-readable storage medium, characterized in that: The non-volatile computer-readable storage medium stores computer-executable instructions, which, when executed by one or more processors, enable the one or more processors to execute the DMD maskless lithography superconducting quantum chip method according to any one of claims 1 to 7.

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