Power saving mode switching to prevent bias temperature instability

Abstract

The present disclosure relates to power saving mode switching that prevents bias temperature instability. Systems and methods for introducing a switching signal in a command pipeline configured to receive a plurality of command types for a memory device. Switching circuitry is configured to introduce the switching signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline does not contain a valid command. When a command that is not valid in the power saving mode is asserted during the power saving mode, the switching is prevented from causing a write by disabling data strobe.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to introducing toggling to mitigate degradation of a memory device. BACKGROUND

[0002] Semiconductor devices (e.g., memory devices) can utilize a power save mode to conserve power during inactive periods of the device. While the memory device is in the power save mode, a limited number of valid commands can be obtained. When the memory device is in the power save mode for a relatively long duration, the memory device can experience a long period without valid commands being issued to the memory device. This can cause various portions of the memory device (e.g., transistors in a delay line) to degrade due to bias temperature instability (BTI) stress caused by the lack of activity. Typically, to mitigate the BTI stress, the inputs to the chip can be toggled to compensate for the BTI stress using a BTI toggle signal. However, since the delay line needs to remain idle to receive incoming valid commands while the memory device is in the power save mode, the delay line (and / or downstream devices) can not be able to toggle in a similar manner.

[0003] Embodiments of the present disclosure can be directed to addressing one or more of the issues set forth above. SUMMARY

[0004] In one aspect, the present disclosure is directed to a memory device comprising a command pipeline configured to receive a plurality of command types for the memory device, and toggle circuitry configured to introduce a toggle signal into at least a portion of the command pipeline when the memory device is in a power save mode and the command pipeline does not contain a valid command.

[0005] In another aspect, the present disclosure is directed to a method comprising receiving, at toggle circuitry of a memory device, an assertion of a power save mode signal as an indication of activation of a power save mode, and introducing, from the toggle circuitry into a command pipeline, a toggle signal during the power save mode, wherein introducing the toggle signal comprises toggling a first path associated with a first command and a second path associated with a second command, wherein the first command comprises a valid command that can be received from a host device to the memory device in the power save mode, and the second command comprises an invalid command that cannot be received from the host device to the memory device in the power save mode.

[0006] In yet another aspect, the disclosure relates to a system comprising: a command pipeline; switching circuitry configured to introduce a switching signal into a plurality of command paths for at least a portion of the command pipeline when the system is in a power save mode and a first command type and a second command type are not in the command pipeline, wherein a command path of the plurality of command paths corresponds to a command that is not active during the power save mode; and resolution circuitry configured to disable a data strobe for capturing data on a data signal line when the power save mode is active and the signal corresponding to the command path is asserted. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 to illustrate some features of a memory device according to embodiments of the disclosure;

[0008] Figure 2 to illustrate a simplified block diagram of a pipeline for a memory device according to embodiments of the disclosure; Figure 1

[0009] Figure 3 to illustrate an implementation of BTI switching circuitry for introducing a BTI switch into a pipeline according to embodiments of the disclosure; Figure 2

[0010] Figure 4 to illustrate logic circuitry for mitigating contention of an incoming signal during a BTI switch using BTI switching circuitry according to embodiments of the disclosure; Figure 3

[0011] Figure 5 to illustrate logic circuitry for synchronizing signals in a pipeline and compensating for delays caused by logic circuitry according to embodiments of the disclosure; Figure 4

[0012] Figure 6 to illustrate logic circuitry for transitioning from a power save mode and normal operation according to embodiments of the disclosure; and

[0013] Figure 7 to illustrate a schematic of a latch that can be used in logic circuitry according to embodiments of the disclosure. Figure 6 DETAILED DESCRIPTION

[0014] ​​​​​One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0015] Memory devices encounter periods of inactivity during operation and can enter a power saving mode that has a reduced number of valid commands that can be received by a delay line of the memory device when compared to modes other than the power saving mode. The memory device can be in the power saving mode for a longer duration without receiving any of these valid commands. This period of inactivity and lack of valid commands can cause components (e.g., transistors) in the delay line to degrade due to bias temperature instability (BTI) stress. Typically, line toggling can be used to mitigate BTI (e.g., negative BTI (NBTI) or positive BTI (PBTI)) in the transistors. However, since the delay line will remain open to receive incoming valid commands, the delay line can not be directly toggled to compensate for the BTI stress. Embodiments disclosed herein provide systems and methods for compensating for BTI stress by introducing a forced toggle into a pipeline upstream of the delay line to cause the delay line to toggle when no commands are detected in the pipeline while still enabling the pipeline to receive incoming valid commands.

[0016] Figure 1 A simplified block diagram illustrating some features of a memory device 10. According to one embodiment, the memory device 10 can be a fifth generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, increased bandwidth, and increased storage capacity as compared to previous generations of DDR SDRAM. The memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a plurality of memory banks 12. The memory banks 12 can be, for example, DDR5 SDRAM memory banks. The memory banks 12 can be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). Each DIMM can include a plurality of SDRAM memory chips (e.g., eight or sixteen memory chips). Each SDRAM memory chip can include one or more memory banks 12.

[0017] For DDR5, the memory banks 12 can be arranged to form bank groups. For example, a memory chip can include sixteen memory banks 12 for an eight gigabyte (8 Gb) DDR5 SDRAM. The memory banks 12 can be arranged into eight bank groups, each bank group including two memory banks. For a sixteen gigabyte (16 Gb) DDR5 SDRAM, a memory chip can include thirty-two memory banks 12 arranged into eight bank groups, each bank group including, for example, four memory banks 12.

[0018] Various other configurations, organizations, and sizes of the memory banks 12 on the memory device 10 can be utilized depending on the application and design of the overall system. In one embodiment, each memory bank 12 includes a bank control block 22 that controls execution of commands to and from the memory bank 12 for performing various functionality in the memory device 10, such as decoding, timing control, data control, and any combination thereof.

[0019] The command interface 14 of the memory device 10 is configured to receive and transmit a plurality of signals (e.g., signals 15). The signals 15 can be received from an external device (not shown), such as a processor or controller. The processor or controller can provide various signals 15 to the memory device 10 to facilitate transmission and reception of data to be written to or read from the memory device 10.

[0020] As will be appreciated, the command interface 14 can include a number of circuits, such as a clock input circuit 18 and a command address input circuit 20, for example, to ensure proper handling of the signals 15. The command interface 14 can receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as true clock signal Clk t and bar clock signal Clk c. The positive clock edge of DDR refers to the point where the rising true clock signal Clk t crosses the falling bar clock signal Clk c. The negative clock edge indicates the transition of the falling true clock signal Clk t and the rising bar clock signal Clk c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal. Data can be transmitted or received on both the positive and negative clock edges.

[0021] Clock input circuit 18 receives true clock signal Clk_t and inverted clock signal Clk_c and generates an internal clock signal CLK. Internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. Phase-controlled internal clock signal LCLK is supplied to, for example, I / O interface 16 and used as a timing signal for determining the output timing of read data. In some embodiments, as discussed below, clock input circuit 18 can include circuitry that splits a clock signal into multiple (e.g., four) phases. Clock input circuit 18 can also include phase detection circuitry for detecting which phase receives the first pulse when the pulse sets occur too frequently, enabling clock input circuit 18 to reset between pulse sets.

[0022] Internal clock signal / phase CLK can also be provided to various other components within memory device 10, and can be used to generate various additional internal clock signals. For example, internal clock signal CLK can be provided to command decoder 32. Command decoder 32 can receive command signals from command bus 38, and can decode the command signals to provide various internal commands. For example, command decoder 32 can provide command signals to DLL circuit 30 over bus 40 to coordinate the generation of phase-controlled internal clock signal LCLK. Phase-controlled internal clock signal LCLK can be used to clock data, for example, through I / O interface 16.

[0023] Furthermore, command decoder 32 can decode incoming commands, such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to particular memory banks 12 corresponding to the commands via bus path 42. As will be appreciated, memory device 10 can include various other decoders, such as row decoders and column decoders, to facilitate access to memory banks 12.

[0024] Command decoder 32 and / or any other portion of memory device 10 can include command expander 34. Command expander 34 can expand command signals for the duration required for certain operations of memory device 10. That is, command expander 34 can be used for unique operations that use an assertion of a command signal that is longer than would be possible without command expander 34. Additionally, command decoder 32 can include QED shifter 36 for shifting command signals to a selected column address strobe latency (CL) duration. CL represents the number of clock cycles between when a command signal is being asserted to a column decoder and when data can be obtained from memory banks 12 in response to the column decoder. In some embodiments, command decoder 32 can be externally coupled to QED shifter 36 and command expander 34.

[0025] Memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device, such as a processor. In one embodiment, command / address bus 38 can be a 14-bit bus to accommodate command / address signals CA<13:0>. Command / address signals 15 are clocked to command interface 14 using clock signals (Clk_t and Clk_c). Command interface 14 can include command address input circuitry 20 configured to receive and transmit commands through command decoder 32 to provide access to memory banks 12. In addition, command interface 14 can receive a chip select signal CS_n. The CS_n signal enables memory device 10 to process commands on the incoming CA<13:0> bus. Access to a particular memory bank 12 within memory device 10 is encoded on the CA<13:0> bus through commands.

[0026] In addition, command interface 14 can be configured to receive a number of other command signals. For example, a command / address on-die termination (CA_ODT) signal can be provided to facilitate proper impedance matching within memory device 10. A reset command RESET_n can be used to reset command interface 14, status registers, state machines, etc. during power-up, for example. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on command / address bus 38, for example, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirror functionality. Based on the configuration of a number of memory devices (such as memory device 10) in a particular application, the MIR signal can be used to multiplex signals so that the signals can be swapped to enable certain routing of signals to memory device 10. Various signals to facilitate testing of memory device 10 can also be provided, such as a test enable (TEN) signal. The TEN signal can be used to place memory device 10 in a test mode for connectivity testing, for example.

[0027] Command interface 14 can also be used to provide a warning signal (ALERT_n) to a system processor or controller for detectable errors. For example, the warning signal (ALERT_n) can be transmitted from memory device 10 if a cyclic redundancy check (CRC) error is detected. Other warning signals can also be generated. In addition, the bus and pin used to transmit the warning signal (ALERT_n) from memory device 10 can be used as an input pin during some operations, such as the connectivity test mode described above that is performed using the TEN signal.

[0028] With the commands and timing signals 15 discussed above, data can be sent to and from the memory device 10 by transmitting and receiving data signals 44 via the I / O interface 16. More specifically, data can be sent to or retrieved from the memory bank 12 through a data path 46 that includes a plurality of bidirectional data buses. The data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For a particular memory device, such as a DDR5 SDRAM memory device, the I / O signals can be divided into upper and lower bytes. For example, for an x16 memory device, the I / O signals can be divided into upper and lower I / O signals, such as upper and lower bytes of data signals (e.g., DQ<15:8> and DQ<7:0>).

[0029] To allow higher data rates within the memory device 10, some memory devices, such as DDR memory devices, can utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal can be used as a clock signal to capture the corresponding input data. As with the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For some memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to upper and lower bytes of data sent to and from the memory device 10.

[0030] An impedance (ZQ) calibration signal can also be provided to the memory device 10 through the IO interface 16. The ZQ calibration signal can be provided to a reference pin and used to tune the output drivers and ODT values by adjusting the pull-up and pull-down resistors of the memory device 10 through changes in process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the ZQ resistor values, the ZQ calibration signal can be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. Such a resistor acts as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0031] In addition, a loopback signal (LOOPBACK) can be provided to the memory device 10 through the IO interface 16. The loopback signal can be used during a test or debug phase to set the memory device 10 in a mode in which signals loop back through the memory device 10 through the same pin. For example, the loopback signal can be used to set the memory device 10 to test the data outputs (DQ) of the memory device 10. The loopback can include both data and strobe, or can include only data pins. This is generally intended for monitoring data captured at the I / O interface 16 by the memory device 10.

[0032] As will be appreciated, various other components such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operation and configuration), read / write amplifiers (to amplify signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10) can also be incorporated into the memory device 10. Thus, it should be understood that the block diagram of the memory device 10 is provided to highlight some of the functional features of the memory device 10 to aid in the following detailed description. Figure 1

[0033] As discussed above, the memory device 10 can remain idle during operation, and can transition into a power saving mode (e.g., a maximum power saving mode). When in the power saving mode, the memory device 10 can receive only a limited number of valid commands, and or can expose the memory device 10 to BTI unless mitigated. These commands can be processed through the pipeline of the memory device 10.

[0034] With the foregoing in mind, Figure 2 A simplified block diagram of the pipeline 50 of the memory device 10 in a power saving mode is illustrated. The command decoder 52 (e.g., the command decoder 32) can receive command signals from the command bus 38, and can decode the command signals to provide various internal commands. The command signals that the command decoder 52 can receive include a write command WR, a write non-target command WR-NT, and a read non-target command RD-NT, among other commands. During the power saving mode, only a subset of the commands can be valid. For example, in some embodiments, the only valid commands that the command decoder can receive and / or decode during the power saving mode include the write non-target command and the read non-target command.

[0035] ​The command decoder 52 can be coupled to a command expander 54 (e.g., the command expander 34). As previously described, the command expander 54 can expand command signals to be asserted for the duration required for certain operations of the memory device 10. The active output of the command expander 54 can be an expanded version of the incoming command, such as a WRExt signal, a WRExt-NT signal, and / or a RDExt-NT signal in response to receiving a respective WR, WR-NT, and / or RD-NT signal. Further, when the command expander 54 receives a write non-target or read non-target command, it can output a respective busy signal, such as a BUSY-WRNT or a BUSY-RDNT, to indicate that the non-target command is incoming / being processed within the command expander 54.

[0036] The command expander 54 can be coupled to a QED shifter 56. The QED shifter 56 can include a plurality of flip-flops that can shift command signals from the command expander 54. In some embodiments, the QED shifter 56 can have a plurality of outputs from which a selected signal is selected according to a selection of a length of a column address strobe latency (CL). As previously described, the CL represents a number of clock cycles between when a command signal is being issued to the command decoder 52 and data available from the memory banks 12 for the command decoded by the command decoder 52. In response to receiving a WRExt signal, a WRExt-NT signal, or a RDExt-NT signal, the QED shifter 56 can output a respective DLL signal, such as a respective WRDLL, WRNTDLL, or RDNTDLL signal. The QED shifter 56 can output a QED_BUSY signal to indicate that a command has not exited the QED shifter 56 while any of the listed commands are being shifted by the QED shifter 56. In some embodiments, the QED shifter 56 can simultaneously output one or more of the signals (WRDLL, WRNTDLL, and RDNTDLL). In certain embodiments, the QED shifter 56 can assert one or more of the signals (WRDLL, WRNTDLL, and RDNTDLL) due to a BTI switch without receiving a respective signal from the command expander 54.

[0037] The QED shifter 56 can be coupled to the DLL circuit 30. The DLL circuit 30 utilizes a delay line as an input / output. As discussed above, the DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on a received internal clock signal CLK and transmits LCLK to RTT circuitry 58 for applying an on-die termination (RTT) to carry out execution of a command in the memory device 10. That is, the DLL circuit 30 can be an interface between other portions of the pipeline 50 and the memory device 10. The DLL circuit 30 can output WRDQ signals, WRNTDQ signals, and / or RDNTDQ signals to the RTT circuitry 58 through the I / O interface 16, where the I / O interface 16 receives the DQ signals.

[0038] As discussed above, memory device 10 can enter a power saving mode, which saves power while allowing a reduced number of valid commands to move through pipeline 50. Memory device 10 can be in the power saving mode for a long duration, and no valid commands are issued to memory device 10. This can cause the transistors on the delay lines of DLL circuit 30 to degrade due to bias temperature instability (BTI) stress. As transistors are implemented using semiconductors (e.g., MOSFETs), BTI stress affects the transistors of memory device 10.

[0039] BTI stress can occur when the transistors of memory device 10 accumulate positive (in the case of pMOS) or negative (for nMOS) charge. The charge is trapped at the oxide-semiconductor boundary below the gate of the MOSFET. These trapped charges partially cancel the gate voltage without contributing to conduction through the channel. When the gate voltage is removed, the trapped charge can dissipate across the area of the gate. Thus, the size of the gate area can be used to mitigate the effects of BTI stress. However, as transistors continue to shrink with the size of electronic devices, it is not always feasible to mitigate BTI stress by altering physical aspects of the MOSFET. BTI stress manifests as changes in the threshold voltage, drain current, and / or transconductance of the MOSFET. BTI stress in memory device 10 can be due, at least in part, to underutilization of the transistors within memory device 10 during the power saving mode. The degree of adverse effects caused by BTI stress can vary from device to device.

[0040] To mitigate BTI stress generated by inactivity during the power save mode, the memory device 10 can cause a switch through the delay lines of the DLL circuit 30 without interrupting any commands in the pipeline 50 while the memory device 10 is in the power save mode. Since the delay lines of the DLL circuit 30 can be used for incoming commands at any time, the delay lines of the DLL circuit 30 can be difficult to switch. Thus, causing a switch through the delay lines of the DLL circuit 30 by introducing a BTI switch signal into the pipeline 50 at the QED shifter 56 can result in a switch on at least a subset of the outputs (WRDLL, WRNTDLL, and RDNTDLL) that are available for use. In some embodiments, a forced switch can be introduced at any location in the pipeline 50. For example, the switch can be introduced at any location of the pipeline 50 (e.g., the command decoder 52, the command expander 54, or the QED shifter 56). By causing a switch of the delay lines of the DLL circuit 30 while the memory device 10 is in the power save mode, the accumulation of charge at the gates of the MOSFETs can be mitigated, and the degradation of the delay lines of the DLL circuit 30 of the memory device 10 can be slowed down / stopped. It should be noted that the switch of the delay lines of the DLL circuit 30 can be at a slower frequency than the external clock. For example, the BTI switch signal can cycle at a first rate (e.g., every 500 nanoseconds), while the external clock can switch at a second rate (e.g., every 384 picoseconds or faster). The lower frequency of the BTI switch signal can be used to reduce the power consumption used in the BTI switch relative to the switching using the external clock.

[0041] Returning to Figure 2 In some embodiments, when BUSY_RDNT, BUSY_WRNT, and QED_BUSY are all low, the memory device 10 can only cause a switch through the delay lines of the DLL circuit 30. When these conditions are met, the memory device 10 can interpret that there are no incoming commands in the pipeline 50 and that the commands have exited the QED shifter 56. Both BUSY_WRNT and BUSY_RDNT can represent busy signals whenever the command expander 54 is in operation for the respective WR_NT and RD_NT commands. Once BUSY_WRNT or BUSY_RDNT is asserted, the switch stops, and the QED shifter 56 is set to the correct state for an incoming command.

[0042] With the foregoing in mind, Figure 3A diagram of a switching circuitry 70 as an embodiment for performing BTI switching by selective switching through a delay line of the DLL circuitry 30. The switching circuitry 70 can be implemented in the QED shifter 56 and / or external to the QED shifter 56 in another portion of the memory device 10. As previously discussed, although the foregoing discussion will focus on introducing the switching signal into the pipeline 50 through the QED shifter 56, the switching can be introduced at any point along the pipeline 50. As illustrated, the switching circuitry 70 can include an inverter 72, a NAND gate 74, an inverter 76, an inverter 78, or a NOR gate 80, a flip-flop 82, or a NOR gate 84, and an inverter 86.

[0043] A signal BTI toggle is supplied along line 88 into the NAND gate 74. The BTI toggle signal is a switching signal to introduce switching through the DLL circuitry 30. In some embodiments, the BTI toggle signal can be slower than the external clock to minimize power consumption. Another signal MAX PWR SAV is supplied along line 90 into the NAND gate 74. The MAX PWR SAV signal indicates that the memory device 10 is in a power saving mode or will enter a power saving mode. When the MAX PWR SAV signal is asserted, the memory device 10 is currently in a maximum power saving mode (or any other power saving mode with a reduced command set). Further, when the MAX PWR SAV signal is asserted, the NAND gate 74 allows the BTI toggle signal to flow through unless disabled by a test mode. A third signal BTI TEST MODE can be supplied along line 92 into the inverter 72 which inverts the BTI TEST MODE signal and supplies it to the NAND gate 74. The BTI TEST MODE signal represents a test mode signal that can be used to disable the BTI switching for various test modes. Unless the memory device 10 is undergoing testing, the BTI TEST MODE signal can default to high, in which case the BTI TEST MODE signal can be constantly asserted. In some embodiments, the three signals, the BTI toggle signal, the MAX POWER SAV signal, and the BTI TEST MODE can be received from a host device through one or more respective mode registers. Thus, the BTI TEST MODE and the MAX POWER SAV can be used to gate the switching of the BTI toggle signal to the NOR gate 84 when the memory device 10 is in a test mode and / or when the power saving mode is not active.

[0044] The signal BUSY_RDRTT is supplied along line 94 and the signal BUSY_WRRTT is supplied along line 96 into the NAND gate 80. The BUSY_RDRTT and the BUSY_WRRTT can be indicative of whether an ODT terminal has been asserted. For example, the BUSY_RDRTT can be based on and / or the same as the BUSY_RDNT and the BUSY_WRRTT can be based on and / or the same as the BUSY_WRNT. Both the BUSY_RDRTT and the BUSY_WRRTT can be indicative of a read or write non-target command (RTT) being in the pipeline 50. In addition, the signal PWR_UP_RST can be supplied along line 100 into the inverter 78, where the signal is inverted and supplied to the NAND gate 80. The PWR_UP_RST signal is indicative of the memory device 10 having been powered up and / or reset to a restart state. The PWR_UP_RST signal can be used to ensure that the flip-flop 82 is set to the correct default state (e.g., output 0) during start-up of the memory device 10. That is, only when both the BUSY_RDNT and the BUSY_WRNT are de-asserted, the PWR_UP_RST signal will reset the flip-flop 82 to be asserted. If any of the BUSY_RDRTT, the BUSY_WRRTT, and the PWR_UP are asserted, the NAND gate 80 output will not be de-asserted. The NAND gate 80 will supply a reset input to the flip-flop 82. In other words, if a command is in the pipeline 50 or has been restarted, the flip-flop 82 is reset to the default state.

[0045] The signal QED_SHIFT_BUSY (e.g., the QED_BUSY signal of Figure 2 the QED_SHIFT_BUSY signal is supplied along line 98 into the inverter 78, where the signal is inverted and supplied to the flip-flop 82 as a clock for the flip-flop 82. As previously described, the QED_SHIFT_BUSY signal can be indicative of the QED shifter 56 being busy and the delay lines of the DLL circuit 30 being unable to switch. When the QED_SHIFT_BUSY signal is low, the flip-flop 82 can latch the data supplied along line 99 into the flip-flop 82 in the VSS voltage (e.g., 1) using the data input into the flip-flop 82. That is, if the NAND gate 80 output is a logic high, the flip-flop 82 output is a logic high such that the flip-flop 82 is clocked in voltage via line 99. That is, the NAND gate 80 output will be a logic high before the BUSY_RDRTT or the BUSY_WRRTT transitions high or before the PWR_UP_RST signal transitions. Once the NAND gate 80 supplies a low output to the flip-flop 82, the flip-flop 82 output is set to the default value (e.g., 0).

[0046] The output of the flip-flop 82 is launched to a NAND gate 84. Since a high output from the flip-flop 82 will force the output of the NAND gate 84 to be low, the output of the flip-flop 82 can be used as a gate forced toggle from the introduction of the NAND gate 74 in the event that a command signal for a read or write non-target command is detected within the pipeline 50. When the flip-flop 82 remains low, the NAND gate 84 tracks the output of the NAND gate 74. The BTI_toggle signal flows through the NAND gate 74 and / or the NAND gate 84 can cause the BTI_toggle signal to be inverted, or can cause the BTI_toggle signal to flow non-inverted depending on the particular implementation. The NAND gate 84 supplies its output to an inverter 86 to correct the logic polarity and / or amplify the output signal MPSM_BTI_toggleF along the output line 102. The MPSM_BTI_toggleF signal is a toggle signal that is driven by the BTI_toggle signal when toggling is enabled for the power save mode by the toggle circuitry 70. When the various signals cause the BTI_toggle signal to flow through the NAND gate 74 and the NAND gate 84 as MPSM_BTI_toggleF, the memory device 10 can cause toggling of the delay lines of the DLL circuit 30 by causing the BTI_toggle signal output by the QED shifter 56 (WRDLL, WRNTDLL, and RDNTDLL) to pass through the QED shifter 56.

[0047] Figure 4 A schematic of the resolution circuitry 110 for resolving contention of the toggle signal used for toggling using the BTI_toggle signal. When multiple (e.g., 3) outputs of the QED shifter 56 are effectively toggled with the BTI_toggle signal, toggling of the delay lines of the DLL circuit 30 can cause contention in the RTT state between the DQ signals. Thus, any enable signals in the DQ signals can be gated to prevent writing / reading during the power save mode while forcing toggling of the delay lines of the DLL circuit 30.

[0048] The resolution circuitry 110 can include a NAND gate 112, an inverter 114, and a NAND gate 116. The signal WrDynRttDQ is supplied to the NAND gate 112 on a line 118. The WrDynRttDQ signal can represent an RTT assertion for a write command from the DLL circuit 30. In other words, the signal can be used during the BTI toggling process to prevent toggling of the delay lines of the DLL circuit 30. The output of the NAND gate 112 is supplied to the inverter 114. The inverter 114 inverts the output of the NAND gate 112 to provide the signal WrDynRttDQinv on a line 120. The signal WrDynRttDQinv is supplied to the NAND gate 116. The output of the NAND gate 116 is supplied to the inverter 86 to correct the logic polarity and / or amplify the output signal MPSM_BTI_toggleF along the output line 102. The MPSM_BTI_toggleF signal is a toggle signal that is driven by the BTI_toggle signal when toggling is enabled for the power save mode by the toggle circuitry 70. When the various signals cause the BTI_toggle signal to flow through the NAND gate 74 and the NAND gate 84 as MPSM_BTI_toggleF, the memory device 10 can cause toggling of the delay lines of the DLL circuit 30 by causing the BTI_toggle signal output by the QED shifter 56 (WRDLL, WRNTDLL, and RDNTDLL) to pass through the QED shifter 56. Figure 3The MPSM_BTI_TOGGLE signal toggles the WrDynRttDQ signal. In some embodiments, other signals in the pipeline 50 can be used as the signal supplied on line 118. For example, in some embodiments, such input can be limited to command types that are not permitted in the power save mode. The MAX_PWR_SAV signal is also supplied along line 119 to the resolving circuitry 110 to the NAND gate 112. As previously described, the MAX_PWR_SAV signal indicates the time that the memory device 10 is in the power save mode. The NAND gate 112 supplies the WrDynRtt_MPSM signal to the output line 120, which supplies one of the NAND gate 116 inputs. The WrDynRtt_MPSM signal is asserted unless both the WrDynRtt_MPSM signal and the MAX_PWR_SAV signal are asserted. In other words, when asserted while the power save mode is asserted, the NAND gate 112 stops the propagation of write commands outside the specification for the power save mode. When both the MAX_PWR_SAV signal and the WrDynRttDQ signal are logically high, the NAND gate 112 outputs a logical low. This ensures that whenever a write command is to pass through the pipeline 50 while the memory device 10 is in the power save mode, the NAND gate 112 prevents the pulse from the BTI_toggle signal from propagating the data to be captured in the memory cells using the DQS signal to the DQ lines. That is, the NAND gate 112 traps the toggling of the WrDynRttDQ signal coincident with the assertion of the MAX_PWR_SAV mode and prevents the propagation of the toggling from the WrDynRttDQ signal by cutting off the toggling from the DQS line while the MAX_PWR_SAV mode is active.

[0049] The signal TDQSEn can also be supplied on line 122 to the inverter 114. The TDQSEn signal can be used to enable DQS toggling, which is used to capture data on the DQ lines for a write when the data is not to be trapped using the NAND gate 112. The inverter 114 inverts and supplies the inverted TDQSEn signal to the NAND gate 116. Thus, the NAND gate 116 is used to gate the DQS signaling when DQS is not to be enabled using the TDQSEn signal. When the TDQSEn signal is enabled, the NAND gate 112 emits the output of the WrDynRtt_MPSM signal on the TDQSEn_MPSM signal on line 124. The TDQSEn_MPSM signal is used to drive the DQS that enables the capture of data on the DQ lines. Otherwise, the NAND gate 116 prevents the emission of the WrDynRtt_MPSM signal as the TDQSEn_MPSM signal. Thus, when the path corresponding to a write command (or another invalid command during the power save mode) is asserted / toggled during the power save mode, the resolving circuitry 110 suppresses the assertion of the DQS.

[0050] When no switching occurs, the timing of the RTT state can still need to be synchronized with the external clock. That is, due to the delay introduced by the NAND gate 112, the inverter 114, and / or the NAND gate 116, the resolving circuitry 110 can add a timing delay into the pipeline 50. With the foregoing in mind, Figure 5 is a diagram of delay circuitry 130 for synchronizing the RTT commands from the pipeline 50 with the external clock. The delay circuitry 130 can include a pair of inverters 132, a pair of inverters 134, and a pair of inverters 136.

[0051] The signal WrDynRttDQ is supplied along line 118 into the pair of inverters 132. The signal WrNomRttDQ, which corresponds to a non-targeted read command, is supplied along line 138 into the pair of inverters 134. The signal RdNomRttDQ, which corresponds to a non-targeted write command, is supplied along line 140 into the pair of inverters 136. Both the WrNomRttDQ signal and the RdNomRttDQ signal represent write and read non-targeted commands, respectively, that are active for the memory device 10. The pair of inverters 132, 134, and 136 can output the WrDynRttDQ_MPSM, WrNomRttDQ_MPSM, and RdNomRttDQ_MPSM signals, respectively. The two inverters in each pair of inverters can cause the same logic value to be output with a delay to match Figure 4 the delay in the circuitry of the memory device 10.

[0052] In certain embodiments, a command can be sent to the memory device 10 to exit the power saving mode during a BTI switch. However, if the MAX_PWR_SAV signal is turned off while the RTT signal output from the DLL circuit 30 is still high during the BTI switch, an incorrect RTT state can be applied. To ensure that the power saving mode is not turned off until after the BTI switch has propagated through a portion of the pipeline 50 (e.g., the DLL circuit 30), the memory device 10 can use: 1) a latch to hold the MAX_PWR_SAV signal de-asserted until after the propagation has completed; 2) a delay for the MAX_PWR_SAV signal de-assertion inserted by the maximum propagation time for a command to travel through the portion or complete the pipeline 50; and 3) a count of the number of BTI switches into and out of the portion / pipeline 50 to determine whether all switching pulses have cleared the portion / pipeline 50. With the foregoing in mind, Figure 6 is a diagram of logic circuitry 150 for implementing a successful transition between the power saving mode and normal operation by ensuring that all of the delay lines of the DLL circuit 30 have cleared before transitioning to the power saving mode.

[0053] Logic circuitry 150 can delay the transition between the power save mode of memory device 10 to another mode (e.g., normal operation) to ensure that the BTI toggles have been cleared from the delay lines of DLL circuit 30. Logic circuitry 150 can include an NOR gate 152, an NOR gate 154, an inverter 156, an inverter 157, a latch 158, and an NOR gate 160. A MAX PWR SAV signal is supplied as an input to NOR gate 152 and latch 158 along line 162. As previously described, the MAX PWR SAV signal can indicate that memory device 10 has entered or will enter a power save mode. Thus, when the MAX PWR SAV signal transitions low, memory device 10 will exit the power save mode. However, logic circuitry 150 can delay this exit until the BTI toggles have propagated through and exit the pipeline 50. In addition to or in lieu of latch 158, logic circuitry 150 can include a delay that is tuned to the duration of the BTI toggles to propagate through the portion / pipeline 50. Additionally or alternatively, logic circuitry 150 can include a first counter that counts the BTI pulses into the portion / pipeline 50 and a second counter that counts the BTI pulses out of the portion / pipeline 50 to delay the de-assertion of MAX PWR SAV until the portion / pipeline 50 has been free of BTI toggles.

[0054] A WrDynRTT signal is supplied as another input into NOR gate 152 along line 164. Unless pipeline 50 is free of toggles / assertions of WrDynRTT for write commands in the delay lines of DLL circuit 30, NOR gate 152 can be used to gate the MAX PWR SAV signal when swapping from the power save mode. When the MAX PWR SAV signal transitions low, if WrDynRTT is not high, the output of NOR gate 152 transitions high. NOR gate 152 can supply the output to inverter 156, where inverter 156 inverts the output from NOR gate 152 and supplies the input to NOR gate 160.

[0055] The WrNomRTT and RdNomRTT signals can be supplied along respective lines 166 and 168, each serving as an input to the NAND gate 154. In a similar manner as used by the NAND gate 152, the NAND gate 154 will output a logic low unless the pipeline 50 does not contain a non-targeted read and write command (e.g., the WrNomRTT and RdNomRTT signals are low). The NAND gate 154 can supply its output to an inverter 157. The inverter 157 inverts the signal from the NAND gate 154 and supplies the signal to a NAND gate 160. The output of the NAND gate 160 can be a logic high unless each of the outputs from the NAND gate 152 and the NAND gate 154 are low, which can only occur when the pipeline 50 and the delay line of the DLL circuit 30 are clear and the memory device 10 exits the power save mode.

[0056] The NAND gate 160 can supply its output at the reset pin of the latch 158. The reset pin (e.g., RST or RSTf) can be used to reset the latch 158 to output a de-assertion of the MAX PWR SAV signal. Thus, when the pipeline 50 is clear, the output of the latch 158 is a delayed transition of the MAX PWR SAV signal at the output line 169 (i.e., the MAX PWR SAVD signal). In other words, the MAX PWR SAVD signal indicates that the delay line of the DLL circuit 30 is clear and that the exit from the power save mode can be completed. In some embodiments, the signals on lines 164, 166, and 168 can be sampled from multiple locations in the pipeline 50. These signals can be combined (e.g., using an OR gate) such that any assertion / transition sampled at any location in the pipeline 50 will prevent the reset of the latch 158.

[0057] With the foregoing in mind, Figure 7 A diagram of an embodiment of the latch 158 that can be used to latch the MAX PWR SAV signal before the BTI transition has been cleared from the delay line of the DLL circuit 30. As illustrated, the latch 158 can include an inverter 170, an inverter 172, an SR latch 174, and an inverter pair 176.

[0058] The MAX PWR SAV signal can be supplied along line 162 into inverter 170. The signal RSTF (or RST with a different number of inverters) can be supplied along line 180 into inverter 172. The RSTF signal can represent the output of the NOR gate 160 or other combinational circuitry based on the MAX PWR SAV, WrDynRtt, WrNomRtt, and RdNomRtt signals. Inverter 170 can invert the MAX PWR SAV signal and output the inverted signal to the reset input of SR latch 174, and inverter 172 can invert the RSTF signal and output the inverted signal to the set input of SR latch 174. When the MAX PWR SAV signal transitions low, the output of SR latch 174 can not transition low before the reset signal indicating a clear pipeline 50 is also high. Once the reset signal is high, the output of SR latch 174 can transition. When the output from SR latch 174 transitions, the MAX PWR SAVd signal transitions low, and the memory device also transitions. Otherwise, the MAX PWR SAVd signal does not transition since the memory device 10 is still in the power save mode and / or the pipeline 50 does not have a forced switch introduced. The output of SR latch 174 can supply its input to inverter pair 176, which can be used to match the timing of the signal to the current clock and / or amplify the MAX PWR SAVd signal.

[0059] By employing the techniques described in this disclosure, the systems and methods described herein can allow for mitigating BTI degradation when the memory device 10 is in the power save mode by causing the delay line switching of the DLL circuit 30. The switching can stop each time an RTT command is detected in the pipeline 50 and the RTT command resumes after the RTT command timing has expired. Further, contention at DQS can be avoided when a forced switch is introduced through all of the delay lines of the DLL circuit 30 or when an early power save mode idle mode exit command is sent. Additionally, the forced switch state of the delay lines of the DLL circuit 30 and the RTT command state can be swapped between to avoid any false RTT state changes and DQ contention. The introduction of the forced switch can occur at any location within the pipeline 50.

[0060] While only certain features of this disclosure have been illustrated and described, many modifications and changes will occur to those skilled in the art. For example, the signal polarity for assertion can be reversed for at least some signals in which a logical low is asserted and a logical high is de-asserted. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the embodiments described herein. Accordingly, no limitation is intended. The scope of the disclosure is limited only by the following claims and the regions of equivalents thereof.

[0061] The technology presented and claimed herein is to be understood to apply to any presently-existing or future technology that performs the same functions as described below, whether the technology is expressly described herein or not. The technology presented and claimed herein is to be understood to apply to any present or future technology that performs the same functions as described below, whether the technology is expressly described herein or not. Furthermore, the technology presented and claimed herein is to be understood to apply to any technology that performs the same functions by equivalent means, whether the technology is expressly described herein or not.

Claims

1. A memory device, comprising: a command pipeline configured to receive a plurality of command types for the memory device, wherein the command pipeline comprises delay-locked loop (DLL) circuitry; and switching circuitry configured to introduce a switching signal into at least a portion of the command pipeline when the memory device is in a power save mode and the command pipeline does not contain a valid command, wherein the introduced switching signal is configured to switch a gate voltage of a component of the DLL circuitry.

2. The memory device of claim 1, wherein the component of the DLL circuitry comprises a transistor on a delay line used by the DLL circuitry.

3. A memory device, comprising: a command pipeline configured to receive a plurality of command types for the memory device, wherein the command pipeline comprises delay-locked loop (DLL) circuitry; and switching circuitry configured to introduce a switching signal into at least a portion of the command pipeline when the memory device is in a power save mode and the command pipeline does not contain a valid command, wherein the switching circuitry is configured to introduce the switching signal when there is no valid command in the command pipeline for the power save mode, and wherein the introduced switching signal is configured to switch a gate voltage of a component of the DLL circuitry.

4. The memory device of claim 3, wherein the valid command consists of a non-targeted write command and a non-targeted read command.

5. The memory device of claim 3, wherein when the switching signal is introduced, the switching circuitry is configured to switch a path for the valid command.

6. The memory device of claim 5, wherein when the switching signal is introduced, a path for at least one invalid command is also switched, wherein the at least one invalid command comprises a command designated as not permitted by a host device in the power save mode.

7. The memory device of claim 6, wherein the at least one invalid command comprises a write command.

8. The memory device of claim 6, wherein the switching circuitry comprises resolution circuitry configured to resolve contention at data (DQ) lines of the memory device with the switching of the path for the at least one invalid command.

9. The memory device of claim 8, wherein resolving contention at the DQ lines comprises preventing activation of a data strobe (DQS) to capture DQ pulses when the power save mode is active and the path for the at least one invalid command is pulsed high.

10. The memory device of claim 8, wherein the switching circuitry comprises delay circuitry configured to delay the DQ lines to compensate for a delay in the resolution circuitry.

11. A method of operating a memory device, comprising: receiving an assertion of a power save mode signal at switching circuitry of the memory device as an indication of activation of a power save mode; and During the power save mode, a toggle signal is introduced from the toggle circuitry into a command pipeline, where the command pipeline includes delay-locked loop, DLL, circuitry, where introducing the toggle signal includes toggling a first path associated with a first command and a second path associated with a second command, where the first command includes a valid command that can be received from a host device to the memory device in the power save mode, and the second command includes an invalid command that cannot be received from the host device to the memory device in the power save mode, and where the introduced toggle signal is configured to toggle a gate voltage of a component of the DLL circuitry.

12. The method of claim 11, including disabling a data strobe for capturing a data signal via resolution circuitry when the indication of activation of the power save mode coincides with an assertion of toggling via the second path.

13. The method of claim 12, including delaying an on-die termination signal associated with the data signal to compensate for a delay in the resolution circuitry.

14. The method of claim 11, including: receiving a de-assertion of the power save mode signal at a delay circuitry; and delaying propagation of the de-assertion of the power save mode signal.

15. The method of claim 14, where delaying the propagation of the de-assertion of the power save mode signal includes delaying the propagation of the de-assertion of the power save mode signal until receiving a clear signal indicating that the command pipeline is free of the toggle signal.

16. The method of claim 15, where delaying the propagation includes using a latch to delay propagation of the de-assertion of the power save mode signal, the latch receiving the clear signal at a reset pin of the latch.

17. The method of claim 15, where the clear signal is based on a plurality of logic gates receiving the power save mode signal and an on-die termination signal for the first command and the second command.

18. The method of claim 15, including: counting a first number of pulses of the toggle signal introduced into the command pipeline; counting a second number of pulses of the toggle signal exiting the command pipeline; and asserting the clear signal when the first number equals the second number.

19. A memory system, comprising: a command pipeline including delay-locked loop, DLL, circuitry; toggle circuitry configured to introduce a toggle signal into a plurality of command paths for at least a portion of the command pipeline when the system is in a power save mode and a first command type and a second command type are not in the command pipeline, where a command path of the plurality of command paths corresponds to a command that is not valid during the power save mode, and where the introduced toggle signal is configured to toggle a gate voltage of a component of the DLL circuitry; and a resolution circuitry configured to disable a data strobe for capturing a data signal when the indication of activation of the power save mode coincides with an assertion of toggling via the second path. Circuitry to address configured to deactivate a data strobe for capturing data on a data signal line when the power saving mode is active and a signal corresponding to the command path is asserted.

20. The memory system of claim 19, wherein the switching circuitry is configured to suppress introduction of the switching signal when a test mode is active for the system.

21. The memory system of claim 19, wherein the first command comprises a non-targeted read command and the second command comprises a non-targeted write command.

22. The memory system of claim 19, wherein the command comprises a write command.

Images