System, method and application for debugging interface of analog chip

Abstract

In order to solve the problem of low actual execution efficiency caused by frequent data update when debugging the chip interface of the ATE device in the prior art, the application provides a system, a method and an application for simulating the debugging interface of a chip, comprising: an input module, a debugging interface device and a chip to be tested; wherein the input module is used for inputting debugging instructions; the debugging interface device interacts with the input module to batch store the debugging instructions; the chip to be tested interacts with the debugging interface device to generate corresponding protocols according to any debugging instruction and the debugging interface device to test the chip to be tested; the system has the advantages of simple structure, and does not need to frequently update data to the DIO unit of the hardware, can batch update data, uniformly trigger transmission, and improves the execution efficiency of the ATE device simulating the debugging interface of the chip.

Description

Technical Field

[0001] This invention relates to the field of ATE equipment, and more particularly to a system, method, and application of a debugging interface for an analog chip. Background Technology

[0002] Automated test equipment is a type of computer-controlled device used to test components, circuit boards, and subsystems. By replacing manual labor with computer programming to automate test sequences, it has become an important part of the global semiconductor equipment industry.

[0003] Automated test equipment (ATE) is used across the entire integrated circuit industry chain, primarily encompassing chip design verification, wafer manufacturing-related testing, and final product testing after packaging. In the final testing phase, ATE equipment uses debug interfaces (JTAG, SWD) to verify chip functionality and also verifies the debug interfaces themselves. Each business board in an ATE device is equipped with two FPGAs, each implementing different functions. In practical applications, FPGA debugging during production typically uses the JTAG interface for programming and debugging. However, when the FPGA is actually used in a product, the JTAG interface is too complex. Therefore, if an FPGA program needs updating, an online upgrade must be used. This involves downloading the new FPGA program to Flash memory, and under certain conditions, loading the new FPGA program from Flash to complete the online upgrade.

[0004] like Figure 1 The debugging method shown uses a simulator and dedicated simulation software, which cannot be used on ATE equipment; for testing ATE equipment, existing methods all employ methods such as... Figure 2 The DIO unit pattern file shown is used to simulate the debugging interface:

[0005] like Figure 3 As shown, during the testing process, the user writes a Pattern file, i.e., EditPattern, and uses the DIO unit of the ATE device to simulate the debugging interface; in order to generate specific data for the debugging interface, the Pattern file needs to be continuously updated, i.e., the UpdatePattern operation is continuously performed through the software interface.

[0006] During this process, updating the Pattern file requires an UpdatePattern operation via a software interface, continuously updating data to the hardware DIO unit; frequent data update operations result in low actual execution efficiency; for example, updating the bin file in the chip's flash memory via the debug interface requires updating data hundreds of kilobytes to megabytes.

[0007] An efficient testing method for ATE equipment is urgently needed. Summary of the Invention

[0008] To overcome the shortcomings of the prior art, the present invention provides a system, method and application for a debugging interface for an analog chip, for solving at least one of the aforementioned technical problems.

[0009] Specifically, the technical solution is as follows:

[0010] A system for a debugging interface of an analog chip, comprising:

[0011] The input module is used to input debugging commands;

[0012] A debugging interface device interacts with the input module to store the debugging instructions in batches;

[0013] The chip under test interacts with the debugging interface device to perform testing on the chip under test according to any of the debugging instructions and the corresponding protocol generated in the debugging interface device.

[0014] The debugging interface device includes:

[0015] A debug command sequence module, connected to the input module, is used to batch write at least two of the debug commands;

[0016] The protocol generation module is located between the debug command sequence module and the chip under test. It is used to continuously read the debug instructions stored in the debug command sequence module and generate the corresponding protocol with the chip under test to complete the relevant tests.

[0017] The input module is connected to the protocol generation module and is used to send a start debugging command, causing the protocol generation module to continuously read the debugging commands stored in the debugging command sequence module.

[0018] The debug command sequence module includes:

[0019] At least two simple domain units are set within the debug command sequence module to store the debug instructions;

[0020] The simple domain unit includes:

[0021] One or more of the following: sequence data, read / write data, address data, and instruction content data.

[0022] A method for debugging an interface based on the analog chip of the system, comprising:

[0023] The user continuously inputs debugging commands to test the chip under test;

[0024] All the aforementioned debugging commands are written in batches into the debugging command sequence module by calling the write instruction;

[0025] By driving the protocol generation module, the debug commands in the debug command sequence module are continuously read;

[0026] The protocol generation module converts any of the debugging commands into corresponding debugging interface signals to test the chip under test.

[0027] The debugging commands are stored in the following format during the process of being written to the debugging command sequence module: Seq / OP / Address / Data;

[0028] Wherein, Seq represents a sequence; OP represents read or write; Address represents the address of the debug command; and Data represents the data content of the debug command.

[0029] The user drives the protocol generation module to read the debugging command by calling the Start interface.

[0030] An electronic device with a debugging interface, comprising:

[0031] One or more processors;

[0032] Storage device for storing one or more programs.

[0033] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described above for a debug interface based on the analog chip of the system.

[0034] A computer-readable medium having a computer program stored thereon, characterized in that, when the program is executed by a processor, it implements the method for a debugging interface based on an analog chip of the system as described above.

[0035] The present invention has at least the following beneficial effects:

[0036] The system of this invention inputs the required debugging commands through an input module; then stores all the debugging commands in a debugging interface device; the chip under test interacts with the debugging interface device, and tests the chip under test according to any of the debugging commands and the corresponding protocol generated in the debugging interface device; the system of this invention does not require continuous updating of the pattern file when testing the chip under test, but instead uses the debugging interface device to batch store the debugging commands and then generates the corresponding communication protocol for the debugging commands, and the debugging interface device continuously reads the debugging commands and completes the testing of the chip under test in accordance with the relevant protocol; the system of this invention has the advantages of simple structure and efficient and fast testing.

[0037] The method described in this invention involves writing all the debugging commands in batches into the debugging command sequence module by calling a write instruction; continuously reading the debugging commands from the debugging command sequence module by driving the protocol generation module; and converting any of the debugging commands into a corresponding debugging interface signal to test the chip under test. This method has the advantage of a simple process, eliminates the need for frequent data updates to the hardware's DIO unit, enables batch data updates, and provides unified transmission triggering, thereby improving the execution efficiency of the ATE equipment's analog chip debugging interface. Attached Figure Description

[0038] In the following, various embodiments of the invention will be described more fully. The invention may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of the invention to the specific embodiments disclosed herein, but rather the invention should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments disclosed herein.

[0039] The terminology used in the various embodiments disclosed herein is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments disclosed herein. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments disclosed herein pertain. The terms (such as those defined in commonly used dictionaries) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments disclosed herein.

[0040] Figure 1 This is a traditional simulator-based test system;

[0041] Figure 2 Use the Pattern file for the DIO unit to simulate the debugging interface schematic;

[0042] Figure 3 for Figure 2 The test timing diagram of the Pattern file of the DIO unit is shown.

[0043] Figure 4 This is a block diagram of the system described in this invention;

[0044] Figure 5 This is a schematic diagram of the structure of a simple domain in the system described in this invention;

[0045] Figure 6 This is a timing diagram of the system described in this invention;

[0046] Figure 7 This is a flowchart of the method described in this invention;

[0047] Among them, 100. Input module; 200. Debug interface device; 300. Chip under test; 201. Debug command sequence module; 202. Protocol generation module; 2011. Simple domain unit; Detailed Implementation

[0048] Those skilled in the art will understand that the modules in the apparatus of the implementation scenario can be distributed within the apparatus of the implementation scenario as described, or they can be located in one or more apparatuses different from this implementation scenario, with corresponding changes. The modules of the above-described implementation scenario can be combined into one module, or they can be further divided into multiple sub-modules.

[0049] Definitions:

[0050] Pattern file: The test equipment generates a set of signals according to the requirements of the test procedure. This set of signals together forms a test Pattern file.

[0051] The UpdatePattern operation: an operation to update the Pattern file;

[0052] WriteCmd: Write command;

[0053] During the testing of ATE equipment, taking Memory IC as an example, the test items generally consist of DC to AC parameter testing plus functional testing. DC parameter testing includes Signal Pin Open / Short, VCC Pin Open / Short, Standby, and ICC current and leakage current tests during operation. AC parameter testing mainly comes from TCAC Test, which targets timing tests: Setup Time, Hold Time, Propagation Delay, and timing calibration. In all of the above tests, it is necessary to frequently update the Pattern file to the hardware DIO unit.

[0054] like Figure 2-3 In the existing technology shown, when performing chip debugging on ATE equipment, updating the Pattern file requires an UpdatePattern operation via a software interface. This involves continuously updating the new Pattern file data to the hardware DIO unit, resulting in frequent data update operations and low actual execution efficiency. To solve the above technical problem, this invention provides an embodiment:

[0055] Specific Implementation Example I:

[0056] like Figure 4-6 A system for a debugging interface of an analog chip includes: an input module 100, a debugging interface device 200, and a chip under test 300; wherein, the input module 100, such as a keyboard, is used to input debugging commands; the debugging interface device 200 interacts with the input module 100 and can store the debugging commands in batches; the chip under test 300 interacts with the debugging interface device 200 and can test the chip under test 300 according to any of the debugging commands and the corresponding protocol generated in the debugging interface device 200.

[0057] Specifically, the debugging interface device 200 includes: a debugging command sequence module 201 and a protocol generation module 202; wherein, the debugging command sequence module 201 is connected to the input module 100 and is used to batch write at least two debugging instructions; the protocol generation module 202 is disposed between the debugging command sequence module 201 and the chip under test 300, and is used to continuously read the debugging instructions stored in the debugging command sequence module 201 and generate corresponding protocols with the chip under test 300 to complete the relevant tests;

[0058] During use, the input module 100 is connected to the protocol generation module 202 to send a start debugging command, causing the protocol generation module 202 to continuously read the debugging commands stored in the debugging command sequence module 201.

[0059] In existing technologies, ATE equipment uses a pattern simulation scheme with DIO units, requiring pattern files to be written that are over a hundred lines long, which is very complex. To solve the above problem, in the system described in this invention:

[0060] like Figure 5 The debug command sequence module 201 includes at least two simple field units 2011. These simple field units 2011 are located within the debug command sequence module 201 and are used to store the debug commands. Each simple field unit 2011 includes one or more of sequence data, read / write data, address data, and instruction content data. In use, the user calls WriteCmd to batch write debug commands to the DebugCmdSeq unit. The specific DebugCmdSeq unit only contains the simple fields Seq / OP / Address / Data. User operation is simple; only sequence data, read / write data, address data, and instruction content data need to be input, eliminating the need for excessive commands and reducing user complexity.

[0061] In this article, the DebugCmdSeq unit refers to the debug command sequence module 201;

[0062] The protocolGenerate unit refers to: Protocol Generation Module 202;

[0063] Specific Implementation Example II:

[0064] like Figure 7 Based on the system described in specific embodiment I, the present invention also provides:

[0065] A method for debugging an analog chip based on the system includes: a user inputting debugging commands for testing the chip under test; writing all the debugging commands in batches into a debugging command sequence module 201 by calling a write instruction; continuously reading the debugging commands in the debugging command sequence module 201 by driving the protocol generation module 202; the protocol generation module 202 converting any one of the debugging commands into a corresponding debugging interface signal to test the chip under test 300; in use, the user can drive the protocol generation module 202 to continuously read the debugging commands by calling the Start interface; the protocol generation module 202 converts any one of the debugging commands into a corresponding debugging interface signal to test the chip under test 300; the testing process is concentrated on the data interaction between the debugging command sequence module 201 and the protocol generation module 202, without the need for excessive updates to the Pattern file, thus improving work efficiency;

[0066] In practical use, the following steps can be used for testing;

[0067] The user inputs debugging commands for testing the chip under test, and then writes all the debugging commands in batches to the DebugCmdSeq unit by calling the WriteCmd command; the DebugCmdSeq unit only contains the simple fields Seq / OP / Address / Data; the user calls the Start interface to drive the protocolGenerate unit to continuously read the debugging commands in the DebugCmdSeq unit; the protocol generation module 202 converts any of the debugging commands into a corresponding debugging interface signal to test the chip under test 300;

[0068] After understanding the method described in this embodiment, after using the WriteCmd command to write all the debugging commands in batches to the DebugCmdSeq unit, the user calls the Start interface to drive the protocolGenerate unit to continuously read the DebugCmdSeq unit, that is, to continuously read the debugging commands in the debugging command sequence module 201 to realize the testing of the ATE device. Since the instruction interface stored in the DebugCmdSeq unit is not a simple domain unit, although the test process is simplified to a certain extent, the instruction structure is still very complex, often exceeding hundreds of lines, making it complicated to write and prone to errors.

[0069] To address the problem of existing pattern files being over a hundred lines long and extremely complex, in this embodiment, the debugging commands are stored in the following format during the writing process to the debugging command sequence module 201: Seq / OP / Address / Data; where Seq represents a sequence; OP represents read or write; Address represents the address of the debugging command; and Data represents the data content of the debugging command. This method significantly reduces the complexity of user input commands and lowers the difficulty for users to debug chips using ATE equipment by providing a simple debugging interface software interface.

[0070] Specific examples:

[0071] If the ATE device uses the DIO unit's Pattern emulation scheme, downloading a 100kByte bin to flash requires:

[0072] 100K*UpdatePattern*PatternRun=10s;

[0073] In other words, using the existing Pattern simulation scheme, due to the complexity of writing commands, it takes 10 seconds to download a 100kByte bin, which shows that the efficiency is very low.

[0074] When using the method described in this invention, the time consumed for a single command operation is as follows:

[0075] UpdatePattern = 10us

[0076] Pattern Run = 10us

[0077] 100K DmaRamUpdate = 100us

[0078] ProtocolGenerate = 100us;

[0079] Using the method described in this application, downloading a 100kByte bin file to flash also requires:

[0080] DmaRamUpdate*ProtocolGenerate = 10ms for 100K data;

[0081] As can be seen, the efficiency of the simple field instruction described in this invention can be improved by 1000 times. Therefore, in this embodiment, the user calls WriteCmd to write debugging commands to the DebugCmdSeq unit in batches. The specific DebugCmdSeq unit only contains the simple field Seq / OP / Address / Data, which makes the operation simple for the user and effectively improves the processing efficiency.

[0082] The present invention also provides an embodiment:

[0083] An electronic device with a debugging interface includes: one or more processors and a storage device; wherein the storage device is used to store one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method of debugging an analog chip based on the system as described in Specific Embodiment II.

[0084] In the aforementioned electronic device, the storage medium is preferably a portable hard drive, a solid-state drive, or a USB flash drive; the processing unit, preferably a CPU, exchanges data with the storage medium and executes the computer program through the processing unit when a status update notification is received, performing the steps of the method for debugging the analog chip interface of the system as described above.

[0085] The aforementioned CPU can execute various appropriate actions and processes according to the program stored in the storage medium. The electronic device also includes peripherals such as input sections including a keyboard, mouse, etc., and may also include output sections such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; particularly, according to the embodiments disclosed in this invention, such as... Figure 7 Any of the processes described herein can be implemented as computer software programs.

[0086] This invention provides an embodiment including a computer program product comprising a computer program carried on a computer-readable medium, the computer program including functions for performing... Figure 7 The program code for the method shown in any of the flowcharts; the computer program can be downloaded and installed from the network, and when the computer program is executed by the CPU in the computer, it performs the functions defined in the system of the present invention.

[0087] The present invention also provides an embodiment:

[0088] A computer-readable storage medium: the computer-readable storage medium stores a computer program; when the computer program is run, it executes the steps of the method for the debugging interface of the analog chip based on the system as described in Specific Embodiment II.

[0089] In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0090] The above descriptions only cover a few specific embodiments of the present invention. However, the present invention is not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention. The above-mentioned serial numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

Claims

1. A system for a debugging interface of an analog chip, characterized in that, include: The input module is used to input debugging commands; A debugging interface device interacts with the input module to store the debugging commands in batches; The chip under test interacts with the debugging interface device to test the chip under test according to any of the debugging commands and the corresponding protocol generated in the debugging interface device. The debugging interface device includes: A debug command sequence module, connected to the input module, is used to batch write at least two of the debug commands; A protocol generation module is set between the debug command sequence module and the chip under test. It is used to continuously read the debug commands stored in the debug command sequence module and generate the corresponding protocol with the chip under test to complete the relevant tests. The input module is connected to the protocol generation module and is used to send a start debugging command, so that the protocol generation module starts to continuously read the debugging commands stored in the debugging command sequence module; The debug command sequence module includes: At least two simple domain units are set within the debug command sequence module to store the debug commands; The simple domain unit includes: One or more of the following: sequence data, read / write data, address data, and instruction content data; After writing all the debugging commands in batches to the debugging command sequence module using the write instruction, the user calls the Start interface to drive the protocol generation module to continuously read the debugging command sequence module, that is, to continuously read the debugging commands in the debugging command sequence module to realize the testing of the ATE device.

2. The method based on the debugging interface of the analog chip of the system as described in claim 1, characterized in that, include: The user continuously inputs debugging commands to test the chip under test; All the aforementioned debugging commands are written in batches into the debugging command sequence module by calling the write instruction; By driving the protocol generation module, the debug commands in the debug command sequence module are continuously read; The protocol generation module converts any of the debugging commands into corresponding debugging interface signals to test the chip under test.

3. The method for debugging the analog chip interface according to claim 2, characterized in that: The debugging commands are stored in the following format during the process of being written to the debugging command sequence module: Seq / OP / Address / Data; Wherein, Seq represents a sequence; OP represents read or write; Address represents the address of the debug command; and Data represents the data content of the debug command.

4. An electronic device with a debugging interface, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors perform the method as described in any one of claims 2-3.

5. A computer-readable medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 2-3.

6. An application of the method as described in any one of claims 2-3 in debugging the interface of an ATE device.

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