A low-power storage and computing architecture FPGA

Abstract

The present application discloses a low-power storage and computing architecture FPGA, which relates to the field of FPGA. In the FPGA, resource modules and interconnected resources located in the same sub-area are implemented as a storage and computing unit. The local storage units in each storage and computing unit transmit data with the outside of the FPGA chip through a global read-write channel. The FPGA implements multi-core parallel storage and computing operations through multiple storage and computing units, and the clock cycles of the driving clocks of all storage and computing units are the same. There is a time delay between the driving clocks of at least two storage and computing units. Therefore, on the basis of ensuring that each storage and computing unit works in parallel and synchronously to improve data processing efficiency, the starting moments of the multiple storage and computing units are distributed to different moments of the clock cycle, thereby reducing the instantaneous current increase caused by the current drawn by the storage and computing unit when starting at each moment, so that the overall maximum instantaneous current of the entire FPGA chip is lower, thereby reducing power consumption.

Description

Technical Field

[0001] The present application relates to the field of FPGA technology, and in particular to a low-power storage and computing architecture FPGA. Background Art

[0002] With the development of high-tech technologies such as the Internet of Things, cloud computing, and artificial intelligence, various data-intensive applications based on hardware platforms have also grown dramatically. FPGA (Field Programmable Gate Array) is a commonly used hardware platform due to its advantages of parallelism and reconfigurability.

[0003] The existing FPGA, like most traditional hardware platforms, adopts the von Neumann architecture. The FPGA contains a large number of resource modules such as CLB, DSP and BRAM. These resource modules are connected by highly configurable interconnects to form computing units and storage units in the FPGA. BRAM is an important on-chip storage unit. On-chip data is mainly stored in BRAM, and on-chip data must be transferred to the computing unit during calculation.

[0004] Therefore, existing FPGAs, like other hardware platforms that use the von Neumann architecture, need to repeatedly transfer large amounts of data between storage units and computing units when performing various computing tasks. Frequent and large-scale data movement not only consumes a large amount of wiring resources and interconnection resources, but also causes huge delays and energy losses, thereby limiting the data processing efficiency of FPGAs. Summary of the invention

[0005] In response to the above problems and technical requirements, the applicant has proposed a low-power storage and computing architecture FPGA. The technical solution of this application is as follows:

[0006] A low-power storage and computing architecture FPGA, the storage and computing architecture FPGA includes a plurality of resource modules arranged according to a predetermined structure, interconnection resources arranged around the resource modules, and a global read-write channel realized by additional hardware resources. The resource modules located in the same sub-area are connected through the interconnection resources to realize a storage and computing unit. The local storage unit in each storage and computing unit is used to store instructions and data of the storage and computing unit. The processor in the storage and computing unit is connected to the local storage unit via the interconnection resources. The local storage unit in each storage and computing unit transmits data with the outside of the FPGA chip through the global read-write channel.

[0007] Multiple storage and computing units in the storage and computing architecture FPGA work in parallel and synchronously to complete storage and computing operations. Each storage and computing unit starts according to its own driving clock and performs operations according to the instructions and data stored in the local storage unit. The clock period of the driving clocks of all storage and computing units is the same, there is a delay between the driving clocks of at least two storage and computing units, and the maximum delay between all driving clocks does not exceed the clock period.

[0008] Its further technical solution is that each storage and computing unit starts at the rising edge of its own driving clock, and the total instantaneous current generated by the storage and computing unit in the storage and computing architecture FPGA at any time does not exceed the current upper limit threshold.

[0009] Its further technical solution is that multiple storage computing units in the storage computing architecture FPGA that work in parallel and synchronously to complete a storage computing operation use a total of C groups of driving clocks, each storage computing unit is connected to a group of driving clocks, and each group of driving clocks is connected to and drives one or more storage computing units, C≥2;

[0010] The sequence of rising edges of each group of driving clocks in the same clock cycle is the same as the data flow sequence of the data processed by the storage and computing units driven by each group of driving clocks; the later the data flow sequence of the data processed by the storage and computing units driven by a group of driving clocks is, the later the rising edges of a group of driving clocks in each clock cycle are, and the later the starting sequence of the storage and computing units driven by a group of driving clocks is in each clock cycle.

[0011] A further technical solution is that the storage and computing units implemented in each sub-region are arranged to form a two-dimensional row and column structure:

[0012] The storage and calculation units in the same column are connected to the same driving clock, and the storage and calculation units in different columns are connected to different driving clocks. The intermediate calculation data generated by the storage and calculation units in any i-th column are sequentially transmitted to the adjacent storage and calculation units in the i+1th column for calculation. The rising edge of the driving clock connected to the storage and calculation unit in the i+1th column in each clock cycle is later than the rising edge of the driving clock connected to the storage and calculation unit in the i-th column.

[0013] Alternatively, the storage and computing units in the same row are connected to the same driving clock, and the storage and computing units in different rows are connected to different driving clocks. The intermediate calculation data generated by the storage and computing units in any j-th row are sequentially transmitted to the storage and computing units in the adjacent j+1-th row for calculation. The rising edge of the driving clock connected to the storage and computing units in the j+1-th row in each clock cycle is later than the rising edge of the driving clock connected to the storage and computing units in the j-th row.

[0014] Among them, i and j are parameters.

[0015] A further technical solution is that, when C≥3, all delay offsets in one clock cycle are equal or there are at least two unequal delay offsets, and one delay offset is the duration between the rising edges of any two adjacent groups of driving clocks.

[0016] Its further technical solution is that the difference between the number of storage and computing units connected to each group of driving clocks does not exceed the numerical threshold, all delay offsets within a clock cycle are equal and each delay offset d=P / C, where P is the length of a clock cycle.

[0017] A further technical solution is that each delay offset within a clock cycle is determined based on the instantaneous current estimation value of each storage and calculation unit connected and driven by each group of driving clocks during the startup and operation process.

[0018] A further technical solution is that the delay offset Tc between the rising edge of any cth group of drive clocks and the rising edge of the c+1th group of drive clocks adjacent thereto within a clock cycle is equal to the delay between the start time of all storage and calculation units connected and driven by the cth group of drive clocks and the time when the total instantaneous current estimate value generated drops to the current lower limit threshold, and c∈[1,C] is a parameter.

[0019] Its further technical solution is that the time delay offset Tf between the rising edge of any f-th group of drive clocks and the rising edge of the f+1-th group of drive clocks adjacent thereto within a clock cycle is a random number between the value of P / C and the value range of the minimum difference value of the f-th group of drive clocks, and the minimum difference value of the f-th group of drive clocks is the delay between the start time of all storage and calculation units connected to the f-th group of drive clocks and the time when the total instantaneous current estimate value generated drops to the current lower limit threshold.

[0020] A further technical solution is that each delay offset within a clock cycle is a random number.

[0021] The beneficial technical effects of this application are:

[0022] The present application discloses a low-power storage and computing architecture FPGA, in which resource modules located in the same sub-area of ​​the FPGA are connected through interconnection resources inside the FPGA to realize a storage and computing unit, and the local storage unit in each storage and computing unit transmits data with the outside of the FPGA through a global read-write channel. The FPGA can realize multi-core parallel storage and computing operations through multiple storage and computing units, and the clock cycle of the driving clocks of all storage and computing units is the same, and there is a time delay between the driving clocks of at least two storage and computing units. On the basis of ensuring that each storage and computing unit works in parallel and synchronously in the same clock cycle to improve data processing efficiency, the starting moments of multiple storage and computing units are distributed to different moments of the clock cycle, thereby reducing the superposition effect of the storage and computing units of the whole chip, reducing the instantaneous current increase caused by the current drawn by the storage and computing units at each moment, so that the overall maximum instantaneous current of the whole FPGA chip is low, thereby reducing power consumption.

[0023] The sequence of rising edges of the driving clocks used by different storage and computing units matches the data flow sequence, so that multiple storage and computing units are started in sequence according to the data flow transmission direction, which can ensure that the storage and computing operations are completed normally while reducing power consumption and not affecting the storage and computing process.

[0024] The present application also provides a variety of methods for determining the distribution of rising edges of each driving clock, which are suitable for different application scenarios. Each driving clock can be released in sequence and distributed into the clock cycle conveniently and quickly to reduce power consumption.

[0025] The processor and local storage unit of each storage unit are in the same sub-area. When executing, the processor only needs to read and write the instructions and data in the adjacent local storage unit, which reduces the wiring resources and interconnection resources consumed by data transmission between the processor and the local storage unit, reduces data transmission delay and energy loss, and improves the data processing efficiency of the FPGA. In addition, the FPGA can realize multi-core parallel storage and computing operations through multiple storage units. The processors of each storage unit will not cause conflicts with each other. Each storage unit can perform operations at full speed without being affected by the storage bandwidth, which can further improve the overall data processing efficiency and computing speed of the FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the arrangement of resource modules inside the FPGA in an example of the present application and a schematic diagram of the eight sub-areas obtained by division.

[0027] Figure 2 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown.

[0028] Figure 3 yes Figure 1 A connection diagram of the driving clocks of each storage and computing unit in the example shown.

[0029] Figure 4 yes Figure 3 Schematic diagram of the waveforms of the two sets of driving clocks.

[0030] Figure 5 yes Figure 1 Another connection diagram of the driving clock of each storage and computing unit in the example shown.

[0031] Figure 6 yes Figure 5 Schematic diagram of the waveforms of the four sets of driving clocks.

[0032] Figure 7 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown.

[0033] Figure 8 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown.

[0034] Fig. 9 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown. DETAILED DESCRIPTION

[0035] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0036] The present application discloses a low-power storage and computing architecture FPGA. The FPGA of the present application is the same as a conventional FPGA, and includes a number of resource modules arranged in a predetermined structure and interconnection resources arranged around the resource modules. The predetermined structure can be arranged according to actual conditions. For example, taking the currently mainstream Column-Based structure as an example, the resource modules are arranged in a row and column structure to form a two-dimensional array architecture. The same type of resource modules are arranged in each column, and interconnection resources are arranged around each resource module. The types of resource modules included in the FPGA include configurable logic modules CLB, configurable storage modules BRAM, and configurable multiplication and addition modules DSP. The configurable logic module CLB contains units such as lookup tables and registers, which can be configured to implement various logical functions. The configurable multiplication and addition module DSP contains arithmetic units that can perform multiple operations such as multiplication, addition, and multi-bit logic gates. The configurable storage module BRAM contains block storage units that can implement single-port and dual-port storage and FIFO storage of various widths and depths. Please refer to Figure 1The schematic diagram of the resource module inside the FPGA shown is a schematic diagram of the resource module inside the FPGA. This part of the structure follows the structure inside the existing FPGA and will not be elaborated in this application.

[0037] All resource modules arranged in a predetermined structure in the FPGA of the present application are divided into several sub-areas, each of which contains a certain number of resource modules. Resource modules in the same sub-area are connected through interconnection resources inside the FPGA to realize a storage and computing unit, and resource modules in multiple different sub-areas correspondingly realize multiple storage and computing units.

[0038] Each storage and computing unit includes its own processor and local storage unit. The processor in each storage and computing unit is connected to the local storage unit in the storage and computing unit via interconnection resources. The local storage unit in each storage and computing unit is used to store the instructions and data of the storage and computing unit, and the processor in each storage and computing unit is used to operate according to the instructions and data stored in the connected local storage unit.

[0039] This application does not limit the number and type of resource modules contained in each sub-area, but the number and type of resource modules contained in each sub-area must be sufficient to implement the processor and local storage unit in a storage and computing unit. The processor in a storage and computing unit is mainly implemented based on DSP, and the storage unit in a storage and computing unit is mainly implemented based on BRAM. In addition, a certain number of CLBs are also required.

[0040] In one embodiment, the instruction sets used by the two storage and computing units implemented by the resource modules in any two sub-areas are the same or different, and the bit widths of the two storage and computing units using the same instruction set are the same or different. In the present application, the storage and computing units formed in the FPGA can form various typical general-purpose 8-bit processors including RISC, 8051 and 6802.

[0041] In one embodiment, the number and type of resource modules contained in any two sub-areas obtained by division are the same, or in another embodiment, the number and type of resource modules contained in any two sub-areas obtained by division are at least one different, that is, the multiple sub-areas obtained by division may be completely the same or not necessarily the same. In addition, each resource module in the FPGA belongs to a sub-area, all resource modules in the FPGA are divided into corresponding sub-areas, or some resource modules in the FPGA are divided into corresponding sub-areas, that is, the FPGA can be divided into sub-areas globally or locally. For example, Figure 1 In the example shown, the resource modules inside the FPGA are divided into 8 sub-areas, each of which contains the same number and type of resource modules, and each area framed by a dotted box represents a sub-area obtained by the division.

[0042] In addition to resource modules and interconnection resources, the FPGA of the present application also adds additional hardware resources to implement global read and write channels compared to conventional FPGAs. The local storage unit in each storage unit transmits data to the FPGA chip through the global read and write channels. Figure 1 The resource modules in each sub-area shown implement a storage and computing unit. Figure 1 The schematic diagram of the storage and computing units implemented by the resource modules in each sub-area is as follows Figure 2 In addition, according to actual needs, the local storage unit in a storage and computing unit can also be connected to other BRAM modules inside the FPGA via the interconnection resources of the FPGA to realize data exchange.

[0043] The FPGA of this architecture of the present application forms multiple storage and computing units inside, and each storage and computing unit supports independent storage and computing operations in the form of a soft core. Therefore, the FPGA completes the storage and computing operations by working in parallel and synchronously through the multiple storage and computing units formed inside. A storage and computing operation implemented by the FPGA through multiple storage and computing units includes:

[0044] (1) First, the parameters of each storage and computing unit are written from outside the FPGA chip into the local storage unit of the corresponding storage and computing unit through the global read and write channel. The parameters written to the local storage unit of each storage and computing unit include the instructions and / or data of the storage and computing unit, that is, only instructions or data can be written to the storage and computing unit, or instructions and data can be written at the same time.

[0045] (2) Each storage and computing unit starts and operates in parallel according to its own driving clock. The processor in each storage and computing unit operates according to the instructions and data in the local storage unit of the storage and computing unit, and stores the operation results in the local storage unit of the storage and computing unit. The clock period of the driving clocks of all storage and computing units is the same, there is a delay between the driving clocks of at least two storage and computing units, and the maximum delay between the driving clocks of all storage and computing units does not exceed the clock period.

[0046] Since the FPGA of the present application needs to use multiple storage and computing units to work in parallel and synchronously to complete storage and computing operations, if all the storage and computing units start to draw current at the same time, the superposition effect of each storage and computing unit will easily cause the instantaneous current of the entire FPGA chip to increase, increase the load of the on-chip power supply network, and make it necessary to increase the design value of the maximum power consumption during physical design, which will lead to an increase in the chip area and affect the integration.

[0047] Therefore, in the present application, there is a time delay between the driving clocks of at least two storage and computing units, and the time delay does not exceed the clock cycle. Under the premise of ensuring that each storage and computing unit works in parallel and synchronously in the same clock cycle, the starting times of multiple storage and computing units are distributed to different times of the clock cycle, thereby reducing the superposition effect of the storage and computing units of the whole chip, and reducing the instantaneous current increase caused by the current drawn by the storage and computing units when starting at each moment, so that the overall maximum instantaneous current of the whole FPGA chip can be reduced, thereby reducing power consumption.

[0048] Based on this design idea, when each storage and computing unit starts at the rising edge of its respective driving clock, the total instantaneous current generated by the storage and computing unit at any time in the low-power storage and computing architecture FPGA does not exceed the current upper limit threshold. The current upper limit threshold can be customized according to the actual power consumption design requirements, thereby ensuring that the low power consumption requirements are met.

[0049] (3) The calculation results in the local storage unit of each storage and calculation unit can then be read out to the outside of the FPGA chip through the global read and write channel.

[0050] On this basis, according to actual needs, the FPGA can sequentially implement multiple storage and calculation operations through the internal storage and calculation units until all operations are completed. And when the FPGA implements any storage and calculation operation, the corresponding parameters are written from outside the FPGA chip to the local storage units of all storage and calculation units, or to the local storage units of some storage and calculation units. Similarly, the parameters here include the instructions and / or data of the storage and calculation units. All storage and calculation units or some storage and calculation units are started to perform parallel operations at the same time. Then the calculation results in the local storage units of all storage and calculation units or the calculation results in the local storage units of some storage and calculation units are read out to the outside of the FPGA chip. That is, when multiple storage and calculation operations are implemented, each storage and calculation operation can use all the storage and calculation units formed inside the FPGA, or only use some storage and calculation units and skip other storage and calculation units. When using some storage and calculation units, the same or different storage and calculation units can also be used multiple times. In addition, each storage and calculation operation can adjust the parameters written to each storage and calculation unit. Each storage and calculation operation can read the calculation results of all or some storage and calculation units. That is, the processes of executing multiple storage and computing operations are basically similar, but each storage and computing operation can flexibly adjust the data reading and writing of each storage and computing unit, without the need to perform the same data reading and writing operations on the local storage units in all storage and computing units every time.

[0051] Since the processor and local storage unit of each storage unit are in the same sub-area, the processor only needs to read and write the instructions and data in the adjacent local storage unit when executing, thus reducing the wiring resources and interconnection resources consumed by transmitting data between the processor and the local storage unit, reducing data transmission delay and energy loss, and improving the data processing efficiency of the FPGA. In addition, in a multi-core scenario, if multiple computing cores read and write the same main memory at the same time, the read and write bandwidth of the main memory will form a bottleneck, restricting the data processing efficiency. This problem will be particularly obvious in high-performance computing. For FPGAs that support artificial intelligence or machine learning applications, the FPGA generally has a large number of relatively simple computing cores inside, and the number of computing cores will exceed 100. The demand for the read and write bandwidth of the main memory is greater, and the problem is more prominent. The FPGA of this application is also a multi-core scenario. Since the processors in each storage unit read and write local storage units respectively, instead of all processors uniformly reading and writing the same memory, the processors of each storage unit will not cause conflicts with each other, and each storage unit can perform operations at full speed, which is not affected by the storage bandwidth, which is conducive to improving the overall data processing efficiency and computing speed. This makes the FPGA of the present application suitable for scenarios involving a large number of storage and computing units. Even if the number of storage and computing units exceeds 100, it can still have a high computing rate, thereby better supporting scenarios of artificial intelligence and machine learning.

[0052] The rising edges of the driving clocks of each storage and computing unit have a sequential relationship in timing. In order to better complete the storage and computing operation, in one embodiment, it is assumed that the multiple storage and computing units in the storage and computing architecture FPGA that work in parallel and synchronously to complete a storage and computing operation use a total of C groups of driving clocks, each storage and computing unit is connected to a group of driving clocks, and each group of driving clocks is connected to and drives one or more storage and computing units, C≥2. Then the sequence of the rising edges of each group of driving clocks in the same clock cycle is the same as the data flow sequence of the data processed by the storage and computing units driven by each group of driving clocks. The later the data flow sequence of the data processed by the storage and computing units driven by a group of driving clocks is, the later the rising edge of a group of driving clocks in each clock cycle is, and the later the start sequence of the storage and computing units driven by the driving clocks is in each clock cycle.

[0053] In storage and computing applications such as artificial intelligence, machine learning, and data model reasoning, data needs to be transferred between multiple storage and computing units that complete a storage and computing operation to form a data flow. For example, the calculation result obtained by one storage and computing unit will be transmitted to another storage and computing unit for use as intermediate data. The storage and computing units that are later in the data flow order of the processed data may rely on the data generated by the previous storage and computing units, and therefore can be started later without affecting the entire storage and computing operation process. Therefore, this embodiment sets the order of the rising edges of the driving clocks of each storage and computing unit according to the data flow order of the processed data.

[0054] On this basis, in one embodiment, when the storage and computing units implemented in each sub-region are as follows Figure 2 When the arrangement shown forms a two-dimensional row and column structure, there are two common implementation methods, where i and j are parameters: (1) The storage and computing units in the same column are connected to the same drive clock, and the storage and computing units in different columns are connected to different drive clocks. The intermediate data generated by any storage and computing unit in the i-th column is sequentially transmitted to the adjacent storage and computing unit in the i+1th column for calculation. The rising edge of the drive clock connected to the storage and computing unit in the i+1th column in each clock cycle is later than the rising edge of the drive clock connected to the storage and computing unit in the i-th column. That is, in this case, the data flow is transmitted between the storage and computing units in different columns along the row direction, such as based on Figure 2 The structure, such as Figure 3 As shown, each storage unit transmits data to the storage units in the same row of the right column. Then, the storage units 1 to 4 in the first column are connected to the same driving clock CLK1, and the storage units 5 to 8 in the second column are connected to the same driving clock CLK2. The clock cycles of the driving clocks of CLK1 and CLK2 are the same, and the rising edge of CLK1 is earlier than the rising edge of CLK2. There is a delay between the driving clocks of at least two storage units of CLK1 and CLK2, and the delay does not exceed the clock cycle. The timing waveform is shown in FIG. Figure 4 As shown. Alternatively, (2) the storage and computing units in the same row are connected to the same drive clock, and the storage and computing units in different rows are connected to different drive clocks. The intermediate data generated by the storage and computing units in any j-th row are sequentially transmitted to the adjacent storage and computing units in the j+1-th row for calculation. The rising edge of the drive clock connected to the storage and computing units in the j+1-th row in each clock cycle is later than the rising edge of the drive clock connected to the storage and computing units in the j-th row. Similar to case (1), except that in this case the data flow is transmitted between the storage and computing units in different rows along the column direction, such as based on Figure 2 The structure, such as Figure 5 As shown, each storage unit transmits data to the storage unit of the same column in the next row, then the storage unit 1 and storage unit 5 in the first row are connected to the same drive clock CLK3, the storage unit 2 and storage unit 6 in the second row are connected to the same drive clock CLK4, the storage unit 3 and storage unit 7 in the third row are connected to the same drive clock CLK5, and the storage unit 4 and storage unit 8 in the second row are connected to the same drive clock CLK6. The clock cycles of CLK3, CLK4, CLK5 and CLK6 are the same and the rising edges arrive in sequence, and the maximum delay between all drive clocks does not exceed the clock cycle. The timing waveform is shown in Figure 6 shown.

[0055] After determining the sequence of rising edges of the driving clocks of each storage and computing unit, the specific time of the rising edges of the driving clocks of each storage and computing unit and the delay between different drives can be adjusted as needed. These driving clocks are generated by the PLL resources provided by the FPGA, and the delay between each driving clock can be obtained by configuring the PLL.

[0056] When C ≥ 3, C groups of driving clocks will form C-1 delay offsets within a clock cycle. A delay offset is the duration between the rising edges of any two adjacent groups of driving clocks. Figure 6 In the timing waveform diagram, there is a delay offset skew1 between CLK3 and CLK4, a delay offset skew2 between CLK4 and CLK5, and a delay offset skew3 between CLK5 and CLK6. Then all delay offsets in a clock cycle are equal or there are at least two unequal delay offsets. The present application provides the following methods to determine each delay offset:

[0057] Method 1: All delay offsets within a clock cycle are equal and each delay offset d = P / C, where P is the length of a clock cycle. Figure 6 In the example, clock skew skew1=skew2=skew3=P / 4.

[0058] This method is particularly suitable for the case where the difference between the number of storage and computing units connected to each group of driving clocks does not exceed the numerical threshold, that is, the number of storage and computing units connected to each group of driving clocks is relatively even, and the number of storage and computing units started at the rising edge of each driving clock is close, and the instantaneous current increase caused by the start of the storage and computing units at the rising edge of each driving clock is basically equal. Therefore, the rising edges of each group of driving clocks can be directly evenly distributed in the clock cycle, and the configuration is more convenient.

[0059] Method 2, each delay offset within a clock cycle is determined based on the instantaneous current estimation value of each storage and computing unit connected and driven by each group of driving clocks during the startup and operation process. The instantaneous current estimation value here can be completed using the existing estimation method, and this embodiment does not limit this.

[0060] In one implementation of the method, the delay offset Tc between the rising edge of any c-th group of driving clocks and the rising edge of the c+1-th group of driving clocks adjacent thereto in a clock cycle is equal to the delay between the start time of all storage and calculation units connected to the c-th group of driving clocks and the time when the total instantaneous current estimation value generated drops to the current lower limit threshold, and c∈[1,C] is a parameter. The current lower limit threshold here can be customized according to actual needs.

[0061] In another implementation of the method, the delay offset T between the rising edge of any f-th group of driving clocks and the rising edge of the f+1-th group of driving clocks adjacent thereto in a clock cycle is f , is a random number between the value of P / C and the minimum difference value of the fth group of driving clocks.

[0062] The minimum difference value of the fth group of driving clocks is the delay between the start time of all storage and calculation units connected and driven by the fth group of driving clocks and the time when the total instantaneous current estimation value generated drops to the current lower limit threshold.

[0063] For example, Figure 5 Among the four groups of driving clocks shown, the delay between the start time of all storage and calculation units connected to CLK3 and the time when the total instantaneous current estimation value generated drops to the current lower limit threshold is t1, then a random number is taken as skew1 within the value range formed by t1 and P / 4.

[0064] Method 3: Each delay offset within a clock cycle is a random number. This method uses the characteristics of random function distribution to randomly disperse the rising edge of the driving clock within the clock cycle to reduce the maximum power consumption. This method can also be applied to situations that are difficult to estimate.

[0065] In one embodiment, when the predetermined structure adopted by the resource module arrangement inside the FPGA is a Column-Based structure, the BRAM module occupies one or more columns, and the local storage units in each storage and computing unit are implemented based on the BRAM module. Therefore, the BRAM module used to implement the local storage unit in each storage and computing unit is located in one or more columns, and the local storage unit in the storage and computing unit and several BRAM modules located in the same column are used to implement data transmission with the FPGA chip outside via the same global read-write channel. The FPGA chip can exchange data with any local storage unit connected to the global read-write channel via each global read-write channel. Based on this, the present application provides the following two methods to implement data transmission between the local storage unit in each storage and computing unit and the FPGA chip outside:

[0066] In one embodiment, several BRAM modules located in the same column and used to implement local storage units in the storage and computing units are connected to an on-chip read / write interface of the FPGA through the same global read / write channel to perform data transmission with the outside of the FPGA, and different global read / write channels are connected to different on-chip read / write interfaces of the FPGA. Figure 2In the example shown, 8 storage and computing units are formed inside the FPGA. The local storage units in storage and computing units 1 to 4 are implemented by BRAM modules located in the same column. The local storage units of these 4 storage and computing units are connected to the on-chip read-write interface 1 of the FPGA through the global read-write channel 1 to realize data transmission with the outside of the FPGA. The local storage units in storage and computing units 5 to 8 are implemented by BRAM modules located in the same column. The local storage units of these 4 storage and computing units are connected to the on-chip read-write interface 2 of the FPGA through the global read-write channel 2 to realize data transmission with the outside of the FPGA.

[0067] The method provided in the above embodiment often needs to occupy multiple on-chip read / write interfaces of the FPGA, and the on-chip read / write interface resources of the FPGA are relatively precious. Therefore, in another embodiment, only one on-chip read / write interface of the FPGA is needed to realize the local storage unit in the soft-core processor, and several BRAM modules located in the same column are connected to an active end of the multiplexer MUX through the same global read / write channel, and the fixed end of the multiplexer MUX is connected to the on-chip read / write interface of the FPGA. By selecting each active end of the multiplexer MUX, each global read / write channel can be selected, so that data can be exchanged with any local storage unit connected to the global read / write channel outside the FPGA chip via the selected global read / write channel. For example, in Figure 7 In the structure diagram shown, it corresponds to Figure 2 , the local storage units in storage and computing units 1 to 4 are connected to an active end of the multiplexer MUX through the global read-write channel 1, the local storage units in storage and computing units 5 to 8 are connected to the other active end of the multiplexer MUX through the global read-write channel 2, and the fixed end of the multiplexer MUX is connected to the on-chip read-write interface of the FPGA to realize data transmission with the outside of the chip, then compared with Figure 2 The method of this embodiment only needs to occupy one on-chip read / write interface of the FPGA.

[0068] According to the traditional von Neumann architecture, the instructions and data in each storage unit are mixed and stored. However, in order to improve the data processing efficiency, in one embodiment, according to the Harvard structure, the instructions and data of each storage unit are stored separately and independently. Then the local storage unit in a storage and computing unit includes an instruction local storage unit and a data local storage unit. The instruction local storage unit is used to store the instructions of the storage and computing unit, and the data local storage unit is used to store the data of the storage and computing unit, so that the instructions and data do not interfere with each other when the processor operates, thereby improving the data processing efficiency. The instruction local storage unit is implemented by at least one BRAM module, and the data local storage unit is implemented by at least one BRAM module. Therefore, based on this, a common sub-area includes at least one DSP, two BRAMs, and 300 CLBs.

[0069] When the local storage unit in each storage and computing unit includes an instruction local storage unit and a data local storage unit, the storage size of the instruction local storage units of any two storage and computing units is the same or different, and the storage size of the data local storage units of any two storage and computing units is the same or different.

[0070] When the local storage unit in each storage unit includes an instruction local storage unit and a data local storage unit: (1) In one embodiment, the instruction local storage unit and the data local storage unit in a storage unit share the global read / write channel for data transmission, and the instruction local storage unit and the data local storage unit in the storage unit and the data local storage unit in the same column are used to transmit data with the FPGA chip via the same global read / write channel. In this embodiment, the global read / write channel can be used as follows Figure 2 The method of the embodiment shown is connected to the on-chip read / write interface of the FPGA, or according to Figure 7 The method of the embodiment shown is connected to an active terminal of the multiplexer MUX. Figure 2 Take the structure shown in the figure as an example. Figure 8 As shown, the instruction local storage units and data local storage units in storage and computing units 1 to 4 are connected to the global read-write channel 1, and the instruction local storage units and data local storage units in storage and computing units 5 to 8 are connected to the global read-write channel 2. (2) Or in another embodiment, the instruction local storage units and data local storage units use their own global read-write channels respectively, and the instruction local storage units in a storage and computing unit transmit instructions via the instruction global read-write channel, and the data local storage units transmit data via the data global read-write channel. Then, the instruction local storage units in the storage and computing units and several BRAM modules in the same column transmit data with the outside of the FPGA chip via the same instruction global read-write channel, and the data local storage units in the storage and computing units and several BRAM modules in the same column transmit data with the outside of the FPGA chip via the same data global read-write channel. Similarly, in this embodiment, each instruction global read-write channel and data global read-write channel can be configured as follows: Figure 2 The method of the embodiment shown is connected to the on-chip read / write interface of the FPGA, or according to Figure 7 The method of the embodiment shown is connected to an active terminal of the multiplexer MUX. Figure 7 Take the structure shown in the figure as an example. Fig. 9The instruction local storage units in storage and computing units 1 to 4 are all connected to the instruction global read and write channel 1, the data local storage units in storage and computing units 1 to 4 are all connected to the data global read and write channel 1, the instruction local storage units in storage and computing units 5 to 8 are all connected to the instruction global read and write channel 2, the data local storage units in storage and computing units 5 to 8 are all connected to the data global read and write channel 2, the instruction global read and write channel 1, the data global read and write channel 1, the instruction global read and write channel 2 and the data global read and write channel 2 are respectively connected to an active end of the multiplexer MUX.

[0071] In another embodiment, the resource module in each sub-area is also used to implement the control signal and status signal of a corresponding storage and computing unit, the control signal is used to control the operating status of the storage and computing unit, and the status signal is used to display the operating status of the storage and computing unit. The control signal and status signal of the storage and computing unit are connected to other circuit structures inside the FPGA, or the control signal and status signal of the storage and computing unit are connected to the outside of the FPGA. That is, the control signal and status signal required by each storage and computing unit when performing storage and computing are implemented by the resource module in the corresponding sub-area.

[0072] The control signal of each storage and calculation unit includes at least one of an enable signal, a reset signal and an interrupt signal. The enable signal is used to control the corresponding storage and calculation unit to execute instructions or stop executing instructions. The reset signal is used to reset the storage and calculation unit. The interrupt signal provides external interrupt capability. The control signals of any two storage and calculation units are the same or different.

[0073] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A low-power storage and computing architecture FPGA, characterized in that: The storage and computing architecture FPGA includes a plurality of resource modules arranged in a predetermined structure, interconnection resources arranged around the resource modules, and a global read-write channel implemented by additional hardware resources. The resource modules located in the same sub-area are connected through the interconnection resources to implement a storage and computing unit. The local storage unit in each storage and computing unit is used to store instructions and data of the storage and computing unit. The processor in the storage and computing unit is connected to the local storage unit via the interconnection resources; the local storage unit in each storage and computing unit transmits data with the FPGA chip outside through the global read-write channel; The multiple storage and computing units in the storage and computing architecture FPGA work in parallel and synchronously to complete the storage and computing operations. Each storage and computing unit is started according to its own driving clock and performs operations according to the instructions and data stored in the local storage unit; The clock cycles of the driving clocks of all storage and computing units are the same, there is a delay between the driving clocks of at least two storage and computing units, and the maximum delay between all driving clocks does not exceed the clock cycle; the multiple storage and computing units that work in parallel and synchronously in the storage and computing architecture FPGA to complete a storage and computing operation use a total of C groups of driving clocks, each storage and computing unit is connected to a group of driving clocks, each group of driving clocks is connected to and drives one or more storage and computing units, C≥2; the sequence of the rising edges of each group of driving clocks in the same clock cycle is the same as the data flow sequence of the data processed by the storage and computing units driven by each group of driving clocks; The later the data flow order of the data processed by the storage and computing units driven by a group of driving clocks is, the later the rising edge of the group of driving clocks in each clock cycle is, and the later the starting order of the storage and computing units driven by the group of driving clocks is in each clock cycle.

2. The storage-computing architecture FPGA according to claim 1, characterized in that: Each storage and computing unit starts at the rising edge of its own driving clock, and the total instantaneous current generated by the storage and computing unit in the storage and computing architecture FPGA at any time does not exceed the current upper limit threshold.

3. The storage-computing architecture FPGA according to claim 1, characterized in that: The storage and computing units implemented in each sub-area are arranged to form a two-dimensional row and column structure: The storage and calculation units in the same column are connected to the same driving clock, and the storage and calculation units in different columns are connected to different driving clocks. The intermediate calculation data generated by the storage and calculation units in any i-th column are sequentially transmitted to the adjacent storage and calculation units in the i+1th column for calculation. The rising edge of the driving clock connected to the storage and calculation unit in the i+1th column in each clock cycle is later than the rising edge of the driving clock connected to the storage and calculation unit in the i-th column. Alternatively, the storage and computing units in the same row are connected to the same driving clock, and the storage and computing units in different rows are connected to different driving clocks. The intermediate calculation data generated by the storage and computing units in any j-th row are sequentially transmitted to the storage and computing units in the adjacent j+1-th row for calculation. The rising edge of the driving clock connected to the storage and computing units in the j+1-th row in each clock cycle is later than the rising edge of the driving clock connected to the storage and computing units in the j-th row. Among them, i and j are parameters.

4. The storage-computing architecture FPGA according to claim 1, characterized in that: When C≥3, all delay offsets in one clock cycle are equal or there are at least two delay offsets that are unequal, and one delay offset is the time length between any two adjacent groups of rising edges of the driving clocks.

5. The storage-computing architecture FPGA according to claim 4, characterized in that: The difference between the number of storage and computing units connected to each group of driving clocks does not exceed the numerical threshold, all delay offsets within a clock cycle are equal and each delay offset d= P / C, where P is the length of a clock cycle.

6. The storage-computing architecture FPGA according to claim 4, characterized in that: Each delay offset within a clock cycle is determined based on the instantaneous current estimation value of each storage and calculation unit connected and driven by each group of driving clocks during the startup and operation process.

7. The storage-computing architecture FPGA according to claim 6, characterized in that: The delay offset Tc between the rising edge of any c-th group of driving clocks and the rising edge of the c+1-th group of driving clocks adjacent thereto in one clock cycle is equal to the delay between the start time of all storage and calculation units connected and driven by the c-th group of driving clocks and the time when the total instantaneous current estimation value generated drops to the current lower limit threshold, and c∈[1,C] is a parameter.

8. The storage-computing architecture FPGA according to claim 6, characterized in that: The delay offset T between the rising edge of any f-th group of driving clocks and the rising edge of the f+1th group of driving clocks adjacent to it in a clock cycle is f , is a random number between the value of P / C and the value range of the minimum difference value of the f-th group of drive clocks. The minimum difference value of the f-th group of drive clocks is the delay between the start time of all storage and calculation units connected and driven by the f-th group of drive clocks and the time when the total instantaneous current estimate value generated drops to the current lower limit threshold.

9. The storage-computing architecture FPGA according to claim 4, characterized in that: Each delay offset within a clock cycle is a random number.

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