Processing system of single-precision configurable matrix operation unit based on RISC-V instruction expansion

Abstract

The invention relates to the technical field of integrated circuits, in particular to a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction expansion, which comprises an RISC-V processor used for executing a software program and identifying a user-defined expansion instruction, and the RISC-V processor is connected with the single-precision configurable matrix operation unit through a user-defined coprocessor interface; the single-precision configurable matrix operation unit comprises an instruction response and decoding module and an instruction retirement and write-back module, and the instruction response and decoding module is used for receiving an instruction function code, source operation data and a destination register number and decoding the instruction function code; after decoding is completed, different execution units are selected according to a decoding result to send corresponding control signals; and after the execution unit completes the corresponding task, the instruction retirement and write-back module returns an execution result and a completion signal to the RISC-V processor, so that execution of a self-defined extension instruction is completed. According to the system, the matrix operation speed can be accelerated through bottom hardware under limited hardware resource consumption.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a processing system for a single-precision configurable matrix operation unit based on RISC-V instruction extension. Background Art

[0002] RISC-V is an open reduced instruction set architecture (ISA) that solves the problems of insufficient openness, complex intellectual property rights, and technological lag in existing ISAs. It is not constrained by commercial organizations, avoids the potential risks of foreign architectures, and achieves independent control. The modular design of RISC-V allows for free combination of instruction subsets, and has the characteristics of simplicity and modularity.

[0003] In recent years, embedded IoT devices have developed rapidly, especially in the field of robotics, and the demand for microcontroller computing power has increased greatly. In order to accurately control the robotic arm in real time, it is necessary to perform real-time operations on matrices composed of a large amount of sensor data. However, traditional general-purpose embedded processors are limited by memory bandwidth and the number of internal arithmetic logic units when performing matrix operations, and perform poorly when performing matrix operation tasks. Therefore, it is urgent to design a hardware that can effectively improve the efficiency of traditional processors when performing matrix tasks.

[0004] Improving the speed of matrix operations is very important in the field of robotics or deep learning. There are generally two ways to improve the matrix operation speed of the processor. One is to develop a more efficient matrix algorithm from an algorithmic perspective to avoid the adverse effects of memory bottlenecks and computing resource bottlenecks. The disadvantage is that the performance improvement is limited. The other method is to use vector instructions, which essentially increases a large amount of cache and computing resources. The disadvantage is that the hardware overhead is large, resulting in increased production costs.

[0005] Traditional embedded microcontrollers often use bus-mounted accelerators when expanding accelerators. The advantage is that the design is simple and easy to verify, but the disadvantage is that the communication delay between the main processor and the accelerator is high, the accelerator algorithm is rigid, and the versatility is poor.

[0006] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the invention

[0007] The purpose of the present invention is to overcome the above-mentioned problems of the prior art and provide a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction extension, so as to solve the technical problems in the prior art of improving the matrix operation speed of the processor, such as limited performance improvement, high hardware overhead and high cost, high communication delay between the main processor and the accelerator, rigid accelerator algorithm and poor versatility.

[0008] The above objectives are achieved through the following technical solutions:

[0009] A processing system of a single-precision configurable matrix operation unit based on RISC-V instruction extension, comprising a RISC-V processor for executing software programs and identifying custom extended instructions, wherein the RISC-V processor is connected to the single-precision configurable matrix operation unit through a custom coprocessor interface; the single-precision configurable matrix operation unit comprises an instruction response and decoding module and an instruction retirement and write-back module, wherein the instruction response and decoding module is used to receive instruction function codes, source operation data and destination register numbers sent by the custom coprocessor interface, and decode the instruction function codes; after decoding is completed, different execution units are selected according to the decoding results to send corresponding control signals; after the execution unit completes the corresponding task, the instruction retirement and write-back module returns the execution result and the completion signal to the RISC-V processor through the custom coprocessor interface, thereby completing the execution of a custom extended instruction; the execution unit The accelerator comprises an accelerator control state register, a matrix register module, an accelerator memory access module, a floating-point operation resource and an operation controller. The accelerator control state register is used to store the shape of the matrix to be processed by the accelerator, including the size of the rows and columns of the matrix; the matrix register module is used to store the original data during the matrix operation and the intermediate results generated during the operation; the accelerator memory access module comprises a data loading channel and a data storage channel, which loads the specified matrix from the specified address of the system main memory according to the control signal, or writes the specified matrix data to the specified address of the system main memory; the floating-point operation resource is used to complete the operation of single-precision floating-point data; the operation controller is used to receive the custom extension instruction sent by the RISC-V processor, and then configure and schedule the data flow, control the floating-point operation resource to realize the addition, subtraction, multiplication, transposition and inversion operations of matrices of different dimensions, and is used to configure the size of the matrix register to be used and the operation unit array.

[0010] Furthermore, the matrix register module includes at least four independent matrix registers for storing four matrices, and each of the matrix registers shares two read ports and one write port.

[0011] Furthermore, each matrix register can store a matrix of 9 rows and 9 columns at most, and the data type of each element is 32-bit single-precision floating point; when the matrix stored in the matrix register is less than 9 rows and 9 columns, the valid data of the matrix is ​​distributed in the least significant row / column of the matrix register.

[0012] Furthermore, the protocol control modules in the data loading channel and the data storage channel initiate transmission to the system bus according to the address, and the data is written into the matrix register or written back into the system main memory after passing through the bit width conversion module.

[0013] Furthermore, the floating-point operation resources include 9 single-precision floating-point adders / subtractors, 9 single-precision floating-point multipliers, and 9 single-precision floating-point dividers; the floating-point operation resources are shared by the operation controller.

[0014] Furthermore, the operation controller includes a matrix inversion controller, a matrix transposition controller, a matrix addition / subtraction controller and a matrix multiplication controller. The matrix inversion controller, the matrix transposition controller, the matrix addition / subtraction controller and the matrix multiplication controller use a unified interface to access the matrix register module, including one or two register read interfaces and a register write interface; they share floating-point operation resources, and only one of them can occupy the floating-point operation resources at the same time.

[0015] Further, the matrix transposition controller is used to read out the matrix of the specified size in the specified source matrix register by column and then write it into the specified destination matrix register by row according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module to complete the matrix transposition;

[0016] The matrix addition / subtraction controller is used to complete the addition / subtraction operation of the matrices of the specified size in the two specified source matrix registers using nine single-precision floating-point adders / subtractors according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module, and then write them back to the specified destination matrix register to complete the matrix addition / subtraction operation;

[0017] The matrix multiplication controller is used to complete the matrix multiplication of the matrices of the specified size in the two specified source matrix registers using nine single-precision floating-point multipliers and adders / subtractors according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module, and then write them back to the specified destination matrix register to complete the matrix multiplication operation;

[0018] The matrix inversion controller is used to perform an inversion operation on a matrix of a specified size in a specified source matrix register and write it into a specified destination matrix register according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module.

[0019] Furthermore, the custom extension instructions include matrix configuration instructions, accelerator memory access instructions and matrix operation instructions;

[0020] The matrix configuration instruction is used to set the number of rows and columns of the matrix in the accelerator control state register;

[0021] The accelerator memory access instruction is used to access the accelerator;

[0022] The matrix operation instruction is used to start array operation.

[0023] Furthermore, the accelerator memory access instructions include matrix data loading instructions and matrix data storage instructions. The matrix data loading instructions are used to control the accelerator to load a complete matrix data from the address specified in the RS0 integer register, and the matrix shape is determined by the accelerator control status register; the matrix data loading instructions control the accelerator to store the matrix data in the matrix register specified by the MRS-IMM immediate number to the address specified in the RS0 integer register.

[0024] Furthermore, the matrix operation instructions include matrix inversion instructions, matrix transposition instructions, matrix addition instructions, matrix subtraction instructions and matrix multiplication instructions; the shapes of the matrices operated by the matrix operation instructions are all controlled by the accelerator control status register; the matrix inversion instructions control the matrix inversion controller to invert the matrix in matrix register No. 1, and the inversion result is stored in matrix register No. 2; when the source matrix is ​​reversible and the inversion is successfully completed, the minv instruction writes data "0" into the rd destination register, and if the source matrix is ​​not reversible, the data "1" is written into the rd destination register;

[0025] The matrix transposition instruction controls the matrix transposition controller to perform a transposition operation on the matrix in the matrix register specified by the mrs0-imm immediate number, and writes the result into the matrix register specified by the mrd-imm immediate number;

[0026] The matrix addition instruction and the matrix subtraction instruction control the matrix addition and subtraction controller to perform addition or subtraction operations on the data in the two matrix registers specified by mrs0-imm and mrs1-imm, and the operation results are stored in the matrix register specified by mrd-imm;

[0027] The matrix multiplication instruction controls the matrix multiplication controller to perform C multiplication operation on the data in the two matrix registers specified by mrs0-imm and mrs1-imm, and the operation result is stored in the matrix register specified by mrd-imm.

[0028] The processing system of the single-precision configurable matrix operation unit based on the RISC-V instruction expansion provided by the present invention integrates a matrix operation acceleration unit in a general-purpose processor to accelerate the processing efficiency of the general-purpose processor for matrix operation tasks, and can be used to accelerate various robotic arm control calculation tasks, such as robotic arm inverse dynamics solution, mass matrix inversion, etc. This scheme uses the RISC-V extended instruction set to control the matrix operation unit extended by the custom coprocessor interface, accelerates the execution of matrix operation tasks by the general-purpose processor, and has the characteristics of configurability and high generality. The newly added custom extended instructions and matrix operation extension architecture are portable and reusable in various processors of the RISC-V instruction set architecture, and can achieve efficient matrix operation acceleration under limited resource consumption and limited power consumption; software programming is performed through custom extended instructions, which is convenient for accelerating the calculation of matrices of different sizes and shapes, and has high versatility. This system can accelerate the matrix operation speed through the underlying hardware under limited hardware resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A block diagram of a processing system for a single-precision configurable matrix operation unit based on RISC-V instruction extension according to the present invention;

[0030] Figure 2 A schematic diagram of the structure of a single-precision configurable matrix operation unit in a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction extension according to the present invention;

[0031] Figure 3 It is a structural block diagram of a matrix register module in a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction expansion according to the present invention;

[0032] Figure 4 A structural block diagram of the interior of a matrix register in a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction expansion according to the present invention;

[0033] Figure 5 It is a structural block diagram of an accelerator memory access unit in a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction expansion according to the present invention;

[0034] Figure 6 The encoding format of the custom extended instruction in the processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension described in the present invention;

[0035] Figure 7 A coding table of eight custom extended instructions in the processing system of the single-precision configurable matrix operation unit based on RISC-V instruction expansion described in the present invention;

[0036] Figure 8 This is a workflow diagram of the matrix operation unit in the processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension described in the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below based on the accompanying drawings and embodiments. The described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] like Figure 1 and Figure 2 As shown, the present solution provides a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction extension, including a RISC-V processor for executing software programs and identifying custom extended instructions, wherein the RISC-V processor is connected to the single-precision configurable matrix operation unit through a custom coprocessor interface, and the single-precision configurable matrix operation unit is used to implement parallel operations of single-precision floating points; the RISC-V processor uses the custom coprocessor interface to send instructions and data to the single-precision configurable matrix operation unit, and returns the execution result to the RISC-V processor after the single-precision configurable matrix operation unit completes the instruction task;

[0039] The single-precision configurable matrix operation unit includes an instruction response and decoding module and an instruction retirement and write-back module. The instruction response and decoding module is used to receive the instruction function code, source operation data and destination register number sent by the custom coprocessor interface, and decode the instruction function code; after the decoding is completed, different execution units are selected according to the decoding result to send corresponding control signals; after the execution unit completes the corresponding task, the instruction retirement and write-back module returns the execution result and the completion signal to the RISC-V processor through the custom coprocessor interface, so as to complete the execution of a custom extended instruction;

[0040] The execution unit includes an accelerator control state register, a matrix register module, an accelerator memory access module, a floating point operation resource and an operation controller.

[0041] The accelerator control state register is used to store the shape of the matrix to be processed by the accelerator, including the size of the rows and columns of the matrix;

[0042] The matrix register module is used to store the original data during matrix operation and the intermediate results generated during the operation;

[0043] The accelerator memory access module includes a data loading channel and a data storage channel, which loads a specified matrix from a specified address of the system main memory or writes specified matrix data to a specified address of the system main memory according to a control signal; the data loading channel can load data from a specified address of the system main memory independently of the CPU, and the data storage channel can write data to a specified address of the system main memory independently of the CPU; the two channels are independent of each other, and data loading and storage can be performed simultaneously;

[0044] The floating-point computing resource is used to complete the operation on single-precision floating-point data;

[0045] The operation controller is used to receive the custom extension instructions sent by the RISC-V processor, and then configure and schedule the data flow, control the floating-point operation resources to implement addition, subtraction, multiplication, transposition and inversion operations for matrices of different dimensions, and configure the matrix register size and operation unit array to be used.

[0046] like Figure 3 and Figure 4 As shown, the matrix register module in this embodiment includes at least four independent matrix registers for storing four matrices, and each of the matrix registers shares two read ports and one write port, which can meet the data throughput required by the operation controller.

[0047] Each of the matrix registers can store a matrix of 9 rows and 9 columns at most, and the data type of each element is 32-bit single-precision floating point; when the matrix stored in the matrix register is less than 9 rows and 9 columns, the valid data of the matrix is ​​distributed in the least significant row / column of the matrix register.

[0048] This embodiment takes a matrix with 4 rows and 4 columns as an example, and its valid data is stored in the 1st to 4th rows and the 1st to 4th columns of the matrix register, and the data in other positions are invalid data.

[0049] like Figure 5 As shown, the protocol control modules in the data loading channel and the data storage channel initiate transmission to the system bus according to the address, and the data is written into the matrix register or written back into the system main memory after passing through the bit width conversion module.

[0050] Specifically, the accelerator memory access module can load a specified matrix from a specified address of the system main memory according to a control signal, or write a specified matrix data to a specified address of the system main memory. The amount of data transmitted each time is determined by the size of the matrix shape set in the accelerator control status register. Specifically, the amount of data transmitted each time is equal to the number of matrix rows (m) * the number of matrix columns (n) * 4 bytes. The protocol control module in the data loading or storage channel initiates transmission to the system bus according to the address, and the data is written to the matrix register after passing through the bit width conversion module, or written back to the system main memory.

[0051] The data loading channel and the data storage channel both contain a protocol control module and a data bit width conversion module. The protocol control module is responsible for interacting with the system bus to complete the sending or receiving of bus data. The bit width conversion module is responsible for converting the matrix register data bit width and the system bus bit width to ensure that the data can be transmitted normally.

[0052] In some embodiments the system bus is an AXI bus.

[0053] The floating-point operation resources are used to complete the operation of single-precision floating-point data, including a plurality of single-precision floating-point adders / subtractors, a plurality of single-precision floating-point multipliers, and a plurality of single-precision floating-point dividers. The floating-point operation resources are shared by various matrix operation controllers to save operation resource overhead.

[0054] In this embodiment, the floating-point operation resources include 9 single-precision floating-point adders / subtractors, 9 single-precision floating-point multipliers, and 9 single-precision floating-point dividers; the floating-point operation resources are shared by the operation controller to save operation resource overhead.

[0055] Specifically, in this embodiment, the floating-point computing resources are a computing array composed of multiple single-precision floating-point computing units, and the connection between each of them can be configured according to different computing types to form a chain, mesh or distributed structure.

[0056] like Figure 2 As shown, the operation controller in this embodiment receives the custom instruction information after pre-decoding from the RISC-V processor, and determines the function of the instruction and the dimension of the matrix according to the information, and allocates the operation function to the calculation unit array. The calculation unit array obtains the matrix data from the external matrix register according to the control signal sent by the controller and caches it inside the matrix operation unit. At the same time, a series of matrix operations are completed. After the calculation is completed, the calculation result is returned to the RISC-V processor, and the matrix register and operation unit array to be used can be configured according to the information of the matrix size given by the configuration instruction. Among them, pre-decoding is to use the instruction response and decoding module to receive the custom instruction request issued by the custom coprocessor interface and return the handshake signal. And the function code issued by the custom coprocessor interface is decoded. After the decoding is completed, the corresponding execution unit is selected to execute the instruction.

[0057] The operation controller includes a matrix inversion controller, a matrix transposition controller, a matrix addition / subtraction controller and a matrix multiplication controller. These controllers receive control signals sent by a decoding module, read source data from a matrix register, and write back to the matrix register after completing a specified matrix operation. The matrix inversion controller, the matrix transposition controller, the matrix addition / subtraction controller and the matrix multiplication controller use a unified interface to access the matrix register module, including one or two register read interfaces and a register write interface. They share floating-point operation resources, and only one of them can occupy the floating-point operation resources at the same time.

[0058] The matrix transposition controller is used to read out the matrix of the specified size in the specified source matrix register by column and then write it into the specified destination matrix register by row according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module to complete the matrix transposition;

[0059] The matrix addition / subtraction controller is used to complete the addition / subtraction operation of the matrices of the specified size in the two specified source matrix registers using nine single-precision floating-point adders / subtractors according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module, and then write them back to the specified destination matrix register to complete the matrix addition / subtraction operation;

[0060] The matrix multiplication controller is used to complete the matrix multiplication of the matrices of the specified size in the two specified source matrix registers using nine single-precision floating-point multipliers and adders / subtractors according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module, and then write them back to the specified destination matrix register to complete the matrix multiplication operation;

[0061] The matrix inversion controller is used to perform an inversion operation on a matrix of a specified size in a specified source matrix register and write it into a specified destination matrix register according to the matrix configuration in the accelerator control status register and the control information issued by the instruction response and decoding module; in this embodiment, the matrix inversion controller uses the Gauss-Jordan elimination method for inversion, and four matrix registers are required for matrix inversion, which respectively store the original matrix, the right half augmented matrix, and the intermediate results generated in the operation.

[0062] It should be noted that this embodiment designs 8 RISC-V custom extension instructions for matrix operations and control of matrix operation units. The encoding format of the 8 instructions is as follows: Figure 6As shown, opcode represents the instruction operation code, funct3 and funct7 encode the function of the instruction, rd(imm0), rs0(imm1) and rs1(imm2) are the source operand or destination operand of the instruction, which can refer to the integer register of RISC-V or the matrix register in the matrix operation unit.

[0063] The custom extension instructions include matrix configuration instructions, accelerator memory access instructions and matrix operation instructions, specifically:

[0064] The matrix configuration instruction (matrix set m, n, msetmnp) is used to set the number of rows and columns of the matrix in the accelerator control status register; the number of rows and columns configured comes from the rs0 and rs1 integer source registers specified in the instruction. If the accelerator supports the matrix shape configured by the instruction, the return data "0" will be placed in the rd integer destination register, if not supported, the data "1" will be returned to indicate that the configuration is invalid;

[0065] The accelerator memory access instruction is used to access the accelerator; it includes a matrix data loading instruction (matrix load, hereinafter referred to as mload) and a matrix data storage instruction (matrix store, hereinafter referred to as mstore), wherein the matrix data loading instruction is used to control the accelerator to load a complete matrix data from the address specified in the rs0 integer register, and the matrix shape is determined by the accelerator control status register. The data loaded by the mload instruction is stored in the matrix register specified by the mrs-imm immediate number. Similarly, the matrix data loading instruction controls the accelerator to store the matrix data in the matrix register specified by the mrs-imm immediate number to the address specified in the rs0 integer register; when the accelerator memory access instruction is successfully executed, data "0" will be written to the rd destination integer register. If the accelerator memory access encounters an abnormal situation, such as accessing an inaccessible address, data "1" will be written back to the rd destination integer register to indicate that the memory access failed.

[0066] The matrix operation instructions in this embodiment are used to start array operations. Specifically, the matrix operation instructions include matrix inverse instructions (minv), matrix transpose instructions (mtrans), matrix addition instructions (madd), matrix subtraction instructions (msub), and matrix multiplication instructions (mmul); the shapes of the matrices operated by the matrix operation instructions are all controlled by the accelerator control state register. The matrix inversion instruction (minv instruction) controls the matrix inversion controller to invert the matrix in the matrix register No. 1, and the inversion result is stored in the matrix register No. 2; when the source matrix is ​​reversible and the inversion is successfully completed, the minv instruction writes data "0" to the rd destination register, and if the source matrix is ​​not reversible, the minv instruction writes data "1" to the rd destination register;

[0067] The matrix transposition instruction (Mtrans instruction) controls the matrix transposition controller to perform a transposition operation on the matrix in the matrix register specified by the mrs0-imm immediate number, and writes the result into the matrix register specified by the mrd-imm immediate number;

[0068] The matrix addition instruction (Madd instruction) and the matrix subtraction instruction (msub instruction) control the matrix addition and subtraction controller to perform addition or subtraction operations on the data in the two matrix registers specified by mrs0-imm and mrs1-imm, and the operation results are stored in the matrix register specified by mrd-imm;

[0069] The matrix multiplication instruction (Mmul instruction) controls the matrix multiplication controller to perform a c multiplication operation on the data in the two matrix registers specified by mrs0-imm and mrs1-imm, and the operation result is stored in the matrix register specified by mrd-imm.

[0070] like Figure 8 As shown, this scheme also proposes a workflow for accelerating matrix operations for the processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension, and the main steps are as follows:

[0071] Step (1), the RISC-V processor needs to perform matrix calculation tasks and sends custom instructions to the matrix operation unit through the custom coprocessor interface to control it to start the calculation.

[0072] Step (2), sending the msetmnp instruction (matrix configuration instruction) to configure the accelerator control status register and configure the matrix shape to be processed by the matrix operation unit.

[0073] Step (3), sending the mload instruction (matrix load instruction) to control the matrix operation unit to load the source matrix data and store it in the matrix register module.

[0074] Step (4), sending matrix operation instructions to control the matrix operation unit to perform a specific type of matrix operation and store the operation results in the matrix register module.

[0075] Step (5), sending an mstore instruction (matrix storage instruction) to control the matrix operation unit to write the operation results in the matrix register module back to the system main memory.

[0076] Step (6), RISC-V matrix acceleration operation is completed.

[0077] The above description is only for illustrating the implementation mode of the present invention and is not intended to limit the present invention. For those skilled in the art, any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A processing system based on a single-precision configurable matrix operation unit extended by RISC-V instructions, characterized in that: A RISC-V processor is included for executing software programs and identifying custom extended instructions, wherein the RISC-V processor is connected to a single-precision configurable matrix operation unit through a custom coprocessor interface, and the single-precision configurable matrix operation unit is used to implement parallel operations of single-precision floating points; the RISC-V processor uses the custom coprocessor interface to send instructions and data to the single-precision configurable matrix operation unit, and returns the execution result to the RISC-V processor after the single-precision configurable matrix operation unit completes the instruction task; The single-precision configurable matrix operation unit includes an instruction response and decoding module and an instruction retirement and write-back module. The instruction response and decoding module is used to receive the instruction function code, source operation data and destination register number sent by the custom coprocessor interface, and decode the instruction function code; after the decoding is completed, different execution units are selected according to the decoding result to send corresponding control signals; after the execution unit completes the corresponding task, the instruction retirement and write-back module returns the execution result and the completion signal to the RISC-V processor through the custom coprocessor interface, so as to complete the execution of a custom extended instruction; The execution unit includes an accelerator control state register, a matrix register module, an accelerator memory access module, a floating point operation resource and an operation controller. The accelerator control state register is used to store the shape of the matrix to be processed by the accelerator, including the size of the rows and columns of the matrix; The matrix register module is used to store the original data during matrix operation and the intermediate results generated during the operation; The accelerator memory access module includes a data loading channel and a data storage channel, and loads a specified matrix from a specified address of the system main memory or writes specified matrix data to a specified address of the system main memory according to a control signal; The floating-point computing resource is used to complete the operation on single-precision floating-point data; The operation controller is used to receive the custom extension instructions sent by the RISC-V processor, and then configure and schedule the data flow, control the floating-point operation resources to implement addition, subtraction, multiplication, transposition and inversion operations for matrices of different dimensions, and configure the matrix register size and operation unit array to be used.

2. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 2 is characterized in that: The matrix register module includes at least four independent matrix registers for storing four matrices, and each of the matrix registers shares two read ports and one write port, which can meet the data throughput required by the operation controller.

3. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 3 is characterized in that: Each of the matrix registers can store a matrix of 9 rows and 9 columns at most, and the data type of each element is 32-bit single-precision floating point; when the matrix stored in the matrix register is less than 9 rows and 9 columns, the valid data of the matrix is ​​distributed in the least significant row / column of the matrix register.

4. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 2 is characterized in that: The protocol control modules in the data loading channel and the data storage channel initiate transmission to the system bus according to the address, and the data is written into the matrix register or written back into the system main memory after passing through the bit width conversion module.

5. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 1, characterized in that: The floating-point operation resources include 9 single-precision floating-point adders / subtractors, 9 single-precision floating-point multipliers, and 9 single-precision floating-point dividers; the floating-point operation resources are shared by the operation controller to save operation resource overhead.

6. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 1, characterized in that: The operation controller includes a matrix inversion controller, a matrix transposition controller, a matrix addition / subtraction controller and a matrix multiplication controller. The matrix inversion controller, the matrix transposition controller, the matrix addition / subtraction controller and the matrix multiplication controller use a unified interface to access the matrix register module, including one or two register read interfaces and a register write interface; they share floating-point operation resources, and only one of them can occupy the floating-point operation resources at the same time.

7. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 6, characterized in that: The matrix transposition controller is used to read out the matrix of the specified size in the specified source matrix register by column and then write it into the specified destination matrix register by row according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module to complete the matrix transposition; The matrix addition / subtraction controller is used to complete the addition / subtraction operation of the matrices of the specified size in the two specified source matrix registers using nine single-precision floating-point adders / subtractors according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module, and then write them back to the specified destination matrix register to complete the matrix addition / subtraction operation; The matrix multiplication controller is used to complete the matrix multiplication of the matrices of the specified size in the two specified source matrix registers using nine single-precision floating-point multipliers and adders / subtractors according to the matrix configuration in the accelerator control state register and the control information sent by the instruction response and decoding module, and then write them back to the specified destination matrix register to complete the matrix multiplication operation; The matrix inversion controller is used to perform an inversion operation on a matrix of a specified size in a specified source matrix register and write it into a specified destination matrix register according to the matrix configuration in the accelerator control status register and the control information issued by the instruction response and decoding module; in this embodiment, the matrix inversion controller uses the Gauss-Jordan elimination method for inversion, and four matrix registers are required for matrix inversion, which respectively store the original matrix, the right half augmented matrix, and the intermediate results generated in the operation.

8. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 1, characterized in that: The custom extended instructions include matrix configuration instructions, accelerator memory access instructions and matrix operation instructions; The matrix configuration instruction is used to set the number of rows and columns of the matrix in the accelerator control status register; the number of rows and columns configured comes from the rs0 and rs1 integer source registers specified in the instruction. If the accelerator supports the matrix shape configured by the instruction, it will return data "0" to the rd integer destination register, if not supported, it will return data "1" to indicate that the configuration is invalid; The accelerator memory access instruction is used to access the accelerator; The matrix operation instruction is used to start array operation.

9. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 8, characterized in that: The accelerator memory access instruction includes a matrix data loading instruction and a matrix data storage instruction. The matrix data loading instruction is used to control the accelerator to load a complete matrix data from the address specified in the rs0 integer register, and the matrix shape is determined by the accelerator control status register. The data loaded by the mload instruction is stored in the matrix register specified by the mrs-imm immediate number. Similarly, the matrix data loading instruction controls the accelerator to store the matrix data in the matrix register specified by the mrs-imm immediate number to the address specified in the rs0 integer register; when the accelerator memory access instruction is successfully executed, data "0" will be written to the rd destination integer register. If the accelerator memory access encounters an abnormal situation, such as accessing an inaccessible address, data "1" will be written back to the rd destination integer register to indicate that the memory access failed.

10. The processing system of the single-precision configurable matrix operation unit based on RISC-V instruction extension according to claim 8, characterized in that: The matrix operation instructions include matrix inversion instructions, matrix transposition instructions, matrix addition instructions, matrix subtraction instructions and matrix multiplication instructions; the shapes of the matrices operated by the matrix operation instructions are all controlled by the accelerator control state register; the matrix inversion instructions control the matrix inversion controller to invert the matrix in the No. 1 matrix register, and the inversion result is stored in the No. 2 matrix register; when the source matrix is ​​reversible and the inversion is successfully completed, the minv instruction writes data "0" into the rd destination register, and if the source matrix is ​​not reversible, the data "1" is written into the rd destination register; The matrix transposition instruction controls the matrix transposition controller to perform a transposition operation on the matrix in the matrix register specified by the mrs0-imm immediate number, and writes the result into the matrix register specified by the mrd-imm immediate number; The matrix addition instruction and the matrix subtraction instruction control the matrix addition and subtraction controller to perform addition or subtraction operations on the data in the two matrix registers specified by mrs0-imm and mrs1-imm, and the operation results are stored in the matrix register specified by mrd-imm; The matrix multiplication instruction controls the matrix multiplication controller to perform C multiplication operation on the data in the two matrix registers specified by mrs0-imm and mrs1-imm, and the operation result is stored in the matrix register specified by mrd-imm.

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