Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method includes: providing a silicon substrate having a gate structure disposed thereon and including source / drain doped regions; forming a dielectric stack covering the source / drain doped regions on the silicon substrate, the dielectric stack including a first nitride layer, an oxide layer and a second nitride layer stacked in sequence; etching the dielectric stack to form an initial contact hole exposing the source / drain doped regions, the initial contact hole having a lateral dimension in the first nitride layer and the oxide layer smaller than a lateral dimension in the second nitride layer; etching the oxide layer and the first nitride layer to form a contact hole having a lateral dimension in the first nitride layer and the oxide layer larger than a lateral dimension in the second nitride layer; forming a metal silicide layer at a bottom of the contact hole; forming a nitride liner layer at sidewalls of the contact hole; and forming a contact plug in the contact hole and connected to the metal silicide layer. The present disclosure is easy to form the metal silicide layer and prevents metal diffusion of the contact plug.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] As semiconductor technology matures, memory integration density is increasing. For example, in DRAM (Dynamic Random Access Memory), linewidth is decreasing, and the aspect ratio of the contact plugs is becoming very large. This makes it more difficult to form metal silicides in the substrate at the bottom of the contact plugs, increasing contact resistance. Furthermore, metal diffusion caused by contact plug formation can affect the stability of the semiconductor structure and reduce yield.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure that can reduce the aspect ratio of the contact plug, facilitate the formation of a metal silicide layer, reduce contact resistance, prevent metal diffusion of the contact plug, improve the stability of the semiconductor structure, and increase yield.

[0005] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a silicon substrate, wherein a gate structure is disposed on the silicon substrate, and the silicon substrate includes source and drain doped regions located on opposite sides of the gate structure; forming a dielectric stack covering the source and drain doped regions on the silicon substrate, the dielectric stack comprising a first nitride layer, an oxide layer, and a second nitride layer sequentially stacked on the source and drain doped regions, wherein the thickness of the first nitride layer is less than the thickness of the second nitride layer; etching the dielectric stack to form initial contact holes exposing the source and drain doped regions, the initial contact holes being located on the first nitride layer... The lateral dimensions of the nitride layer and the oxide layer are smaller than the lateral dimensions of the initial contact hole in the second nitride layer; the sidewalls of the oxide layer and the first nitride layer exposed by the initial contact hole are etched to form a contact hole, the lateral dimensions of the contact hole in the first nitride layer and the oxide layer being larger than the lateral dimensions of the contact hole in the second nitride layer; a metal silicide layer is formed at the bottom of the contact hole; a nitride liner layer is formed on the sidewalls of the contact hole; a contact plug is formed in the contact hole, the contact plug being electrically connected to the source / drain doped region through the metal silicide layer.

[0006] In some embodiments of this disclosure, before forming the nitride liner layer on the sidewall of the contact hole, the method further includes: nitriding the sidewall of the oxide layer exposed by the contact hole using a far-field plasma nitriding process to form a nitride oxide layer; wherein the nitride liner layer covers the nitride oxide layer.

[0007] In some embodiments of this disclosure, the gate structure includes a gate stack structure, a nitride isolation layer covering the sidewalls of the gate stack structure, and an oxide isolation layer covering the sidewalls of the nitride isolation layer; the first nitride layer further covers the oxide isolation layer; during the formation of the initial contact hole, the oxide isolation layer is partially etched; during the formation of the contact hole, the oxide isolation layer is partially etched.

[0008] In some embodiments of this disclosure, before forming the nitride liner layer on the sidewall of the contact hole, the method further includes: nitriding the sidewall of the oxide layer exposed by the contact hole and the sidewall of the oxide isolation layer using a far-field plasma nitriding process to form a nitride oxide layer; wherein the nitride liner layer covers the nitride oxide layer.

[0009] In some embodiments of this disclosure, the contact hole includes a recess located in the silicon substrate, and the metal silicide layer is located within the recess.

[0010] In some embodiments of this disclosure, forming the contact plug in the contact hole includes: forming a diffusion barrier layer that conformally covers the nitride liner layer and the metal silicide layer; and forming a metal layer that covers the diffusion barrier layer and fills the contact hole.

[0011] This disclosure also provides a semiconductor structure, including: a silicon substrate; a gate structure located on the silicon substrate, the silicon substrate including source and drain doped regions located on opposite sides of the gate structure; a dielectric stack including a first nitride layer, an oxide layer, and a second nitride layer sequentially stacked on the source and drain doped regions, wherein the thickness of the first nitride layer is less than the thickness of the second nitride layer, and a contact hole exposing the source and drain doped regions is provided in the dielectric stack; a metal silicide layer disposed at the bottom of the contact hole; a nitride pad layer disposed on the sidewall of the contact hole; and a contact plug disposed in the contact hole where the nitride pad layer serves as the sidewall, the contact plug being electrically connected to the source and drain doped regions through the metal silicide layer; wherein the lateral dimension of the contact plug in the first nitride layer and the oxide layer is greater than the lateral dimension of the contact plug in the second nitride layer.

[0012] In some embodiments of this disclosure, the semiconductor structure further includes an oxide nitride layer located between the nitride pad layer and the oxide layer, and covering the sidewalls of the oxide layer exposed by the contact holes.

[0013] In some embodiments of this disclosure, the gate structure includes a gate stack structure, a nitride isolation layer covering the sidewalls of the gate stack structure, and an oxide isolation layer covering the sidewalls of the nitride isolation layer; the oxide nitride layer is disposed between the oxide isolation layer and the nitride pad layer.

[0014] In some embodiments of this disclosure, the contact plug includes: a diffusion barrier layer conformally covering the nitride liner layer and the metal silicide layer; and a metal layer covering the diffusion barrier layer and filling the contact hole.

[0015] As can be seen from the above technical solutions, the semiconductor structure fabrication method of this disclosure has at least one of the following advantages and positive effects:

[0016] In this embodiment, the sidewalls of the oxide layer and the first nitride layer exposed by the initial contact hole are etched to form the contact hole. The lateral dimension of the contact hole in the first nitride layer and the oxide layer is larger than the lateral dimension of the contact hole in the second nitride layer, thereby reducing the aspect ratio of the contact hole. This makes it easier to form a metal silicide layer at the bottom of the contact hole and reduces the contact resistance of the contact plug. Since a nitride pad layer is formed on the sidewall of the contact hole, metal diffusion of the contact plug can be prevented, improving the stability of the semiconductor structure and increasing the yield. Attached Figure Description

[0017] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0018] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure;

[0019] Figure 2 This is a schematic diagram illustrating the formation of a dielectric stack on a silicon substrate according to some embodiments of the present disclosure;

[0020] Figure 3 This is a schematic diagram illustrating the formation of initial contact holes in a dielectric stack according to some embodiments of this disclosure;

[0021] Figure 4 This is a schematic diagram illustrating the formation of a contact hole on the sidewalls of the oxide layer and the first nitride layer exposed by etching the initial contact hole, as shown in some embodiments of this disclosure.

[0022] Figure 5The present disclosure provides a schematic diagram illustrating contact holes including recesses located in a silicon substrate, as shown in some embodiments.

[0023] Figure 6 This is a schematic diagram illustrating the formation of a metal silicide layer in a recess, as shown in some embodiments of this disclosure;

[0024] Figure 7 This is a schematic diagram illustrating how a far-field plasma nitriding process is used to nitrid the sidewalls of the oxide layer exposed by the contact hole and the sidewalls of the oxide isolation layer to form a nitride layer, as shown in some embodiments of this disclosure.

[0025] Figure 8 This is a schematic diagram illustrating the formation of nitride liner layers within contact holes and on dielectric stacks, as shown in some embodiments of this disclosure.

[0026] Figure 9 This is a schematic diagram illustrating the formation of a nitride liner layer on the sidewall of a contact hole, as shown in some embodiments of this disclosure.

[0027] Figure 10 This is a schematic diagram illustrating the formation of a contact plug in a contact hole according to some embodiments of this disclosure.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1. Silicon substrate; 101. Source / drain doped region; 102. Shallow trench isolation; 103. Active region; 2. Gate structure; 201. Gate dielectric layer; 202. Gate layer; 203. Insulating cap layer; 204. Nitride isolation layer; 205. Oxide isolation layer; 3. Dielectric stack; 301. First nitride layer; 302. Oxide layer; 303. Second nitride layer; 304. Oxide oxynitride layer; 4. Nitride pad layer; 5. Metal silicide layer; 6. Contact plug; 601. Diffusion barrier layer; 602. Metal layer; H1. Initial contact hole; H2. Contact hole; R. Recess; X. Horizontal direction; Y. Vertical direction. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0031] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0032] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0033] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0034] like Figure 1 As shown, this disclosure provides a method for fabricating a memory, including the following steps S110 to S170.

[0035] S110: A silicon substrate 1 is provided, on which a gate structure 2 is disposed. The silicon substrate 1 includes source and drain doped regions 101 located on opposite sides of the gate structure 2.

[0036] S120: A dielectric stack 3 covering the source / drain doped regions 101 is formed on the silicon substrate 1. The dielectric stack 3 includes a first nitride layer 301, an oxide layer 302, and a second nitride layer 303 sequentially stacked on the source / drain doped regions 101. The thickness of the first nitride layer 301 is less than the thickness of the second nitride layer 303.

[0037] S130: Etch the dielectric stack 3 to form an initial contact hole H1 that exposes the source / drain doped region 101. The lateral dimension of the initial contact hole H1 in the first nitride layer 301 and oxide layer 302 is smaller than the lateral dimension of the initial contact hole H1 in the second nitride layer 303.

[0038] S140: Etch the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 to form contact hole H2, wherein the lateral dimension of contact hole H2 in the first nitride layer 301 and oxide layer 302 is larger than the lateral dimension of contact hole H2 in the second nitride layer 303.

[0039] S150: A metal silicide layer 5 is formed at the bottom of the contact hole H2.

[0040] S160: A nitride liner layer 4 is formed on the sidewall of the contact hole H2.

[0041] S170: A contact plug 6 is formed in the contact hole H2. The contact plug 6 is electrically connected to the source / drain doped region 101 through the metal silicide layer 5.

[0042] The above-described fabrication method in this embodiment forms a contact hole H2 by etching the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1. The lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, reducing the aspect ratio of the contact hole H2. This makes it easier to form a metal silicide layer 5 at the bottom of the contact hole H2, and the area of ​​the metal silicide layer 5 is larger, reducing the contact resistance of the contact plug 6. Since a nitride pad layer 4 is formed on the sidewall of the contact hole H2, metal diffusion of the contact plug 6 can be prevented, improving the stability of the semiconductor structure and increasing the yield.

[0043] The method for fabricating the semiconductor structure according to the embodiments of this disclosure will be described in detail below.

[0044] S110: A silicon substrate 1 is provided, on which a gate structure 2 is disposed. The silicon substrate 1 includes source and drain doped regions 101 located on opposite sides of the gate structure 2.

[0045] like Figure 2 As shown, the silicon substrate 1 in this embodiment is made of single-crystal silicon to facilitate the formation of the metal silicide layer 5.

[0046] In some embodiments, such as Figure 2 As shown, shallow trench isolation 102 is formed on silicon substrate 1, and active regions 103 are provided between the shallow trench isolation 102. Gate structure 2 is located in active regions 103. Active regions 103 also have bit line structures and word line structures (not shown in the figure), and the word line structures and bit line structures are located at different heights. Both word line structures and bit line structures are electrically connected to active regions 103.

[0047] like Figure 2As shown, source and drain doped regions 101 are also provided in the active region 103 of the substrate 1, located on both sides of the gate structure 2. One of the source and drain doped regions 101 can serve as the source and the other as the drain.

[0048] In some embodiments, such as Figure 2 As shown, the gate structure 2 includes a gate stack structure, a nitride isolation layer 204 covering the sidewalls of the gate stack structure, and an oxide isolation layer 205 covering the sidewalls of the nitride isolation layer 204.

[0049] like Figure 2 As shown, the gate structure 2 includes a gate stack structure. The gate stack structure includes a gate dielectric layer 201, a gate layer 202, and an insulating capping layer 203 sequentially stacked from the surface of the silicon substrate 1. The gate layer 202 can be a stack, including a polysilicon layer and a metal material layer sequentially stacked from the gate dielectric layer 201, or the gate layer 202 can be a single polysilicon layer or a single metal material layer; no particular limitation is made here. In some embodiments, the metal material layer may include at least one of tungsten, copper, and aluminum. In some embodiments, the material of the gate dielectric layer 201 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the insulating capping layer 203 may be silicon nitride.

[0050] like Figure 2 As shown, a nitride isolation layer 204 covers the sidewalls of the gate stack structure, thereby insulating the gate stack structure from other functional layers or structures. In some embodiments, the material of the nitride isolation layer 204 may include at least one of silicon nitride and silicon oxynitride. An oxide isolation layer 205 covers the sidewalls of the nitride isolation layer 204, further isolating the gate stack structure from other functional layers or structures and protecting the gate stack structure. In some embodiments, the material of the oxide isolation layer 205 may include silicon oxide.

[0051] The gate structure 2 described above can be formed using deposition and etching processes, which will not be elaborated here. Before forming the gate structure 2, metal elements can be doped into the silicon substrate 1 located on both sides of the gate structure 2 using an ion implantation process to form source / drain doped regions 101.

[0052] The deposition process in this embodiment of the disclosure may be at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0053] S120: A dielectric stack 3 covering the source / drain doped regions 101 is formed on the silicon substrate 1. The dielectric stack 3 includes a first nitride layer 301, an oxide layer 302, and a second nitride layer 303 sequentially stacked on the source / drain doped regions 101. The thickness of the first nitride layer 301 is less than the thickness of the second nitride layer 303.

[0054] Continue to refer to Figure 2 A first nitride layer 301 can be formed on a silicon substrate 1 using a deposition process. The first nitride layer 301 covers the source / drain doped regions 101 and the gate structure 2 of the silicon substrate 1. The first nitride layer 301 also covers the oxide isolation layer 205 of the gate structure 2. In some embodiments, the material of the first nitride layer 301 may include at least one of silicon nitride and silicon oxynitride.

[0055] After the first nitride layer 301 is formed, an oxide layer 302 is formed on the first nitride layer 301 using a deposition process. The material of the oxide layer 302 may include silicon oxide. In the vertical direction Y, the thickness of the oxide layer 302 is greater than the thickness of the first nitride layer 301. The oxide layer 302 can not only further play an insulating role, but also play a supporting role, and can serve as the main carrier for forming the initial contact hole H1 in subsequent processes.

[0056] After forming the oxide layer 302, a second nitride layer 303 is formed on the oxide layer 302 using a deposition process. In some embodiments, the material of the second nitride layer 303 may include at least one of silicon nitride and silicon oxynitride. The thickness of the second nitride layer 303 is greater than the thickness of the first nitride layer 301, and the thickness of the second nitride layer 303 is less than the thickness of the oxide layer 302, so that when the contact hole H2 is subsequently formed using an etching process, the lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 can be greater than the lateral dimension of the contact hole H2 in the second nitride layer 303. As the top layer of the dielectric stack 3, the second nitride layer 303 can avoid reaction with other external elements, thereby improving the stability of the dielectric stack 3. The thicknesses of the first nitride layer 301, oxide layer 302, and second nitride layer 303 refer to the dimensions of the first nitride layer 301, oxide layer 302, and second nitride layer 303 in the vertical Y direction directly above the source / drain doped region 101.

[0057] S130: Etch the dielectric stack 3 to form an initial contact hole H1 that exposes the source / drain doped region 101. The lateral dimension of the initial contact hole H1 in the first nitride layer 301 and oxide layer 302 is smaller than the lateral dimension of the initial contact hole H1 in the second nitride layer 303.

[0058] like Figure 3 As shown, the dielectric stack 3 can be etched using an etching process to form the initial contact hole H1 exposing the source / drain doped regions 101. In some embodiments, such as... Figure 3 As shown, the bottom of the initial contact hole H1 may stop at the source / drain doped region 101 of the silicon substrate 1. In other embodiments, the bottom of the initial contact hole H1 may also extend into the source / drain doped region 101.

[0059] In some embodiments, the etching process can be a dry etching process. The dry etching process can be a plasma etching process, where the etching gas used can be chlorine gas. By controlling the amount of etching gas used, the degree of etching can be controlled.

[0060] like Figure 3 As shown, the lateral dimension of the initial contact hole H1 in the first nitride layer 301 and oxide layer 302 is smaller than the lateral dimension of the initial contact hole H1 in the second nitride layer 303. In other words, the lateral dimension of the initial contact hole H1 gradually decreases from top to bottom, which makes processing more convenient. The lateral dimension of the initial contact hole H1 can be understood as the dimension of the initial contact hole H1 along the horizontal direction X.

[0061] It should be noted that, in the embodiments of this disclosure, "vertical direction Y" can be understood as a direction perpendicular to the surface of the silicon substrate 1. For example, in the gate stack structure, the gate dielectric layer 201, the gate layer 202, and the insulating cap layer 203 are stacked in the vertical direction Y, and the gate dielectric layer 201 is located on the silicon substrate 1, and the gate dielectric layer 201 is located below the gate layer 202. "Horizontal direction X" can be understood as a direction parallel to the surface of the silicon substrate 1. For example, the initial contact hole H1 is distributed on both sides of the gate structure 2 in the horizontal direction X. The horizontal direction X and the vertical direction Y are perpendicular to each other. The above technical terms are only for ease of description and do not have a limiting meaning.

[0062] In some embodiments, during the formation of the initial contact hole H1, the oxide isolation layer 205 of the gate structure 2 is partially etched. That is, during the formation of the initial contact hole H1, after etching away a portion of the first nitride layer 301, a portion of the oxide isolation layer 205 is also etched away, so that a portion of the oxide isolation layer 205 serves as the inner wall of the initial contact hole H1. Of course, in other embodiments, during the formation of the initial contact hole H1, such as... Figure 3 As shown, the oxide isolation layer 205 of the gate structure 2 may not be etched, but a portion of the first nitride layer 301 may be etched. Those skilled in the art can adjust the etching range according to the actual situation, for example, according to the size of the lateral dimension of the initial contact hole H1. No special limitation is made here.

[0063] S140: Etch the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 to form contact hole H2, wherein the lateral dimension of contact hole H2 in the first nitride layer 301 and oxide layer 302 is larger than the lateral dimension of contact hole H2 in the second nitride layer 303.

[0064] like Figure 4As shown, the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 are etched using an etching process to enlarge the lateral dimension of the initial contact hole H1 at this location. This reduces the aspect ratio of the contact hole H2 and makes the lateral dimension of the contact hole H2 at this location larger than its lateral dimension in the second nitride layer 303. In other words, the inner wall of the contact hole H2 located in the second nitride layer 303 is not etched, preventing the lateral dimension of the contact hole H2 in the second nitride layer 303 from becoming too large and causing the subsequently formed contact plug 6 to electrically connect with other structures, affecting the electrical performance of the semiconductor structure. At the same time, since the lateral dimension of the contact hole H2 located in the second nitride layer 303 is already relatively large, it is also easier to form the contact plug 6 in the contact hole H2.

[0065] In some embodiments, such as Figure 5 As shown, the contact hole H2 includes a recess R located in the silicon substrate 1, and the metal silicide layer 5 is located within the recess R.

[0066] like Figure 4 As shown, after etching the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 to form the contact hole H2, the source / drain doped regions 101 located on the silicon substrate 1 can be etched further to form the recess R, as shown. Figure 6 As shown, this allows the metal silicide layer 5 formed in subsequent processes to be located in the recess R. The metal silicide layer 5 is electrically connected to the source / drain doped region 101, thereby enabling the contact plug 6 formed in subsequent processes to be electrically connected to the source / drain doped region 101 through the metal silicide layer 5, reducing the contact resistance of the contact plug 6.

[0067] S150: A metal silicide layer 5 is formed at the bottom of the contact hole H2.

[0068] As described in the steps above, the bottom of the contact hole H2 includes a recess R located in the silicon substrate 1, such as Figure 6 As shown, a metal silicide layer 5 can be formed in the recess R using a metal silicide process. In some embodiments, the metal element of the metal silicide layer 5 may include at least one of Co, Ni, Pt, Ti, Ta, Mo, and W, which can bond with silicon in the silicon substrate 1 to form a stable metal silicide, reducing the contact resistance with the contact plug 6.

[0069] S160: A nitride liner layer 4 is formed on the sidewall of the contact hole H2.

[0070] like Figure 8 As shown, after forming the metal silicide layer 5, a nitride pad layer 4 can be formed on the inner wall of the contact hole H2 and on the surface of the second nitride layer 303 using a deposition process. The material of the nitride pad layer 4 can be silicon nitride. Figure 9As shown, the nitride pad layer 4 is etched back to remove the nitride pad layer 4 located on the bottom wall of the contact hole H2 and on the second nitride layer 303, while retaining the nitride pad layer 4 located on the sidewall of the contact hole H2. Figure 9 As shown, contact holes H2 are located on both sides of gate structure 2. In subsequent processes, after contact plugs 6 are formed in contact holes H2, nitride pad layer 4 can act as a barrier layer to prevent metal diffusion in contact plugs 6 from affecting the electrical performance of gate structure 2 and improve the stability of semiconductor structure.

[0071] In some embodiments, before forming the nitride liner layer 4 on the sidewall of the contact hole H2, the method further includes: nitriding the sidewall of the oxide layer 302 exposed by the contact hole H2 using a far-field plasma nitriding process to form a nitride layer 304.

[0072] like Figure 7 As shown, after forming the metal silicide layer 5, the sidewalls of the oxide layer 302 exposed by the contact hole H2 can be nitrided using a far-field plasma nitriding process. This alters the properties of the oxide layer 302, causing its sidewalls to form an oxide nitride layer 304. The properties of the oxide nitride layer 304 are closer to those of the nitride liner layer 4 formed in subsequent processes, allowing the nitride liner layer 4 to form more stably on the oxide nitride layer 304. Simultaneously, this further prevents the diffusion of metal from the contact plug 6 formed later.

[0073] In some embodiments, such as Figure 4 As shown, during the formation of contact hole H2, the oxide isolation layer 205 of gate structure 2 is partially etched. That is, the sidewall of contact hole H2 includes exposed oxide isolation layer 205. Before forming nitride pad layer 4 on the sidewall of contact hole H2, the method further includes: nitriding the sidewall of exposed oxide layer 302 and sidewall of oxide isolation layer 205 of contact hole H2 using a far-field plasma nitriding process to form oxide nitride layer 304. That is, the entire inner wall of contact hole H2 is formed with oxide nitride layer 304, and the nitride pad layer 4 formed in subsequent processes can cover oxide nitride layer 304. Thus, the nitride pad layer 4 formed in subsequent processes can be formed more stably in contact hole H2.

[0074] In some embodiments, during the formation of the contact hole H2, the sidewalls of the contact hole H2 expose a first nitride layer 301 and an oxide layer 302. Before the nitride liner layer 4 is formed on the sidewalls of the contact hole H2, the method further includes: nitriding the sidewalls of the exposed oxide layer 302 of the contact hole H2 using a far-field plasma nitriding process to form a nitride oxide layer 304. That is, one sidewall of the contact hole H2 is covered with the nitride oxide layer 304, and the other sidewall is the first nitride layer 301. Since the properties of the first nitride layer 301 are similar to those of the nitride liner layer 4, it can also be stably bonded to the nitride liner layer 4.

[0075] S170: A contact plug 6 is formed in the contact hole H2. The contact plug 6 is electrically connected to the source / drain doped region 101 through the metal silicide layer 5.

[0076] like Figure 10 As shown, before forming the contact plug 6 in the contact hole H2, the method further includes: forming a diffusion barrier layer 601 that conformally covers the nitride liner layer 4 and the metal silicide layer 5; and forming a metal layer 602 that covers the diffusion barrier layer 601 and fills the contact hole H2.

[0077] like Figure 10 As shown, a diffusion barrier layer 601 can be formed in the contact hole H2 using a deposition process. The diffusion barrier layer 601 is used to prevent the diffusion of the metal of the contact plug 6, ensuring the stability of the electrical performance of the semiconductor structure. The diffusion barrier layer 601 can be a single layer or a stack of different materials. In some embodiments, the material of the diffusion barrier layer 601 can be at least one of titanium nitride and tungsten nitride.

[0078] After forming the diffusion barrier layer 601, a metal layer 602 covering the diffusion barrier layer 601 and filling the contact hole H2 is formed again using a deposition process. The material of the metal layer 602 may include at least one of W, Cu, and Al, to be electrically connected to the source / drain doped region 101.

[0079] In summary, the semiconductor structure fabrication method of this disclosure involves etching the sidewalls of the oxide layer 302 and the first nitride layer 301 exposed by the initial contact hole H1 to form a contact hole H2. The lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, thereby reducing the aspect ratio of the contact hole H2. This makes it easier to form a metal silicide layer 5 at the bottom of the contact hole H2, and the area of ​​the metal silicide layer 5 is larger, reducing the contact resistance of the contact plug 6. Since a nitride pad layer 4 is formed on the sidewall of the contact hole H2, metal diffusion of the contact plug 6 can be prevented, improving the stability of the semiconductor structure and increasing the yield.

[0080] This disclosure also provides a semiconductor structure, such as... Figure 10 As shown, the semiconductor structure includes a silicon substrate 1, a gate structure 2, a dielectric stack 3, a metal silicide layer 5, a nitride pad layer 4, and a contact plug 6.

[0081] like Figure 2 As shown, the silicon substrate 1 can be made of single-crystal silicon. Shallow trench isolation 102 is formed on the silicon substrate 1, and active regions 103 are provided between the shallow trench isolation 102. The gate structure 2 is located in the active regions 103. The active regions 103 also have bit line structures and word line structures (not shown in the figure), and the word line structures and bit line structures are located at different heights. Both the word line structures and bit line structures are electrically connected to the active regions 103.

[0082] The gate structure 2 is located on a silicon substrate 1, which includes source and drain doped regions 101 located on opposite sides of the gate structure 2. Figure 10 As shown, the gate structure 2 includes a gate stack structure, a nitride isolation layer 204 covering the sidewalls of the gate stack structure, and an oxide isolation layer 205 covering the sidewalls of the nitride isolation layer 204.

[0083] Continue to refer to Figure 10 The gate stack structure includes a gate dielectric layer 201, a gate layer 202, and an insulating capping layer 203 sequentially stacked from the surface of the silicon substrate 1. The gate layer 202 can be a stack, including a polysilicon layer and a metal material layer sequentially stacked from the gate dielectric layer 201, or the gate layer 202 can be a single polysilicon layer or a single metal material layer; no particular limitation is made here. In some embodiments, the metal material layer may include at least one of tungsten, copper, and aluminum. In some embodiments, the material of the gate dielectric layer 201 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the insulating capping layer 203 may be silicon nitride.

[0084] like Figure 10 As shown, a nitride isolation layer 204 covers the sidewalls of the gate stack structure, thereby insulating the gate stack structure from other functional layers or structures. In some embodiments, the material of the nitride isolation layer 204 may include at least one of silicon nitride and silicon oxynitride. An oxide isolation layer 205 covers the sidewalls of the nitride isolation layer 204, further insulating the gate stack structure from other functional layers or structures and protecting the gate stack structure. In some embodiments, the material of the oxide isolation layer 205 may include silicon oxide.

[0085] like Figure 10 As shown, the dielectric stack 3 is located on the silicon substrate 1 and covers the source / drain doped regions 101. The dielectric stack 3 includes a first nitride layer 301, an oxide layer 302, and a second nitride layer 303 stacked sequentially, as shown. Figure 4As shown, the thickness of the first nitride layer 301 is less than the thickness of the second nitride layer 303, and a contact hole H2 is provided in the dielectric stack 3, penetrating the dielectric stack 3 and exposing the source / drain doped regions 101. The lateral dimension of the contact hole H2 in the first nitride layer 301 and the oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, thus reducing the aspect ratio of the contact hole H2, and as... Figure 5 As shown, the bottom of the contact hole H2 also includes a recess R for forming a metal silicide layer 5. Since the height-to-depth ratio of the contact hole H2 is reduced, it is easier to form a metal silicide layer 5 in the recess R, thereby reducing the contact resistance of the contact plug 6.

[0086] like Figure 5 and Figure 10 As shown, the metal silicide layer 5 is disposed at the bottom of the contact hole H2. Specifically, the metal silicide layer 5 is disposed at the bottom of the contact hole H2, and the bottom of the contact hole H2 is a recess R located in the source / drain doped region 101. That is, the metal silicide layer 5 is disposed in the source / drain doped region 101, so that the formed contact plug 6 can be electrically connected to the source / drain doped region 101.

[0087] like Figure 10 As shown, a nitride pad layer 4 is disposed on the sidewall of the contact hole H2, and the material of the nitride pad layer 4 can be silicon nitride. A contact plug 6 is disposed in the contact hole H2, where the nitride pad layer 4 serves as the sidewall, and the contact plug 6 is electrically connected to the source / drain doped region 101 through the metal silicide layer 5.

[0088] Since the lateral dimension of the contact hole H2 in the first nitride layer 301 and oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, the lateral dimension of the contact plug 6 located in the first nitride layer 301 and oxide layer 302 is larger than its lateral dimension located in the second nitride layer 303, thereby increasing the contact area between the contact plug 6 and the metal silicide layer 5 and further reducing the contact resistance.

[0089] In some embodiments, such as Figure 10 As shown, the contact plug 6 includes a diffusion barrier layer 601 and a metal layer 602. The diffusion barrier layer 601 conformally covers the nitride liner layer 4 in the contact hole H2, and the metal layer 602 covers the diffusion barrier layer 601 and fills the contact hole H2. The diffusion barrier layer 601 prevents the diffusion of the metal in the contact plug 6, ensuring the stability of the electrical performance of the semiconductor structure. The diffusion barrier layer 601 can be a single layer or a stack of different materials. The contact plug 6 is electrically connected to the metal silicide layer 5 through the diffusion barrier layer 601; therefore, the material of the diffusion barrier layer 601 is a conductive material, such as at least one of titanium nitride and tungsten nitride.

[0090] In some embodiments, the semiconductor structure further includes an oxide nitride layer 304 located between the nitride pad layer 4 and the oxide layer 302, and covering the sidewalls of the oxide layer 302 exposed by the contact hole H2.

[0091] In some embodiments, the nitride layer 304 is located only between the nitride pad layer 4 and the oxide layer 302, and the first nitride layer 301 is located between the nitride pad layer 4 and the oxide isolation layer 205. That is, during the formation of the initial contact hole H1 and the contact hole H2, the oxide isolation layer 205 is not exposed, but the first nitride layer 301 is exposed.

[0092] In other embodiments, such as Figure 10 As shown, the oxide nitride layer 304 is located not only between the nitride liner layer 4 and the oxide layer 302, but also between the nitride liner layer 4 and the oxide isolation layer 205. That is, during the formation of the contact hole H2, at least part of the oxide isolation layer 205 is etched away. When the oxide layer 302 is nitrided using a far-field plasma nitriding process, the exposed oxide isolation layer 205 can be nitrided simultaneously to form the oxide nitride layer 304. Since the nitride liner layer 4 is located on the oxide nitride layer 304, the bonding between the nitride liner layer 4 and the inner wall of the contact hole H2 is more stable. At the same time, the oxide nitride layer 304 can further prevent the metal spread of the contact plug 6.

[0093] In summary, in the semiconductor structure of this embodiment, since the lateral dimension of the contact hole H2 in the first nitride layer 301 and oxide layer 302 is larger than the lateral dimension of the contact hole H2 in the second nitride layer 303, the aspect ratio of the contact hole H2 is reduced, making it easier to form a metal silicide layer 5 at the bottom of the contact hole H2, and the area of ​​the metal silicide layer 5 is larger, thus reducing the contact resistance of the contact plug 6; since a nitride pad layer 4 is formed on the sidewall of the contact hole H2, metal diffusion of the contact plug 6 can be prevented, improving the stability of the semiconductor structure and increasing the yield.

[0094] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A silicon substrate is provided, on which a gate structure is disposed, the silicon substrate including source and drain doped regions located on opposite sides of the gate structure; A dielectric stack covering the source / drain doped regions is formed on the silicon substrate. The dielectric stack includes a first nitride layer, an oxide layer, and a second nitride layer sequentially stacked on the source / drain doped regions, wherein the thickness of the first nitride layer is less than the thickness of the second nitride layer. The dielectric stack is etched to form initial contact holes that expose the source and drain doped regions. The lateral dimension of the initial contact holes in the first nitride layer and the oxide layer is smaller than the lateral dimension of the initial contact holes in the second nitride layer. The sidewalls of the oxide layer and the first nitride layer exposed by the initial contact hole are etched to form a contact hole, wherein the lateral dimension of the contact hole in the first nitride layer and the oxide layer is larger than the lateral dimension of the contact hole in the second nitride layer; A metal silicide layer is formed at the bottom of the contact hole; A nitride liner layer is formed on the sidewall of the contact hole; A contact plug is formed in the contact hole, and the contact plug is electrically connected to the source / drain doped region through the metal silicide layer.

2. The method according to claim 1, characterized in that, Before the nitride liner layer is formed on the sidewall of the contact hole, the method further includes: The sidewalls of the oxide layer exposed by the contact hole are nitrided using a far-field plasma nitriding process to form a nitride layer; The nitride liner layer covers the oxide nitride layer.

3. The method according to claim 1, characterized in that, The gate structure includes a gate stack structure, a nitride isolation layer covering the sidewalls of the gate stack structure, and an oxide isolation layer covering the sidewalls of the nitride isolation layer; The first nitride layer also covers the oxide isolation layer; During the formation of the initial contact hole, the oxide isolation layer is partially etched; During the formation of the contact hole, the oxide isolation layer is partially etched.

4. The method according to claim 3, characterized in that, Before the nitride liner layer is formed on the sidewall of the contact hole, the method further includes: The sidewalls of the oxide layer exposed by the contact hole and the sidewalls of the oxide isolation layer are nitrided using a far-field plasma nitriding process to form a nitride layer. The nitride liner layer covers the oxide nitride layer.

5. The method according to any one of claims 1 to 4, characterized in that, The contact hole includes a recess located in the silicon substrate, and the metal silicide layer is located within the recess.

6. The method according to any one of claims 1 to 4, characterized in that, Forming the contact plug in the contact hole includes: A diffusion barrier layer is formed that conformally covers the nitride liner layer and the metal silicide layer; A metal layer is formed that covers the diffusion barrier layer and fills the contact hole.

7. A semiconductor structure, characterized in that, include: silicon substrate; A gate structure is located on the silicon substrate, the silicon substrate including source and drain doped regions located on opposite sides of the gate structure; A dielectric stack includes a first nitride layer, an oxide layer, and a second nitride layer sequentially stacked on the source / drain doped regions, wherein the thickness of the first nitride layer is less than the thickness of the second nitride layer, and the dielectric stack has contact holes that expose the source / drain doped regions. A metal silicide layer is disposed at the bottom of the contact hole, and the metal silicide layer is formed after the contact hole; A nitride liner layer is disposed on the sidewall of the contact hole; A contact plug is disposed in the contact hole where the nitride liner layer serves as the sidewall, and the contact plug is electrically connected to the source / drain doped region through the metal silicide layer; Wherein, the lateral dimension of the contact plug in the first nitride layer and the oxide layer is greater than the lateral dimension of the contact plug in the second nitride layer.

8. The semiconductor structure according to claim 7, characterized in that, Also includes: A nitride oxide layer is located between the nitride liner layer and the oxide layer, and covers the sidewalls of the oxide layer exposed by the contact holes.

9. The semiconductor structure according to claim 8, characterized in that, The gate structure includes a gate stack structure, a nitride isolation layer covering the sidewalls of the gate stack structure, and an oxide isolation layer covering the sidewalls of the nitride isolation layer; The oxide nitride layer is disposed between the oxide isolation layer and the nitride liner layer.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that, The contact plug includes: A diffusion barrier layer conformally covers the nitride liner layer and the metal silicide layer; A metal layer covers the diffusion barrier layer and fills the contact hole.

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