A current divider circuit

Abstract

This invention provides a current divider circuit, comprising: a multiplier for multiplying an input current analog signal and a reference current analog signal; an operational amplifier for filtering and amplifying the output signal of the multiplier; an output frequency regulator for adjusting the frequency of the output signal of the operational amplifier; a latch comparator for converting the frequency signal output by the output frequency regulator into a square wave signal related to the input current analog signal; and an output conversion circuit for converting the square wave signal output by the latch comparator to obtain the division result of the input current analog signal and the reference current analog signal. This invention can realize the division of two analog input current signals. This structure effectively eliminates the influence of process deviations and input errors caused by traditional circuit structures on the signal conditioning system, improves the conversion accuracy of the signal conditioning system, and has the advantages of simple design, flexibility, and ease of implementation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a current divider circuit. Background Technology

[0002] With the continuous development of the chip industry and the increasing complexity of modern displacement sensor signal conditioning systems, the requirements for linearity, conversion accuracy, temperature variation, and power consumption of these systems are gradually increasing. A displacement sensor signal conditioning system is an electronic device used to process and improve the signals generated by displacement sensors, converting them into readable data. Traditional displacement sensor signal conditioning systems often employ complex circuits such as analog-to-digital converters (ADCs) and logic control units for signal acquisition and processing. Because they use ADCs for signal acquisition and processing, they are susceptible to errors caused by manufacturing processes, which are difficult to eliminate. Therefore, existing displacement sensor signal conditioning systems suffer from structural complexity and low accuracy. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a current divider circuit that solves the problems of complex structure and low accuracy in existing displacement sensor signal conditioning systems.

[0004] This invention provides a current divider circuit, comprising: a multiplier, an operational amplifier, an output frequency regulator, a latch comparator, an output conversion circuit, and a bias circuit. The multiplier multiplies an input current analog signal and a reference current analog signal. The input terminal of the operational amplifier is connected to the output terminal of the multiplier, used to filter and amplify the output signal of the multiplier. The input terminal of the output frequency regulator is connected to the output terminal of the operational amplifier, used to adjust the frequency of the operational amplifier's output signal. The input terminal of the latch comparator is connected to the output terminal of the output frequency regulator, used to convert the frequency signal output by the output frequency regulator into a square wave signal related to the input current analog signal. The input terminal of the output conversion circuit is connected to the output terminal of the latch comparator, used to convert the square wave signal output by the latch comparator to obtain the division result of the input current analog signal and the reference current analog signal. The bias circuit provides a bias signal to the multiplier, the operational amplifier, the output frequency regulator, the latch comparator, and the output conversion circuit.

[0005] Optionally, the multiplier includes: a multiplication module, a current input module, and an output filtering module; the input terminal of the multiplication module is connected to the output terminal of the latch comparator and the reference current output terminal, respectively, for multiplying the square wave signal output by the latch comparator with the reference current analog signal; the input terminal of the current input module is connected to the output terminal of the latch comparator and the current input terminal, respectively, for multiplying the square wave signal output by the latch comparator with the input current analog signal; the output filtering module is connected to the input terminal of the multiplication module and the output terminal of the current input module, respectively, for multiplying and filtering the output signal of the multiplication module and the output signal of the current input module.

[0006] Optionally, the multiplication module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the bases of the first transistor and the fourth transistor are respectively connected to the second output terminal of the latch comparator; the bases of the second transistor and the third transistor are respectively connected to the first output terminal of the latch comparator; the collector of the first transistor is connected to the collector of the third transistor; the collector of the second transistor is connected to the collector of the fourth transistor; the emitters of the first transistor and the second transistor are respectively connected to the collector of the fifth transistor; the emitters of the third transistor and the fourth transistor are respectively connected to the collector of the sixth transistor; the bases of the fifth transistor and the sixth transistor are respectively connected to the bias circuit; and the emitters of the fifth transistor and the sixth transistor are respectively connected to the reference current output terminal.

[0007] Optionally, the current input module includes: a seventh transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, an eleventh transistor, and a twelfth transistor; the bases of the seventh and ninth transistors are respectively connected to the second output terminal of the latch comparator, the bases of the eighth and thirteenth transistors are respectively connected to the first output terminal of the latch comparator, the collectors of the seventh and eighth transistors are respectively connected to the collector of the fourth transistor, and the collector of the ninth transistor... The collectors of the eleventh and thirteenth transistors are connected to the collector of the first transistor, the emitters of the seventh and eighth transistors are connected to the collector of the eleventh transistor, the emitters of the ninth and thirteenth transistors are connected to the collector of the twelfth transistor, the bases of the eleventh and twelfth transistors are connected to the bias circuit, and the emitters of the eleventh and twelfth transistors are connected to the current input terminal.

[0008] Optionally, the output filtering module includes: a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a thirteenth transistor, and a fourteenth transistor; the bases of the thirteenth transistor and the fourteenth transistor are respectively connected to the bias circuit; the emitter of the thirteenth transistor is connected to the collector of the first transistor; the emitter of the thirteenth transistor is also connected to the emitter of the fourteenth transistor through the first capacitor; the collector of the thirteenth transistor is grounded through the second capacitor; and the collector of the thirteenth transistor is also connected to the power supply terminal through the first resistor; the emitter of the fourteenth transistor is connected to the collector of the fourth transistor; the collector of the fourteenth transistor is grounded through the third capacitor; and the collector of the fourteenth transistor is also connected to the power supply terminal through the second resistor.

[0009] Optionally, the operational amplifier includes: a fifteenth transistor, a sixteenth transistor, a third resistor, a fourth resistor, a fifth resistor, a first P-type transistor, and a second P-type transistor; the base of the fifteenth transistor is connected to the first output terminal of the multiplier, the collector of the fifteenth transistor is connected to the power supply terminal, the base of the sixteenth transistor is connected to the second output terminal of the multiplier, the collector of the sixteenth transistor is connected to the power supply terminal, the base of the first P-type transistor is connected to the emitter of the fifteenth transistor, the emitter of the first P-type transistor is connected to the base of the fifteenth transistor through the third resistor, and the emitter of the second P-type transistor is connected to the base of the sixteenth transistor through the fourth resistor.

[0010] Optionally, the operational amplifier further includes: a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twenty-third transistor, a twenty-first transistor, a sixth resistor, a seventh resistor, an eighth resistor, a third P-type transistor, a fourth capacitor, and a fifth capacitor; the collector of the seventeenth transistor is connected to the emitter of the fifteenth transistor, the base of the seventeenth transistor is connected to the bias circuit, and the emitter of the seventeenth transistor is grounded through the seventh resistor; the collector of the eighteenth transistor is connected to the emitter of the sixteenth transistor, the base of the eighteenth transistor is connected to the bias circuit, and the emitter of the eighteenth transistor is grounded through the eighth resistor; the bases of the nineteenth transistor and the twenty-third transistor are connected to the bias circuit. The emitters of the nineteenth and twenty-third transistors are grounded, the collector of the nineteenth transistor is connected to the collector of the first P-type transistor, and the collector of the twenty-third transistor is connected to the collector of the second P-type transistor. The bases of the three P-type transistors and the twenty-first transistor are respectively connected to the bias circuit. The emitter of the third P-type transistor is connected to the power supply terminal through the sixth resistor, and the collector of the third P-type transistor is connected to the collector of the twenty-first transistor. The emitter of the twenty-first transistor is connected to the base of the fifteenth transistor through the fourth capacitor, and the emitter of the twenty-first transistor is connected to the base of the sixteenth transistor through the fifth capacitor.

[0011] Optionally, the latch comparator includes: a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, a 26th transistor, a 27th transistor, a 28th transistor, a 29th transistor, a 33rd transistor, a 9th resistor, a 10th resistor, an 11th resistor, a 12th resistor, a 13th resistor, and a 14th resistor; the base of the 22nd transistor is connected to the first output terminal of the output frequency regulator, the collector of the 22nd transistor is connected to the bias circuit through the 9th resistor, and the base of the 23rd transistor is connected to the... The second output terminal of the output frequency regulator is connected; the collector of the 23rd transistor is connected to the bias circuit through the 10th resistor; the base of the 24th transistor is connected to the collector of the 23rd transistor, and the collector of the 24th transistor is connected to the bias circuit through the 11th resistor; the base of the 25th transistor is connected to the collector of the 22nd transistor, and the collector of the 25th transistor is connected to the bias circuit through the 12th resistor; the base of the 26th transistor is connected to the collector of the 27th transistor. The collector of the 26th transistor is connected to the collector of the 25th transistor, and the collector of the 27th transistor is connected to the collector of the 24th transistor; the collector of the 28th transistor is connected to the emitters of the 22nd and 23rd transistors respectively, the base of the 28th transistor is connected to the bias circuit, and the emitter of the 28th transistor is grounded; the bases of the 29th, 33rd, and 31st transistors are respectively connected to the bias circuit. The collector of the 29th transistor is connected to the emitter of the 24th transistor and the 25th transistor, respectively. The emitter of the 29th transistor is grounded through the 13th resistor. The collector of the 33rd transistor is connected to the emitter of the 26th transistor and the 27th transistor, respectively. The emitter of the 33rd transistor is connected to the 14th resistor. The emitter of the 31st transistor is connected to the 22nd transistor through the 9th resistor. The collector of the 31st transistor is connected to the power supply terminal.

[0012] Optionally, the bias circuit includes: a 32nd transistor, a 33rd transistor, a 34th transistor, a 35th transistor, a 4th P-type transistor, a 5th P-type transistor, a 15th resistor, a 16th resistor, a 17th resistor, an 18th resistor, a 19th resistor, a 20th resistor, and a 21st resistor; the base of the 4th P-type transistor is connected to the base of the 5th P-type transistor, the emitter of the 4th P-type transistor is connected to the power supply terminal through the 15th resistor, the emitter of the 5th P-type transistor is connected to the power supply terminal through the 16th resistor, the collector of the 4th P-type transistor is connected to the collector of the 32nd transistor, and the emitter of the 32nd transistor is connected to the power supply terminal through the 15th resistor. The twentieth resistor is grounded; the collector of the fifth P-type transistor is connected to the collector of the thirty-fifth transistor through the seventeenth resistor, the emitter of the thirty-fifth transistor is connected to the collector of the thirty-fourth transistor, the base of the thirty-fourth transistor is connected to the collector of the thirty-fifth transistor through the eighteenth resistor, the base of the thirty-fourth transistor is connected to the emitter of the thirty-fourth transistor through the nineteenth resistor, the collector of the thirty-third transistor is connected to the emitter of the thirty-fourth transistor, the collector of the thirty-third transistor is connected to the base of the thirty-third transistor, and the emitter of the thirty-third transistor is grounded through the twenty-first resistor.

[0013] Optionally, the output conversion circuit includes: a 36th transistor, a 37th transistor, a 38th transistor, a 22nd resistor, a 23rd resistor, a 24th resistor, a 25th resistor, a 6th capacitor, and an amplifier; the base of the 36th transistor is connected to the first output terminal of the latch comparator, the collector of the 36th transistor is connected to the inverting input terminal of the amplifier through the 24th resistor, the base of the 37th transistor is connected to the second output terminal of the latch comparator, and the collector of the 37th transistor is connected to the non-inverting input terminal of the amplifier; the inverting input terminal of the amplifier is connected to the output terminal of the amplifier through the 22nd resistor, and the non-inverting input terminal of the amplifier is connected to the output terminal of the amplifier through the 23rd resistor; the collector of the 36th transistor is also connected to the collector of the 37th transistor through the 6th capacitor, the collector of the 38th transistor is connected to the emitter of the 36th transistor and the emitter of the 37th transistor respectively, and the emitter of the 38th transistor is grounded through the 25th resistor.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The current divider circuit provided by this invention for a displacement sensor signal conditioning system can divide two analog input current signals. Since process deviations have a similar impact on both currents, this impact is directly eliminated through the divider's ratio. Therefore, this structure effectively eliminates the influence of process deviations and input errors caused by traditional circuit structures on the signal conditioning system, improving the conversion accuracy of the signal conditioning system. Furthermore, because it uses a structure that divides two analog current signals (temperature has a similar impact on both currents, which is directly eliminated through the divider's ratio), it eliminates the influence of temperature on the circuit output, achieving a wider operating temperature range. Existing displacement sensor signal conditioning systems typically employ analog-to-digital converters, controller data converters, and SIP packages, resulting in complex structures, large areas, and high costs. This structure does not involve analog-to-digital converters or controller data converters, effectively solving problems related to miniaturization, monolithic integration, and low cost. The overall circuit has the advantages of simple design, flexibility, and ease of implementation. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a current divider circuit provided in an embodiment of the present invention;

[0017] Figure 2 A circuit diagram of a multiplier provided in an embodiment of the present invention;

[0018] Figure 3 A circuit diagram of an operational amplifier provided for an embodiment of the present invention;

[0019] Figure 4 This is a circuit diagram of a latch comparator provided in an embodiment of the present invention;

[0020] Figure 5 A circuit diagram of a bias circuit provided in an embodiment of the present invention;

[0021] Figure 6 A circuit diagram of an output conversion circuit provided in an embodiment of the present invention;

[0022] Figure 7 The equivalent circuit diagram is provided for the theoretical derivation of a current divider circuit according to an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Example 1

[0025] Figure 1A circuit diagram of the first current divider circuit provided in the embodiments of the present invention is shown below. Figure 1 As shown, the current divider circuit includes:

[0026] Multiplier, operational amplifier, output frequency regulator, latch comparator, output conversion circuit and bias circuit;

[0027] The multiplier is used to multiply the input current analog signal and the reference current analog signal;

[0028] The input terminal of the operational amplifier is connected to the output terminal of the multiplier, and is used to filter and amplify the output signal of the multiplier;

[0029] The input terminal of the output frequency regulator is connected to the output terminal of the operational amplifier, and is used to adjust the frequency of the output signal of the operational amplifier;

[0030] The input terminal of the latch comparator is connected to the output terminal of the output frequency regulator, and is used to convert the frequency signal output by the output frequency regulator into a square wave signal related to the input current analog signal.

[0031] The input terminal of the output conversion circuit is connected to the output terminal of the latch comparator, and is used to convert the square wave signal output by the latch comparator to obtain the division result of the input current analog signal and the reference current analog signal.

[0032] The bias circuit provides bias signals for the multiplier, the operational amplifier, the output frequency regulator, the latch comparator, and the output conversion circuit.

[0033] In this embodiment, Figure 1 I in A I is the analog input current signal for the current divider circuit; B The input reference current analog signal is the current signal of the current divider circuit, and its two analog current signals I A and I B It can be obtained in different ways, not limited to directly inputting current; I out This is the output current signal of the current divider circuit; the external bias module is an external circuit used to provide bias current to the conversion output circuit, so that the conversion output circuit will... A and I B The ratio relationship is converted into current output; the bias circuit is the bias module of the entire current divider circuit, providing bias signals to each module.

[0034] In this embodiment, a multiplier is used to multiply two analog signals to obtain the multiplied output signal. One analog signal is a constant input signal, serving as the reference input signal for the current divider, and the other analog signal is the input signal for the current divider. An operational amplifier is used to amplify and filter the output signal of the multiplier so that the subsequent stage can detect the correct input signal and output it to the next stage. An output frequency regulator is used to determine the frequency of the output signal to obtain the desired signal frequency of the signal conditioning system. It is flexible and convenient to design, and by designing a suitable output frequency regulator, the requirement for low-pass filtering in the signal conditioning system can be reduced. A latch comparator is used to convert the signal output by the output frequency regulator into a square wave signal related to the input signal, which is then provided to the next stage for conversion and output. An output conversion circuit is used to convert the output square wave signal of the latch comparator to obtain the final result of the current division.

[0035] This invention eliminates the need for traditional analog-to-digital converters (ADCs) and controller-to-data converters (CTCs) processing units. Instead, it employs a novel current divider to replace these components and achieve signal conditioning functionality. This current divider can divide two analog input current signals. First, this structure effectively eliminates the impact of process variations and input errors caused by traditional circuit structures on the signal conditioning system, improving its conversion accuracy. Second, because it uses a structure that divides two analog current signals, it eliminates the influence of temperature on the circuit output, achieving a wider operating temperature range. Third, existing signal conditioning systems mostly employ ADCs, CTCs, and SIP packages, resulting in complex structures, large areas, and high costs. This new structure effectively solves problems related to miniaturization, monolithic integration, and low cost, offering advantages such as simple design, flexibility, and ease of implementation.

[0036] Example 2

[0037] In this embodiment, the multiplier includes a multiplication module, a current input module, and an output filtering module. The input terminal of the multiplication module is connected to the output terminal of the latch comparator and the reference current output terminal, respectively, and is used to multiply the square wave signal output by the latch comparator with the reference current analog signal. The input terminal of the current input module is connected to the output terminal of the latch comparator and the current input terminal, respectively, and is used to multiply the square wave signal output by the latch comparator with the input current analog signal. The output filtering module is connected to the input terminal of the multiplication module and the output terminal of the current input module, respectively, and is used to multiply and filter the output signal of the multiplication module and the output signal of the current input module.

[0038] like Figure 2As shown, the multiplication module includes: a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, and a sixth transistor N6; the bases of the first transistor N1 and the fourth transistor N4 are respectively connected to the second output terminal of the latch comparator, the bases of the second transistor N2 and the third transistor N3 are respectively connected to the first output terminal of the latch comparator, the collector of the first transistor N1 is connected to the collector of the third transistor N3, and the collector of the second transistor N2 is connected to the collector of the third transistor N3. The emitter of the first transistor N1 and the emitter of the second transistor N2 are connected to the collector of the fifth transistor N5, the emitter of the third transistor N3 and the emitter of the fourth transistor N4 are connected to the collector of the sixth transistor N6, the base of the fifth transistor N5 and the base of the sixth transistor N6 are connected to the bias circuit, and the emitter of the fifth transistor N5 and the emitter of the sixth transistor N6 are connected to the reference current output terminal.

[0039] In this embodiment, the current input module includes: a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a thirteenth transistor N10, an eleventh transistor N11, and a twelfth transistor N12; the bases of the seventh transistor N7 and the ninth transistor N9 are respectively connected to the second output terminal of the latch comparator, the bases of the eighth transistor N8 and the thirteenth transistor N10 are respectively connected to the first output terminal of the latch comparator, the collectors of the seventh transistor N7 and the eighth transistor N8 are respectively connected to the collector of the fourth transistor N4, and the ninth transistor N9... The collectors of the first transistor N1 and the thirteenth transistor N10 are connected to the collector of the first transistor N1. The emitters of the seventh transistor N7 and the eighth transistor N8 are connected to the collector of the eleventh transistor N11. The emitters of the ninth transistor N9 and the thirteenth transistor N10 are connected to the collector of the twelfth transistor N12. The bases of the eleventh transistor N11 and the twelfth transistor N12 are connected to the bias circuit. The emitters of the eleventh transistor N11 and the twelfth transistor N12 are connected to the current input terminal.

[0040] In this embodiment, the output filtering module includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a thirteenth transistor N13, and a fourteenth transistor N14; the bases of the thirteenth transistor N13 and the fourteenth transistor N14 are respectively connected to the bias circuit, the emitter of the thirteenth transistor N13 is connected to the collector of the first transistor N1, and the emitter of the thirteenth transistor N13 is also connected through the first capacitor C1. The emitter of the fourteenth transistor N14 is connected to the collector of the thirteenth transistor N13, which is grounded through the second capacitor C2. The collector of the thirteenth transistor N13 is also connected to the power supply terminal through the first resistor R1. The emitter of the fourteenth transistor N14 is connected to the collector of the fourth transistor N4, which is grounded through the third capacitor C3. The collector of the fourteenth transistor N14 is also connected to the power supply terminal through the second resistor R2.

[0041] It should be noted that the multiplication module includes transistors N1, N2, N3, N4, N5, and N6; wherein N1, N2, N3, and N4 form an upper input cross pair, and N5 and N6 form a lower input pair. The current input module includes N7, N8, N9, N10, N11, and N12. The output filtering module includes capacitors C1, C2, and C3, resistors R1 and R2, and transistors N13 and N14.

[0042] The multiplication module is implemented using an analog multiplier based on Gilbert cells, and its working principle is exactly the same as that of an analog multiplier using Gilbert cells. The current input module receives an external current flowing through N7, N8, N9, N10, N11, and N12, which is ultimately superimposed on the output current of the analog multiplier of the Gilbert cell. This is regulated by a feedback control signal to achieve balance. N7, N8, N9, and N10 form the signal input transmission gate, conducting the input signal current, while N11 and N12 act as input transistors. The filtering module is implemented using an RC circuit, and its working principle is the same as that of an RC low-pass filter, filtering out high-frequency noise.

[0043] The formula derivation for this embodiment is as follows: Reference current I B The signal is input through the emitters of N5 and N6 and compared with the output signal V of the latch comparator. out The result of multiplying is as follows:

[0044] For a low-frequency modulated sinusoidal input reference current signal I B Result: I B (t)=I B cosω B t;

[0045] The output of the latch comparator is a high-frequency square wave input of ±1, resulting in:

[0046]

[0047]

[0048] Therefore, the output signal of the multiplication module is:

[0049]

[0050] Where K is the gain obtained by the multiplier from the input to the output of the small signal, and ω m The frequency of the input signal, ω out For the output frequency of the latch comparator, B n This represents the peak-to-peak value of the input signal current.

[0051] Reference current I A The result obtained by multiplying the output signal Vout of the latch comparator by the emitter inputs of N11 and N12 is as follows:

[0052] For a low-frequency modulated sinusoidal input reference current signal I A have

[0053] I A (t)=-I A cosω A t

[0054] Therefore I A The corresponding output signal for channel A is:

[0055] I out2 (t)=K[I A [(t)]=-KI A cosω out t

[0056] Where K is the gain of the small signal from input to output after passing through the multiplier, and "-" represents I. A with I B They are inverse relationships. The total output of the multiplier is the reference current I. B (t) and I A The algebraic sum of (t) has

[0057] I out3 (t)=I out1 (t)-I out2 (t)

[0058] The following is a quantitative analysis of the above equation from the perspective of DC analysis:

[0059] like Figure 2As shown, the currents flowing through N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, and N12 are defined as I1, I2, I3, I4, I5, I6, I7, I8, I9, and I... 10 I 11 I 12 Then the collector currents of N1, N2, N3, N4, N5, and N6 are:

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066] Substituting I5 and I6 into I1, I2, I3, and I4 respectively, we get:

[0067]

[0068]

[0069]

[0070]

[0071] The formula for calculating the differential output current is given below:

[0072]

[0073] Therefore, the DC transfer characteristic is the product of the hyperbolic tangent functions of the two input voltages. The conversion between voltage and current can be completed simply by dividing by the equivalent resistance, so it can be regarded as a current multiplier.

[0074] Therefore, let's return to equation I. out3 (t)=I out1 (t)-I out2 (t), this formula follows the same calculation logic as ΔI=(I1-I4)-(I2-I3), therefore it can be explained that I B (t) and I A The output of the algebraic sum of (t) is also a product relationship, thus completing the derivation of the working principle of the multiplier.

[0075] Theoretically derived from the entire divider, the entire divider module can be equivalent to... Figure 7 The circuit shown, I B As a reference input current signal, I A For the input current signal, I B Through a gain level K B , to obtain I B K B I A Through a gain level K A , to obtain I A K A From the virtual short of the op-amp, the output of the divider can be obtained as:

[0076] I A K A =K B I B ×I out1

[0077]

[0078] Let K A / K B =K, then we have:

[0079]

[0080] Example 3

[0081] like Figure 3 As shown, the operational amplifier includes: a fifteenth transistor N15, a sixteenth transistor N16, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first P-type transistor P1, and a second P-type transistor P2; the base of the fifteenth transistor N15 is connected to the first output terminal of the multiplier, and the collector of the fifteenth transistor N15 is connected to the power supply terminal; the base of the sixteenth transistor N16 is connected to the second output terminal of the multiplier, and the collector of the sixteenth transistor N16 is connected to the power supply terminal; the base of the first P-type transistor P1 is connected to the emitter of the fifteenth transistor N15, and the emitter of the first P-type transistor P1 is connected to the base of the fifteenth transistor N15 through the third resistor R3; the emitter of the second P-type transistor P2 is connected to the base of the sixteenth transistor N16 through the fourth resistor R4.

[0082] In this embodiment, the operational amplifier further includes: a seventeenth transistor N17, an eighteenth transistor N18, a nineteenth transistor N19, a twenty-third transistor N20, a twenty-first transistor N21, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third P-type transistor P3, a fourth capacitor C4, and a fifth capacitor C5; the collector of the seventeenth transistor N17 is connected to the emitter of the fifteenth transistor N15, the base of the seventeenth transistor N17 is connected to the bias circuit, and the emitter of the seventeenth transistor N17 is grounded through the seventh resistor R7; the collector of the eighteenth transistor N18 is connected to the emitter of the sixteenth transistor N16, the base of the eighteenth transistor N18 is connected to the bias circuit, and the emitter of the eighteenth transistor N18 is grounded through the eighth resistor R8; the base of the nineteenth transistor N19 and the twenty-third transistor N20... The base of the transistor is connected to the bias circuit. The emitter of the nineteenth transistor N19 and the emitter of the twenty-third transistor N20 are grounded. The collector of the nineteenth transistor N19 is connected to the collector of the first P-type transistor P1. The collector of the twenty-third transistor N20 is connected to the collector of the second P-type transistor P2. The base of the three P-type transistors and the base of the twenty-first transistor N21 are respectively connected to the bias circuit. The emitter of the third P-type transistor P3 is connected to the power supply terminal through the sixth resistor R6. The collector of the third P-type transistor P3 is connected to the collector of the twenty-first transistor N21. The emitter of the twenty-first transistor N21 is connected to the base of the fifteenth transistor N15 through the fourth capacitor C4. The emitter of the twenty-first transistor N21 is connected to the base of the sixteenth transistor N16 through the fifth capacitor C5.

[0083] It should be noted that, as Figure 3 As shown, in the operational amplifier circuit, transistors N15, N16, P1, P2, R3, R4, and R5 constitute the core circuit of the operational amplifier, transistors N17, N18, N19, N20, N21, P3, resistors R6, R7, and R8 constitute the bias circuit of the operational amplifier circuit, and capacitors C4 and C5 constitute the frequency selection network. The total transconductance of the amplifier input stage can be calculated.

[0084] The input stage consists of N15 and N16, and the total transconductance is:

[0085]

[0086] Where i out The output current of the input stage, v id For the input differential voltage, g m1 The transconductance of the N15 tube.

[0087] The total output equivalent resistance of the transconductance amplifier is:

[0088] R out =g m1 r 01 / / r 02

[0089] Where r 01 The on-resistance of transistor N15 is r. 02 This is the on-resistance of the N17 transistor.

[0090] Therefore, the gain of the transconductance amplifier is:

[0091] A v =G m R out

[0092] The arithmetic amplifier circuit amplifies the output signal of the multiplier. m R oit The output is passed to the next level.

[0093] Example 4

[0094] In this embodiment, the output frequency regulator only includes capacitor C0, and its working principle is based on an RC filter circuit. The output frequency of the RC circuit is defined as:

[0095]

[0096] Substituting the values ​​of R and C, we get:

[0097]

[0098] Wherein, R5 is the corresponding fifth resistor R5 in the operational amplifier.

[0099] Example 5

[0100] like Figure 4As shown, the latch comparator includes: transistors N22 (22nd), N23 (23rd), N24 (24th), N25 (25th), N26 (26th), N27 (27th), N28 (28th), N29 (29th), N30 (33rd), N31 (31st), resistors R9 (9th), R10 (10th), R11 (11th), R12 (12th), R13 (13th), and R14 (14th); the base of transistor N22 is connected to the first output terminal of the output frequency regulator, the collector of transistor N22 is connected to the bias circuit through resistor R9, and the base of transistor N23 is connected to the second output terminal of the output frequency regulator. The collector of transistor N23 is connected to the bias circuit through the tenth resistor R10; the base of transistor N24 is connected to the collector of transistor N23, and the collector of transistor N24 is connected to the bias circuit through the eleventh resistor R11; the base of transistor N25 is connected to the collector of transistor N22, and the collector of transistor N25 is connected to the bias circuit through the twelfth resistor R12; the base of transistor N26 is connected to the collector of transistor N27, the collector of transistor N26 is connected to the collector of transistor N25, and the collector of transistor N27 is connected to the collector of transistor N24.

[0101] The collector of the 28th transistor N28 is connected to the emitter of the 22nd transistor N22 and the emitter of the 23rd transistor N23, respectively. The base of the 28th transistor N28 is connected to the bias circuit, and the emitter of the 28th transistor N28 is grounded. The bases of the 29th transistor N29, the 33rd transistor N30, and the 31st transistor N31 are connected to the bias circuit, respectively. The collector of the 29th transistor N29 is connected to the emitter of the 24th transistor N24 and the 25th transistor N25. The emitter of transistor N25 is connected to the ground, the emitter of transistor N29 is grounded through resistor R13, the collector of transistor N30 is connected to the emitters of transistors N26 and N27 respectively, and the emitter of transistor N30 is connected to the ground through resistor R14; the emitter of transistor N31 is connected to transistor N22 through resistor R9, and the collector of transistor N31 is connected to the power supply.

[0102] It should be noted that, as Figure 5 As shown, transistors N22, N23, and N28, along with resistors R9 and R10, form the input amplification stage in the latch comparator to provide a certain gain. Transistors N24, N25, N26, N27, N29, and N30, along with resistors R11, R12, R13, and R14, form the latch, which quickly converts the output signal of the output frequency regulator into a square wave signal. Transistor N31 forms a step-down module. Net5 is connected to Net6 of the bias circuit, and Vb4 is connected to Net8 of the bias circuit, reducing the supply voltage of the latch comparator circuit to a suitable voltage so that the switching transistors N1, N2, N3, N4, N5, N6, N7, and N8 of the multiplier circuit can be quickly turned on and off.

[0103] The working principle of a latch comparator is to compare two input signals and output the result of the comparison. The output result is directly pulled to VDD or GND through the comparator's gain stage. Therefore, the input can be an analog signal, while the output is a digital level 0 or 1.

[0104] The gain expression for the latch comparator is:

[0105]

[0106] Where V oH V OL These represent the high and low levels output by the latch comparator, respectively. IH V IL These are the input voltage values ​​corresponding to when the output reaches its maximum and minimum values, respectively.

[0107] The output voltage expression of the latch comparator is:

[0108] V OUT =2I R11 ×R11

[0109] Among them, I R11 This is the current flowing through resistor R11.

[0110] The small signal input of the comparator is as follows Figure 2 The current I is derived from the middle out The comparator amplifies and compares the result, with a total comparator gain of M and a comparator output of MI. oit .

[0111] The comparator's output I / O expression is as follows:

[0112]

[0113] KM, represented by k, has

[0114]

[0115] Example 6

[0116] In this embodiment, as Figure 5 As shown, the bias circuit includes: a 32nd transistor N32, a 33rd transistor N33, a 34th transistor N34, a 35th transistor N35, a 4th P-type transistor P4, a 5th P-type transistor P5, a 15th resistor R15, a 16th resistor R16, a 17th resistor R17, an 18th resistor R18, a 19th resistor R19, a 20th resistor 20, and a 21st resistor 21. The bases of the 4th P-type transistor P4 and the 5th P-type transistor P5 are connected. The emitter of the 4th P-type transistor P4 is connected to the power supply terminal through the 15th resistor R15. The emitter of the 5th P-type transistor P5 is connected to the power supply terminal through the 16th resistor R16. The collector of the 4th P-type transistor P4 is connected to the collector of the 32nd transistor N32. The emitter of the 32nd transistor N32 is connected to the power supply terminal. The collector of the fifth P-type transistor P5 is connected to the collector of the thirty-fifth transistor N35 through the seventeenth resistor R17. The emitter of the thirty-fifth transistor N35 is connected to the collector of the thirty-fourth transistor N34. The base of the thirty-fourth transistor N34 is connected to the collector of the thirty-fifth transistor N35 through the eighteenth resistor R18. The base of the thirty-fourth transistor N34 is connected to the emitter of the thirty-fourth transistor N34 through the nineteenth resistor R19. The collector of the thirty-third transistor N33 is connected to the emitter of the thirty-fourth transistor N34. The collector of the thirty-third transistor N33 is connected to the base of the thirty-third transistor N33. The emitter of the thirty-third transistor N33 is connected to the ground through the twenty-first resistor 21.

[0117] It should be noted that, as Figure 7 As shown, the bias circuit includes transistors N32, N33, N34, N35, P4, P5, and resistors R15, R16, R17, R18, R19, R20, and R21. Vb6 is connected to the external bias circuit to obtain a constant reference bias voltage. Net6 is connected to Net5 of the latch comparator. Net7 is connected to Vb2 of the operational amplifier to obtain a suitable bias current. Net8 is connected to Vb4 of the latch comparator to obtain a suitable bias current. Net9 is connected to Vb1 of the operational amplifier and Vb5 of the latch comparator to obtain a suitable bias current.

[0118] Example 7

[0119] like Figure 6 As shown, in this embodiment, the output conversion circuit includes: a 36th transistor N36, a 37th transistor N37, a 38th transistor N38, a 22nd resistor R22, a 23rd resistor R23, a 24th resistor R24, a 25th resistor R25, a 6th capacitor C6, and an amplifier Amp; the base of the 36th transistor N36 is connected to the first output terminal of the latch comparator, the collector of the 36th transistor N36 is connected to the inverting input terminal of the amplifier Amp through the 24th resistor R24, the base of the 37th transistor N37 is connected to the second output terminal of the latch comparator, and the collector of the 37th transistor N37 is connected to the second output terminal of the latch comparator. The non-inverting input terminal of the amplifier Amp is connected; the inverting input terminal of the amplifier Amp is connected to the output terminal of the amplifier Amp through the 22nd resistor R22, and the non-inverting input terminal of the amplifier Amp is connected to the output terminal of the amplifier Amp through the 23rd resistor R23; the collector of the 36th transistor N36 is also connected to the collector of the 37th transistor N37 through the 6th capacitor C6, the collector of the 38th transistor N38 is connected to the emitter of the 36th transistor N36 and the emitter of the 37th transistor N37 respectively, and the emitter of the 38th transistor N38 is grounded through the 25th resistor R25.

[0120] In this embodiment, N36 and N37 are the input conversion stages of the output conversion circuit. Vin4+ is connected to the positive output terminal Vout4+ of the latch comparator, and Vin4- is connected to the positive output terminal Vout4- of the latch comparator. R24 and C6 constitute the filter circuit of the output conversion circuit. R22, R23, and operational amplifier Amp constitute the mirror circuit of the output conversion circuit, so that the current flowing through R22 and R23 is always equal. One end of R22 is connected to the output terminal of operational amplifier Amp, and the other end of R22 is connected to the inverting input terminal of operational amplifier Amp. One end of R23 is connected to the output terminal of operational amplifier Amp, and the other end of R23 is connected to the non-inverting input terminal of operational amplifier Amp. The common terminal of operational amplifier Amp is grounded. N38 and R25 constitute the bias current of the output conversion circuit, providing a constant reference current for the output conversion. Vb6 is connected to the external bias circuit to obtain a constant reference bias voltage.

[0121] Through the Figure 2 , Figure 3 and Figure 5 Analysis of its working principle reveals that the output of the latch comparator is:

[0122]

[0123] At this point, the core circuit and theoretical derivation of this invention have been completed. This formula is the core expression of the current divider, and the derivation process has been given in detail above.

[0124] To verify the feasibility of using a current division circuit for signal conditioning, the working principle and implementation method of the output conversion are further elaborated. The ratio of the currents is converted and output to achieve the final output of the displacement sensor signal conditioning system. As can be seen from the comparator's output expression, inputting two current signals to the current divider will yield a ratio of the currents. To convert this ratio into a specific value, a reference current I needs to be introduced. REF As a measure, such as Figure 6 As shown, I B and I A The ratio can be equivalent to the duty cycle of the comparator output. By controlling the on and off states of N36 and N37, the on-time of N37 is... Therefore, the expression for the converted output current is:

[0125]

[0126] By directly measuring the total output current value, the final quantized output value of the signal conditioning system can be determined, thus completing the signal conditioning process. Wherein, I... A For the input current signal, I B For the input reference current signal, I REF A constant reference current source flows through R25. In this circuit, a stable IREF current is required as the input reference signal by an external bias module.

[0127] Therefore, this invention can realize the division of two analog input current signals. This structure effectively eliminates the influence of process deviations and input errors caused by traditional circuit structures on the signal conditioning system, improving the conversion accuracy of the signal conditioning system. At the same time, since it adopts the structure of dividing two analog current signals, it eliminates the influence of temperature on the circuit output, achieving a wider operating temperature range. Most existing signal conditioning systems are implemented in the form of analog-to-digital converters, controller data converters, processing units, and SIP packages, which are complex, large in area, and expensive. This structure effectively solves the problems of miniaturization, monolithic integration, and low cost. The overall circuit has the advantages of simple design, flexibility, and ease of implementation.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Furthermore, matters not covered in the present invention are well-known technologies. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0129] In this document, relational terms such as “first” and “second” are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A current divider circuit, characterized in that, The current divider circuit includes: Multiplier, operational amplifier, output frequency regulator, latch comparator, output conversion circuit and bias circuit; The multiplier is used to multiply the input current analog signal and the reference current analog signal; The input terminal of the operational amplifier is connected to the output terminal of the multiplier, and is used to filter and amplify the output signal of the multiplier; The input terminal of the output frequency regulator is connected to the output terminal of the operational amplifier, and is used to adjust the frequency of the output signal of the operational amplifier; The input terminal of the latch comparator is connected to the output terminal of the output frequency regulator, and is used to convert the frequency signal output by the output frequency regulator into a square wave signal related to the input current analog signal. The input terminal of the output conversion circuit is connected to the output terminal of the latch comparator, and is used to convert the square wave signal output by the latch comparator to obtain the division result of the input current analog signal and the reference current analog signal. The bias circuit is used to provide bias signals for the multiplier, the operational amplifier, the output frequency regulator, the latch comparator, and the output conversion circuit. The multiplier includes: Multiplication module, current input module, and output filtering module; The input terminal of the multiplication module is connected to the output terminal of the latch comparator and the reference current output terminal, respectively, and is used to multiply the square wave signal output by the latch comparator with the analog signal of the reference current. The input terminal of the current input module is connected to the output terminal and the current input terminal of the latch comparator, respectively, and is used to multiply the square wave signal output by the latch comparator with the input current analog signal. The output filtering module is connected to the input terminal of the multiplication module and the output terminal of the current input module, respectively, and is used to multiply and filter the output signal of the multiplication module and the output signal of the current input module.

2. The current divider circuit as described in claim 1, characterized in that, The multiplication module includes: Transistor 1, Transistor 2, Transistor 3, Transistor 4, Transistor 5, and Transistor 6; The bases of the first and fourth transistors are connected to the second output of the latch comparator, the bases of the second and third transistors are connected to the first output of the latch comparator, the collector of the first transistor is connected to the collector of the third transistor, the collector of the second transistor is connected to the collector of the fourth transistor, the emitters of the first and second transistors are connected to the collector of the fifth transistor, the emitters of the third and fourth transistors are connected to the collector of the sixth transistor, the bases of the fifth and sixth transistors are connected to the bias circuit, and the emitters of the fifth and sixth transistors are connected to the reference current output.

3. The current divider circuit as described in claim 2, characterized in that, The current input module includes: Transistor No. 7, Transistor No. 8, Transistor No. 9, Transistor No. 13, Transistor No. 11, and Transistor No. 12; The bases of the seventh and ninth transistors are connected to the second output of the latch comparator, the bases of the eighth and thirteenth transistors are connected to the first output of the latch comparator, the collectors of the seventh and eighth transistors are connected to the collector of the fourth transistor, the collectors of the ninth and thirteenth transistors are connected to the collector of the first transistor, the emitters of the seventh and eighth transistors are connected to the collector of the eleventh transistor, the emitters of the ninth and thirteenth transistors are connected to the collector of the twelfth transistor, the bases of the eleventh and twelfth transistors are connected to the bias circuit, and the emitters of the eleventh and twelfth transistors are connected to the current input terminal.

4. The current divider circuit as described in claim 3, characterized in that, The output filtering module includes: First capacitor, second capacitor, third capacitor, first resistor, second resistor, thirteenth transistor and fourteenth transistor; The bases of the thirteenth and fourteenth transistors are respectively connected to the bias circuit. The emitter of the thirteenth transistor is connected to the collector of the first transistor. The emitter of the thirteenth transistor is also connected to the emitter of the fourteenth transistor through the first capacitor. The collector of the thirteenth transistor is grounded through the second capacitor. The collector of the thirteenth transistor is also connected to the power supply terminal through the first resistor. The emitter of the fourteenth transistor is connected to the collector of the fourth transistor. The collector of the fourteenth transistor is grounded through the third capacitor. The collector of the fourteenth transistor is also connected to the power supply terminal through the second resistor.

5. A current divider circuit as described in claim 1, characterized in that, The operational amplifier includes: The fifteenth transistor, the sixteenth transistor, the third resistor, the fourth resistor, the fifth resistor, the first P-type transistor, and the second P-type transistor; The base of the fifteenth transistor is connected to the first output terminal of the multiplier, and the collector of the fifteenth transistor is connected to the power supply terminal. The base of the sixteenth transistor is connected to the second output terminal of the multiplier, and the collector of the sixteenth transistor is connected to the power supply terminal. The base of the first P-type transistor is connected to the emitter of the fifteenth transistor. The emitter of the first P-type transistor is connected to the base of the fifteenth transistor through a third resistor and a fourth capacitor. The emitter of the second P-type transistor is connected to the base of the sixteenth transistor through a fourth resistor and a fifth capacitor. The operational amplifier also includes: Transistor number 17, transistor number 18, transistor number 19, transistor number 23, transistor number 21, resistor number 6, resistor number 7, resistor number 8, P-type transistor number 3, capacitor number 4, and capacitor number 5; The collector of the seventeenth transistor is connected to the emitter of the fifteenth transistor, the base of the seventeenth transistor is connected to the bias circuit, and the emitter of the seventeenth transistor is grounded through the seventh resistor; the collector of the eighteenth transistor is connected to the emitter of the sixteenth transistor, the base of the eighteenth transistor is connected to the bias circuit, and the emitter of the eighteenth transistor is grounded through the eighth resistor; the bases of the nineteenth transistor and the twenty-third transistor are connected to the bias circuit, the emitters of the nineteenth transistor and the twenty-third transistor are grounded, the collector of the nineteenth transistor is connected to the collector of the first P-type transistor, and the collector of the twenty-third transistor is connected to the collector of the second P-type transistor; The bases of the three P-type transistors and the twenty-first transistor are respectively connected to the bias circuit. The emitter of the third P-type transistor is connected to the power supply terminal through the sixth resistor. The collector of the third P-type transistor is connected to the collector of the twenty-first transistor. The emitter of the twenty-first transistor is connected to the base of the fifteenth transistor through the fourth capacitor. The emitter of the twenty-first transistor is connected to the base of the sixteenth transistor through the fifth capacitor.

6. The current divider circuit as described in claim 5, characterized in that, The latch comparator includes: Transistor number 22, transistor number 23, transistor number 24, transistor number 25, transistor number 26, transistor number 27, transistor number 28, transistor number 29, transistor number 33, transistor number 31, resistor number 9, resistor number 10, resistor number 11, resistor number 12, resistor number 13, and resistor number 14; The base of the 22nd transistor is connected to the first output terminal of the output frequency regulator, and the collector of the 22nd transistor is connected to the bias circuit through the ninth resistor. The base of the 23rd transistor is connected to the second output terminal of the output frequency regulator, and the collector of the 23rd transistor is connected to the bias circuit through the tenth resistor. The base of the 24th transistor is connected to the collector of the 23rd transistor, and the collector of the 24th transistor is connected to the bias circuit through the eleventh resistor. The base of the 25th transistor is connected to the collector of the 22nd transistor, and the collector of the 25th transistor is connected to the bias circuit through the twelfth resistor. The base of the 26th transistor is connected to the collector of the 27th transistor, the collector of the 26th transistor is connected to the collector of the 25th transistor, the collector of the 27th transistor is connected to the collector of the 24th transistor, and the base of the 27th transistor is connected to the collector of the 26th transistor. The collector of the 28th transistor is connected to the emitter of the 22nd transistor and the emitter of the 23rd transistor, respectively. The base of the 28th transistor is connected to the bias circuit, and the emitter of the 28th transistor is grounded. The bases of the 29th transistor, the 33rd transistor, and the 31st transistor are connected to the bias circuit, respectively. The collector of the 29th transistor is connected to the emitter of the 24th transistor and the 25th transistor, respectively. The emitter of the 29th transistor is grounded through the 13th resistor. The collector of the 33rd transistor is connected to the emitter of the 26th transistor and the 27th transistor, respectively. The emitter of the 33rd transistor is connected to the 14th resistor. The emitter of the 31st transistor is connected to the 22nd transistor through the 9th resistor, and the collector of the 31st transistor is connected to the power supply terminal.

7. A current divider circuit as described in claim 6, characterized in that, The bias circuit includes: Transistor No. 32, Transistor No. 33, Transistor No. 34, Transistor No. 35, Transistor No. 4, Transistor No. 5, Resistor No. 15, Resistor No. 16, Resistor No. 17, Resistor No. 18, Resistor No. 19, Resistor No. 20, and Resistor No. 21; The base of the fourth P-type transistor is connected to the base of the fifth P-type transistor. The emitter of the fourth P-type transistor is connected to the power supply terminal through the fifteenth resistor. The base of the fourth P-type transistor is connected to its collector and to the base of the third P-type transistor in the operational amplifier. The emitter of the fifth P-type transistor is connected to the power supply terminal through the sixteenth resistor. The collector of the fourth P-type transistor is connected to the collector of the thirty-second transistor. The emitter of the thirty-second transistor is grounded through the twentieth resistor. The collector of the fifth P-type transistor is connected to the collector of the thirty-fifth transistor through the seventeenth resistor. The emitter of the thirty-fifth transistor is connected to the collector of the thirty-fourth transistor. The base of the thirty-fifth transistor is connected to the emitter of the thirty-first transistor in the latch comparator. The base of the thirty-fourth transistor is connected to the collector of the thirty-fifth transistor through the eighteenth resistor. The base of the thirty-fourth transistor is connected to the emitter of the thirty-fourth transistor through the nineteenth resistor. The collector of the thirty-third transistor is connected to the emitter of the thirty-fourth transistor. The collector of the thirty-third transistor is connected to the base of the thirty-third transistor. The base of the thirty-third transistor is connected to the base of the seventeenth transistor in the operational amplifier and the base of the twenty-ninth transistor in the latch comparator. The emitter of the thirty-third transistor is grounded through the twenty-first resistor. The base of the thirty-second transistor is connected to the bias voltage Vb7.

8. A current divider circuit as described in claim 1, characterized in that, The output conversion circuit includes: Transistor No. 36, Transistor No. 37, Transistor No. 38, Resistor No. 22, Resistor No. 23, Resistor No. 24, Resistor No. 25, Capacitor No. 6 and Amplifier; The base of the thirty-sixth transistor is connected to the first output terminal of the latch comparator, and the collector of the thirty-sixth transistor is connected to the inverting input terminal of the amplifier through the twenty-fourth resistor. The base of the thirty-seventh transistor is connected to the second output terminal of the latch comparator, and the collector of the thirty-seventh transistor is connected to the non-inverting input terminal of the amplifier. The inverting input terminal of the amplifier is connected to the output terminal of the amplifier through the twenty-second resistor, and the non-inverting input terminal of the amplifier is connected to the output terminal of the amplifier through the twenty-third resistor. The collector of the thirty-sixth transistor is also connected to the collector of the thirty-seventh transistor through the sixth capacitor. The collector of the thirty-eighth transistor is connected to the emitter of the thirty-sixth transistor and the emitter of the thirty-seventh transistor, respectively. The emitter of the thirty-eighth transistor is grounded through the twenty-fifth resistor. The base of the thirty-eighth transistor is connected to an external bias circuit to obtain a constant reference bias voltage.

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