A negative temperature drift bandgap reference circuit suitable for large dynamic range logarithmic amplifiers

Abstract

The present invention discloses a negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier. The circuit relates to the field of integrated circuit technology and includes a startup circuit for providing a startup current; and a reference core circuit comprising a plurality of transistors and a plurality of resistors, the transistors being electrically connected to the resistors. The reference core circuit is configured to provide a reference voltage with a negative temperature coefficient, biasing a rectifier, thereby ensuring an extremely low DC bias current temperature coefficient of the rectifier at temperatures between -55°C and 125°C. Compared to conventional zero temperature coefficient bandgap reference circuits, the present invention is more suitable for large dynamic range logarithmic amplifiers, enabling them to exhibit excellent temperature characteristics, including slope and logarithmic consistency error.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a negative temperature drift bandgap reference circuit suitable for a logarithmic amplifier with a large dynamic range. Background Art

[0002] The bandgap reference circuit is one of the most common circuit modules in integrated circuit chips. Almost all types of chips are inseparable from the bandgap reference circuit. The core idea of ​​the bandgap reference circuit is to offset the changes caused by temperature by reasonably configuring materials or circuits with positive temperature coefficients and negative temperature coefficients, thereby obtaining a constant that is basically independent of temperature.

[0003] In related technologies, for large dynamic range logarithmic amplifiers, the performance of indicators such as intercept, slope, dynamic range, and logarithmic consistency error under three temperatures is very important. The performance of the rectifier determines the slope and logarithmic consistency error. Under conditions of -55℃ to 125℃, the bias provided by the conventional zero-drift bandgap reference circuit will cause the temperature characteristics to deteriorate, thereby worsening the slope and logarithmic consistency error.

[0004] Therefore, there is an urgent need to improve the defects in the prior art. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier, comprising:

[0007] Starting circuit, the starting circuit is used to provide starting current;

[0008] The reference core circuit includes multiple transistors and multiple resistors. The transistors are electrically connected to the resistors. The reference core circuit is used to provide a reference voltage with a negative temperature coefficient to provide a bias for the rectifier, so that the DC bias current temperature coefficient of the rectifier is extremely low under the conditions of -55℃ to 125℃.

[0009] Beneficial effects of the present invention:

[0010] The present invention provides a negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier. Compared with a conventional zero temperature coefficient bandgap reference circuit, the present invention is more suitable for a large dynamic range logarithmic amplifier, so that the large dynamic range logarithmic amplifier has excellent temperature characteristics of slope and logarithmic consistency error.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the main structure of a large dynamic range logarithmic amplifier in the prior art;

[0013] Figure 2 It is a schematic diagram of a rectifier structure in the prior art;

[0014] Figure 3 This is a structural diagram of a negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier provided by an embodiment of the present invention;

[0015] Figure 4 The tail current source I provided by the embodiment of the present invention is TAIL A structural schematic diagram of a temperature curve simulation diagram. DETAILED DESCRIPTION

[0016] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0017] For related technologies, see Figure 1 , Figure 1 This diagram illustrates the main structure of a high-dynamic-range logarithmic amplifier in existing technology. It employs six limiting amplifiers connected in series, with a rectifier connected to the output of each limiting amplifier stage. The rectifier output currents are summed and converted to an output voltage via a transimpedance output stage. This structure achieves a linear relationship between the output voltage and the input power.

[0018] For large dynamic range logarithmic amplifiers, the intercept, slope, dynamic range, and logarithmic consistency error are very important under three temperatures. The performance of the rectifier determines the slope and logarithmic consistency error. The function of the rectifier is to detect the power information of the signal to be measured and output the corresponding output differential current. Figure 2 As shown, Figure 2 This is a schematic diagram of a rectifier structure in the prior art. NPN tubes Q1, Q2, and Q3 form a common-emitter differential pair structure. The bases of Q1 and Q2 are connected to the positive and negative terminals of the differential-mode input signal, respectively. The base of Q3 is connected to the common-mode input signal. The emitters of Q1, Q2, and Q3 are connected to the collector of Q4. The base of Q4 is connected to the bias voltage Vbias. Therefore, Vbias, Q4, and R1 form a tail current source I TAIL ,exist:

[0019]

[0020] The collector of Q1 generates current I1, the collector of Q2 generates current I2, and the collector of Q3 generates current I3. The output differential current ΔI is proportional to the differential input voltage V ID The relationship is:

[0021]

[0022] Among them, ΔI is the output differential current of the rectifier, which has an approximately exponential relationship with the differential input voltage; in the subsequent stage, the output differential current of all rectifiers is converted into output voltage through the transresistance output stage. It can be found that the tail current I TAIL Therefore, under the condition of -55℃~125℃, the bias provided by the conventional zero-drift bandgap reference circuit will cause I TAIL The temperature characteristics deteriorate, which in turn deteriorates the slope and logarithmic consistency error.

[0023] In order to overcome the disadvantage that the conventional zero-drift bandgap reference circuit may deteriorate the temperature characteristics of the slope and logarithmic consistency error of a large dynamic range logarithmic amplifier, the present invention provides a negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier, which provides a tail current bias for the rectifier so that the temperature coefficient of the tail current is extremely low under the conditions of -55°C to 125°C, thereby obtaining excellent temperature characteristics of the logarithmic slope and logarithmic consistency error.

[0024] See Figure 3 As shown, Figure 3 1 is a structural diagram of a negative temperature drift bandgap reference circuit for a large dynamic range logarithmic amplifier provided by an embodiment of the present invention. The negative temperature drift bandgap reference circuit for a large dynamic range logarithmic amplifier provided by the present invention comprises:

[0025] A starting circuit 10, the starting circuit 10 is used to provide a starting current I4;

[0026] The reference core circuit 20 includes a plurality of transistors and a plurality of resistors, wherein the transistors are electrically connected to the resistors. The reference core circuit 20 is used to provide a reference voltage V having a negative temperature coefficient. REF , providing bias for the rectifier, making the DC bias current temperature coefficient of the rectifier extremely low under the conditions of -55℃~125℃.

[0027] The startup circuit 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, a second transistor Q2 and a third transistor Q3;

[0028] A first end of the first resistor R1 is electrically connected to the enable signal end for receiving an enable signal Enable, a second end of the first resistor R1 is electrically connected to the first end of the second resistor R2; a second end of the second resistor R2 is electrically connected to the first end of the first transistor Q1; a second end of the first transistor Q1 is electrically connected to the first end of the second transistor Q2, and a third end of the first transistor Q1 is electrically connected to the first end of the second resistor R2; a second end of the second transistor Q2 is electrically connected to the ground end GND, and a third end of the second transistor Q2 is electrically connected to the first end of the second transistor Q2; a first end of the third resistor R3 is electrically connected to the ground end GND, a second end of the third resistor R3 is electrically connected to the second end of the second resistor R2 and the first end of the first transistor Q1, respectively, and a second end of the third resistor R3 is also electrically connected to the third end of the third transistor Q3; a first end of the fourth resistor R4 is electrically connected to the ground end GND, a second end of the fourth resistor R4 is electrically connected to the first end of the third transistor Q3, and a second end of the third transistor Q3 outputs a startup current I4.

[0029] The reference core circuit 20 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a first capacitor C1, a second capacitor C2, and a third capacitance difference C3; wherein,

[0030] A first end of a fifth resistor R5 is electrically connected to the second end of the third transistor Q3 for receiving a startup current I4. A second end of the fifth resistor R5 is electrically connected to the fixed voltage signal end VCC. A first end of a fourth transistor Q4 is electrically connected to the fixed voltage signal end. A second end of the fourth transistor Q4 is electrically connected to the first end of the sixth resistor R6, the first end of the seventh resistor R7, and the first end of the eighth resistor R8, respectively. A third end of the fourth transistor Q4 is electrically connected to the second end of the third transistor Q3.

[0031] a second end of the sixth resistor R6 is electrically connected to the first end of the fifth transistor Q5, a second end of the fifth transistor Q5 is electrically connected to the first end of the seventh transistor Q7, and a third end of the fifth transistor Q5 is electrically connected to the second end of the fifth transistor Q5 and the third end of the sixth transistor Q6, respectively; a first end of the sixth transistor Q6 is electrically connected to the second end of the seventh resistor R7, a second end of the sixth transistor Q6 is electrically connected to the first end of the eighth transistor Q8, a second end of the sixth transistor Q6 is electrically connected to the third end of the ninth transistor Q9, and a second end of the sixth transistor Q6 is also electrically connected to the first end of the ninth resistor R9;

[0032] a second end of the eighth resistor R8 electrically connected to the first end of the ninth transistor Q9, the second end of the eighth resistor R8 also electrically connected to the first end of the tenth transistor Q10, the second end of the ninth transistor Q9 electrically connected to the first end of the eleventh transistor Q11, the second end of the ninth transistor Q9 also electrically connected to the third end of the twelfth transistor Q12, the second end of the tenth transistor Q10 electrically connected to the first end of the eleventh transistor Q11, the second end of the tenth transistor Q10 also electrically connected to the third end of the twelfth transistor Q12, and the third end of the tenth transistor Q10 electrically connected to the second end of the third transistor Q3, for receiving the startup current I4;

[0033] a second end of the ninth resistor R9 electrically connected to the first end of the first capacitor C1, a second end of the first capacitor C1 electrically connected to the second end of the ninth transistor Q9, the second end of the tenth transistor Q10, one end of the eleventh transistor Q11, the third end of the twelfth transistor Q12, and the first end of the second capacitor C2, respectively; and a second end of the second capacitor C2 electrically connected to the ground terminal GND.

[0034] a second end of the seventh transistor Q7 electrically connected to the first end of the tenth resistor R10, a second end of the tenth resistor R10 electrically connected to the third end of the seventh transistor Q7, a second end of the tenth resistor R10 electrically connected to the third end of the eighth transistor Q8 and the third end of the eleventh transistor Q11, a second end of the seventh transistor Q7 electrically connected to the first end of the eleventh resistor R11, a second end of the eleventh resistor R11 electrically connected to the second end of the eighth transistor Q8, a second end of the seventh transistor Q7, a first end of the tenth resistor R10, and a first end of the eleventh resistor R11 electrically connected to the first end of the twelfth resistor R12, and a second end of the twelfth resistor R12 electrically connected to the ground terminal GND;

[0035] The second end of the tenth resistor R10 is also electrically connected to the first end of the thirteenth resistor R13, the second end of the thirteenth resistor R13 is electrically connected to the second end of the eleventh transistor Q11, the second end of the eleventh transistor Q11 is also electrically connected to the first end of the fourteenth resistor R14, and the second end of the fourteenth resistor R14 is electrically connected to the ground terminal GND;

[0036] The second end of the tenth resistor R10 is also electrically connected to the first end of the third capacitor C3, the second end of the third capacitor C3 is electrically connected to the ground terminal GND, and the first end of the third capacitor C3, the third end of the eleventh transistor Q11 and the second end of the twelfth transistor Q12 are electrically connected to the output end.

[0037] In an optional embodiment of the present invention, the fifth transistor Q5 and the sixth transistor Q6 form a current mirror.

[0038] In an optional embodiment of the present invention, the first transistor Q1 , the third transistor Q3 , the seventh transistor Q7 , the eighth transistor Q8 , the eleventh transistor Q11 , and the twelfth transistor Q12 are NPN transistors.

[0039] In an optional embodiment of the present invention, the fourth transistor Q4, the sixth transistor Q6, the ninth transistor Q9 and the tenth transistor Q10 are PNP transistors.

[0040] In an optional embodiment of the present invention, the fifth transistor Q5 is a diode-connected PNP transistor.

[0041] In an optional embodiment of the present invention, the second transistor Q2 is a diode-connected NPN transistor.

[0042] In an optional embodiment of the present invention, the driving process of the negative temperature drift bandgap reference circuit provided in this embodiment includes:

[0043] For the startup circuit 10, when the enable signal Enable is at a low level, no current flows through the first resistor R1, and the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all non-conductive, and the output startup current I4 is almost zero, which cannot drive the fourth transistor Q4. The fourth transistor Q4 is a power transistor, that is, the entire reference circuit cannot work normally.

[0044] When the enable signal Enable is at a high level, current flows through the first resistor R1, the third transistor Q3 is turned on, and the startup current I4 flows through the fifth resistor R5, causing the fifth resistor R5 to generate a huge voltage difference, causing the fourth transistor Q4, the tenth transistor Q10 and the eleventh transistor Q11 to be turned on, forming a circuit path. Next, the twelfth transistor Q12 is turned on, drawing current from the fixed voltage end to flow through the tenth resistor R10. As I R10 gradually increases, the seventh transistor Q7 is turned on, I CQ7 The current is copied to I by the current mirror formed by the fifth transistor Q5 and the sixth transistor Q6. CQ8 , the eighth transistor Q8 is turned on, and the entire reference circuit works normally. At this time, the output reference voltage V REF for:

[0045] V REF =V BEQ7 +(I R10 +I EQ7 +I R11 )R 12 (1);

[0046] Among them, V REF is the reference voltage, V BEQ7is the voltage difference between the base and emitter of the seventh transistor Q7, I R10 is the base current of the seventh transistor Q7 and the eighth transistor Q8, I EQ7 is the emitter current of the seventh transistor Q7, I R11 is the emitter current of the eighth transistor Q8, R 12 is the resistance value of the twelfth resistor R12;

[0047] Because I R10 Also serves as the base current of the seventh transistor Q7 and the eighth transistor Q8, and I CQ7 =I CQ8 , then I EQ7 =I EQ8 =I R11 ,in,

[0048]

[0049] In the above formula, n is the area of ​​the effective emitter region of the eighth transistor Q8, which is n times the area of ​​the effective emitter region of the seventh transistor Q7.

[0050] Substituting formula (2) into formula (1), we get formula (3), which is expressed as follows:

[0051]

[0052] By adjusting the ratio of the tenth resistor R10 and the twelfth resistor R12, a negative temperature coefficient output reference voltage V is further obtained on the conventional zero temperature coefficient reference voltage. REF At the same time, the existence of the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 can make V REF The temperature coefficient can be adjusted more accurately.

[0053] Furthermore, in V REF =V BIAS Under the condition of , formula (3) is substituted into the following formula (4) to obtain formula (5), which is expressed as follows:

[0054]

[0055]

[0056] When designing the circuit of this application, the seventh transistor Q7 adopts an NPN transistor. The temperature derivative of formula (5) is taken. By reasonably adjusting the temperature coefficient of the numerator to match the resistance temperature coefficient under the process, the rectifier tail current I with a low temperature coefficient can be obtained. TAIL See Figure 4 As shown, Figure 4 The tail current source I provided by the embodiment of the present invention isTAIL A structural diagram of a temperature curve simulation diagram, I TAIL At 25°C, the current is 65uA, and under the conditions of -55°C to 125°C, it only changes by 2.2uA, meeting the requirements of using a logarithmic amplifier with a large dynamic range.

[0057] In summary, the negative temperature drift bandgap reference circuit provided in this embodiment is more suitable for a large dynamic range logarithmic amplifier than a conventional zero temperature coefficient bandgap reference circuit, so that the large dynamic range logarithmic amplifier has excellent temperature characteristics of slope and logarithmic consistency error.

[0058] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0059] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0060] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier, characterized in that: include: A starting circuit, wherein the starting circuit is used to provide a starting current; A reference core circuit, comprising a plurality of transistors and a plurality of resistors, wherein the transistors are electrically connected to the resistors, and the reference core circuit is configured to provide a reference voltage having a negative temperature coefficient to bias the rectifier, such that the DC bias current temperature coefficient of the rectifier is extremely low at -55°C to 125°C; The reference core circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first capacitor, a second capacitor, and a third capacitance difference; wherein, a first end of the fifth resistor is electrically connected to the output end of the startup circuit for receiving a startup current, and a second end of the fifth resistor is electrically connected to the fixed voltage signal end; a first end of the fourth transistor is electrically connected to the fixed voltage signal end, a second end of the fourth transistor is electrically connected to the first end of the sixth resistor, the first end of the seventh resistor, and the first end of the eighth resistor, respectively; and a third end of the fourth transistor is electrically connected to the output end of the startup circuit; a second end of the sixth resistor being electrically connected to the first end of the fifth transistor, a second end of the fifth transistor being electrically connected to the first end of the seventh transistor, and a third end of the fifth transistor being electrically connected to the second end of the fifth transistor and the third end of the sixth transistor, respectively; a first end of the sixth transistor being electrically connected to the second end of the seventh resistor, a second end of the sixth transistor being electrically connected to the first end of the eighth transistor, a second end of the sixth transistor being electrically connected to the third end of the ninth transistor, and a second end of the sixth transistor being further electrically connected to the first end of the ninth resistor; a second end of the eighth resistor electrically connected to the first end of the ninth transistor, a second end of the eighth resistor further electrically connected to the first end of the tenth transistor, a second end of the ninth transistor electrically connected to the first end of the eleventh transistor, a second end of the ninth transistor further electrically connected to the third end of the twelfth transistor, a second end of the tenth transistor electrically connected to the first end of the eleventh transistor, a second end of the tenth transistor further electrically connected to the third end of the twelfth transistor, and a third end of the tenth transistor electrically connected to the output end of the startup circuit for receiving a startup current; a second end of the ninth resistor being electrically connected to the first end of the first capacitor, a second end of the first capacitor being electrically connected to the second end of the ninth transistor, the second end of the tenth transistor, one end of the eleventh transistor, the third end of the twelfth transistor, and the first end of the second capacitor, respectively, and a second end of the second capacitor being electrically connected to the ground; the second end of the seventh transistor is electrically connected to the first end of the tenth resistor, the second end of the tenth resistor is electrically connected to the third end of the seventh transistor, the second end of the tenth resistor is also electrically connected to the third end of the eighth transistor and the third end of the eleventh transistor, the second end of the seventh transistor is also electrically connected to the first end of the eleventh resistor, the second end of the eleventh resistor is electrically connected to the second end of the eighth transistor, the second end of the seventh transistor, the first end of the tenth resistor, and the first end of the eleventh resistor are all electrically connected to the first end of the twelfth resistor, and the second end of the twelfth resistor is electrically connected to the ground; The second end of the tenth resistor is also electrically connected to the first end of the thirteenth resistor, the second end of the thirteenth resistor is electrically connected to the second end of the eleventh transistor, the second end of the eleventh transistor is also electrically connected to the first end of the fourteenth resistor, and the second end of the fourteenth resistor is electrically connected to the ground; The second end of the tenth resistor is also electrically connected to the first end of the third capacitor, the second end of the third capacitor is electrically connected to the ground, and the first end of the third capacitor, the third end of the eleventh transistor and the second end of the twelfth transistor are electrically connected to the output end of the reference core circuit.

2. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 1, characterized in that: The startup circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first transistor, a second transistor and a third transistor; wherein, The first end of the first resistor is electrically connected to the enable signal end for receiving an enable signal, the second end of the first resistor is electrically connected to the first end of the second resistor; the second end of the second resistor is electrically connected to the first end of the first transistor; the second end of the first transistor is electrically connected to the first end of the second transistor, and the third end of the first transistor is electrically connected to the first end of the second resistor; the second end of the second transistor is electrically connected to the ground end, and the third end of the second transistor is electrically connected to the first end of the second transistor; the first end of the third resistor is electrically connected to the ground end, the second end of the third resistor is electrically connected to the second end of the second resistor and the first end of the first transistor respectively, and the second end of the third resistor is also electrically connected to the third end of the third transistor; the first end of the fourth resistor is electrically connected to the ground end, the second end of the fourth resistor is electrically connected to the first end of the third transistor, and the second end of the third transistor outputs a startup current.

3. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 2, characterized in that: The fifth transistor and the sixth transistor form a current mirror.

4. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 2, characterized in that: The first transistor, the third transistor, the seventh transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor are NPN transistors.

5. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 2, characterized in that: The fourth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are PNP transistors.

6. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 3, characterized in that: The fifth transistor is a diode-connected PNP transistor.

7. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 2, characterized in that: The second transistor is a diode-connected NPN transistor.

8. The negative temperature drift bandgap reference circuit suitable for a large dynamic range logarithmic amplifier according to claim 3, characterized in that: The expression of the reference voltage output by the output terminal is: ； in, is the reference voltage, is the voltage difference between the base and emitter of the seventh transistor, are the base currents of the seventh and eighth transistors, is the emitter current of the seventh transistor, is the emitter current of the eighth transistor, is the resistance of the twelfth resistor.

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