Error amplifier circuit

Abstract

The error amplifier circuit of the present invention includes: a plurality of error amplifiers that respectively obtain outputs of errors regarding two input signals; and a multiplexer that selects or deselects the outputs of the plurality of error amplifiers and outputs the output of the selected error amplifier as a control signal for a controlled circuit. In the multiplexer, for one of the plurality of error amplifiers whose output is not selected, a delay element provided on the input path of the one error amplifier is short-circuited to expand the frequency band of the error amplifier.

Description

Technical Field

[0001] The present invention relates to an error amplifier circuit including a plurality of error amplifiers. Background Art

[0002] Conventionally, feedback control has been widely used as a control method. For example, in a regulator that outputs a specific power supply voltage, feedback control is performed on its output voltage.

[0003] Here, when performing feedback control, an error amplifier that compares a set voltage with a detected voltage is mostly used. When there are a plurality of set values, one of the outputs of the plurality of error amplifiers is selected to feedback-control the regulator. This selection is performed using, for example, a multiplexer.

[0004] For the unselected error amplifiers, the outputs are not fed back, and thus, their outputs are fixed at the upper limit or the lower limit.

[0005] In addition, in feedback control using an error amplifier, a phase compensation circuit including a resistor and a capacitor is provided to prevent oscillation of the error amplifier.

[0006] Therefore, when one error amplifier changes from a non-selected state to a selected state, the output changes from a state fixed at the upper limit or the lower limit to a target state. However, because there is a phase compensation circuit, the change is slow, and it takes time to reach the target state. In addition, there is a problem of overshoot or undershoot during this period. Summary of the Invention

[0007] The error amplifier circuit of the present invention includes:

[0008] a plurality of error amplifiers that respectively obtain outputs of errors regarding two input signals; and

[0009] a multiplexer that selects or does not select the outputs of the plurality of error amplifiers and outputs the output of the selected error amplifier as a control signal for a controlled circuit; and

[0010] in the multiplexer, for one of the plurality of error amplifiers whose output is not selected, a delay element provided on the input path of the one error amplifier is short-circuited to widen the frequency band of the error amplifier.

[0011] According to the present invention, the time until reaching a target value can be reduced by a relatively simple circuit. Brief Description of the Drawings

[0012] Figure 1 It is a diagram showing the configuration of an error amplifier circuit according to an embodiment.

[0013] Figure 2AThis is a diagram showing the configuration of the error amplifiers EA (EA1 to EA3).

[0014] Figure 2B This is a diagram showing the detailed configuration of the three error amplifiers EA1 to EA3 and the multiplexer 12.

[0015] Figure 3 This is a diagram showing Figure 2B the operation timing diagram of the circuit. Detailed Embodiment

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the following embodiments do not limit the present invention, and configurations formed by selectively combining multiple examples are also included in the present invention.

[0017] "Overall Configuration"

[0018] Figure 1 This is a diagram showing the configuration of the error amplifier circuit according to the embodiment. The power supply Vin is connected to the ground via a pair of switches S1 and S2. The connection point of the switches S1 and S2 is connected to the output terminal 10 via the coil L, and the voltage Vout is output from here. In addition, one end of the capacitor C is connected to the output terminal, and the other end of the capacitor C is connected to the ground. The switches S1 and S2 are constituted by, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In addition, the output voltage Vout is used as a power supply for a load or the like.

[0019] The switches S1 and S2, the coil L, and the capacitor C constitute a DC-DC converter. By alternately turning on / off the switches S1 and S2 with an appropriate duty ratio, the desired output voltage Vout can be obtained at the output terminal 10. In addition, in the present embodiment, the DC-DC converter is a controlled circuit.

[0020] The voltage of the power supply Vin is Vin, which is input to the negative input terminal of the error amplifier EA1. This input signal is called the detection signal V1, and V1 corresponds to Vin. For the positive input terminal of the error amplifier EA1, the reference value Vref1 related to the reference voltage is input, and the output signal Vea1 corresponding to the difference between the two inputs is output.

[0021] The current Iin from the power supply Vin is input to the negative input terminal of the error amplifier EA2. The input signal is called the detection signal V2, and V2 corresponds to Iin. For the positive input terminal of the error amplifier EA2, the reference value Vref2 related to the reference current is input, and the output signal Vea2 corresponding to the difference between the two inputs is output.

[0022] The output voltage Vout is input to the negative input terminal of the error amplifier EA3. The input signal is called the detection signal V3, and V3 corresponds to Vout. For the positive input terminal of the error amplifier EA3, the reference value Vref3 related to the reference output voltage is input, and the output signal Vea3 corresponding to the difference between the two inputs is output.

[0023] In addition, as long as V1 corresponds to Vin, V2 corresponds to Iin, and V3 corresponds to Vout respectively, it can be V1 = Vin, V2 = Iin, V3 = Vout, or V1, V2, and V3 can be set to a fraction of Vin, Iin, and Vout respectively.

[0024] Moreover, the output signals Vea1 to Vea3 are input to the multiplexer 12, and one of them is selected. The signal selected by the multiplexer 12 is input to the modulator 14. The modulator 14 generates a PWM modulation signal according to the output signal Vea* selected from the output signals Vea1 to Vea3. In addition, the signal Vea* is called the control signal. The obtained PWM modulation signal is input to the pre-driver 16 and is converted into the switching signals of the switches S1 and S2 here. In addition, as the multiplexer 12, for example, an analog multiplexer using an analog switch or the like can be used, but as long as it can select signals, any configuration can be adopted.

[0025] In this way, the switching signals of the switches S1 and S2 are controlled according to the output signal Vea* selected from the output signals Vea1 to Vea3. Therefore, when the output signal Vea1 is selected, the switches are controlled so that the voltage Vin is consistent with the reference value Vref1. When the output signal Vea2 is selected, the switches are controlled so that the current Iin is consistent with the reference value Vref2. When the output signal Vea3 is selected, the switches are controlled so that the voltage Vout is consistent with the reference value Vref3.

[0026] In addition, which one the multiplexer 12 selects and how to turn on / off the switches S1 and S2 at what duty ratio are controlled by the controller 20. For example, the following methods can be adopted: select the one with the smallest value among the output signals Vea1 to Vea3. In addition, in this example, three error amplifiers EA1 to EA3 are provided, but as long as there are multiple error amplifiers, the number can be two or four or more.

[0027] "Short-circuit of the delay element"

[0028] Figure 2A It is a diagram showing the configuration of the error amplifier EA (EA1, EA2, EA3). Here, the error amplifier EA represents Figure 2BThe three error amplifiers EA1, EA2, and EA3 shown. In addition, Figure 2B In Figure 2B , three error amplifiers EA1, EA2, and EA3 are shown, but four or more may be provided to correspond to four or more detection signals.

[0029] In the error amplifier EA, the detection signals V (V1, V2, V3) in the control circuit are input to the negative input terminals of the internal amplifiers Amp (Amp1, Amp2, Amp3). In this example, V1 = Vin, V2 = Iin, and V3 = Vout.

[0030] Resistors R1 (R11, R12, R13) are arranged on the input path leading to the negative input terminal of the amplifier Amp. This resistor R1 limits the current in the input path to the negative input terminal, and thus functions as a delay element related to signal changes. In addition, capacitors C1 (C11, C12, C13) are connected in parallel to this resistor R1.

[0031] And switches SW1 (SW11, SW12, SW13) are provided in parallel with the resistor R1 and the capacitor C1. Therefore, by turning on the switch SW1, both ends of the resistor R1 and the capacitor C1 are short-circuited, and the detection signal V is directly input to the negative input terminal of the amplifier Amp without passing through them. In addition, a series connection of a capacitor C2 (C21, C22, C23) and a resistor R2 (R21, R22, R23) is arranged between the negative input terminal and the output terminal (negative feedback path) of the amplifier Amp.

[0032] An inverted selection signal SEL_Vea_b is supplied to the switch SW1 that shorts the resistor R1 and the capacitor C1, and the opening / closing of the switch SW1 is controlled by the inverted selection signal SEL_Vea_b. The inverted selection signal SEL_Vea_b is a signal obtained by inverting the selection signal SEL_Vea used to select the output signal Vea using an inverter INV (INV1 to INV3).

[0033] A reference value Vref (Vref1, Vref2, Vref3) is input to the positive input terminal of the error amplifier EA. Therefore, the error amplifier EA operates in such a way that the detection signal V coincides with the reference value Vref. That is, a feedback loop using the error amplifier EA is formed for the detection signal V. And the phase is compensated by the resistors R1, R2, the capacitors C1, C2 so that the feedback loop does not oscillate or the like.

[0034] Figure 2BThis is a diagram showing the configuration of three error amplifiers EA1 to EA3 and a multiplexer 12. Here, the three error amplifiers EA1 to EA3 have basically the same configuration. That is, the three error amplifiers EA1 to EA3 respectively receive three detection signals V1 to V3 and three selection signals SEL_Vea1 to SEL_Vea3, and respectively output three output signals Vea1 to Vea3.

[0035] The resistors R11, R21, the capacitors C11, C21, the switches SW11, SW21, and the inverter INV1 of the error amplifier EA1, the resistors R12, R22, the capacitors C12, C22, the switches SW12, SW22, and the inverter INV2 of the error amplifier EA2, and the resistors R13, R23, the capacitors C13, C23, the switches SW13, SW23, and the inverter INV3 of the error amplifier EA3 respectively correspond to each other.

[0036] The outputs of the respective error amplifiers EA1 to EA3, that is, the output signals Vea1 to Vea3, are output in the multiplexer 12 via three internal switches SW21, SW22, and SW23 respectively. The selection signals SEL_Vea1 to SEL_Vea3 from the controller 20 are supplied to the multiplexer 12, and any one of the three switches SW21, SW22, and SW23 is opened by the selection signals SEL_Vea1 to SEL_Vea3. Thus, any one of the output signals Vea1 to Vea3 from the corresponding error amplifiers EA1 to EA3 is selected and output as the output signal Vea*.

[0037] In addition, the selection signals SEL_Vea1 to SEL_Vea3 are supplied to the switches SW11, SW12, and SW13 of the respective error amplifiers EA1 to EA3 as inverted selection signals SEL_Vea1_b to SEL_Vea3_b via the inverters INV1 to INV3.

[0038] Therefore, when one of the three switches SW21, SW22, and SW23 is opened, the corresponding one of the three switches SW11, SW12, and SW13 is opened, and the other two switches among the switches SW11, SW12, and SW13 are closed. In this way, when one of the output signals Vea is selected, in the error amplifier EA for which the output signal is selected, the detection signal V supplied to the error amplifier EA is input via the resistor R1 and C1, and in the error amplifier EA for which the output signal Vea is not selected, the detection signal V is directly input to the amplifier Amp.

[0039] In this way, the frequency band of the error amplifiers EA1 to EA3 can be expanded by short-circuiting the phase compensation resistors R11, R12, and R13 in the unselected circuits, enabling a fast response.

[0040] Furthermore, when there is phase compensation RC inside each of the error amplifiers EA1 to EA3, if it is not selected, high-speed response can be achieved by also cutting off the RC.

[0041] In addition, in the unselected feedback loop, the input detection signal V is not feedback-controlled. Therefore, it is less likely to be consistent with Vref, and the output signal Vea of the error amplifier EA reaches near the upper or lower limit of the output range.

[0042] "Operation Explanation"

[0043] Figure 3 It is a timing diagram showing Figure 2B the operation of the circuit. It shows the situation where the output signal Vea2 of the control current Iin is selected (switch SW22 is opened) starting from the state where the output signal Vea3 of the control voltage Vout is selected (switch SW23 is opened).

[0044] In this example, with the output voltage Vout approximately fixed, the input current Iin rises significantly. Also, in this example, it is assumed that the reference values Vref1 to Vref3 are the same (Vref = Vref1 = Vref2 = Vref3).

[0045] The output signal Vea2 is not selected as the feedback loop, and the detection signal V2 is not consistent with the reference value Vref2. Based on this comparison result, the output signal Vea2 remains at the upper limit value.

[0046] On the other hand, since the output signal Vea3 is not selected, it is controlled to a specific value according to the voltage Vout. Figure 3 In, the voltage Vout does not change, and the error amplifier EA3 controls the output signal Vea3 so that the detection signal V3 is consistent with Vref3. Therefore, the output signal Vea3 also remains at an approximately fixed value.

[0047] In this state, the current Iin starts to rise. As a result, in the error amplifier EA2, the input detection signal V2 (corresponding to the current Iin) rises. Here, since the error amplifier EA2 is not selected for the feedback loop, the switch SW12 is open, and the output signal Vea2 drops rapidly in response to the change in the detection signal V2. On the other hand, the feedback loop functions such that the detection signal V3 is controlled to be consistent with Vref3. On the other hand, in the state where the current Iin increases, in order to prevent the voltage Vout from dropping and maintain it at a specific value, the output signal Vea3 rises. In addition, the increase in the current Iin causes the voltage Vin to drop.

[0048] Moreover, in the state where the output signal Vea2 of the error amplifier EA2 exceeds the output Vea3 of the error amplifier EA3, the signal SEL_Vea3 is disconnected and the signal SEL_Vea2 is connected, and the feedback loop to be selected is switched from the error amplifier EA3 to the error amplifier EA2.

[0049] As a result, the detection signal V2 is controlled to be consistent with the reference value Vref, and the output signal Vea2 is controlled to a value that maintains the current Iin at a specific value. Therefore, the current Iin drops after temporarily exceeding the specific value and is maintained at the specific value. In addition, the output signal Vea3 remains at the upper limit value due to being out of the loop.

[0050] Here, Figure 3 In the figure, the case where the switch SW12 is not provided is indicated by a dashed line. In this way, the output signal Vea2 of the unselected loop has a delay in its drop due to current limiting of the resistor R12, etc., and there is a delay time until it is controlled to a specific value. In addition, regarding the current Iin as the control object, its increase cannot be suppressed due to control delay, resulting in a large overshoot. Regarding the output signal Vea3, even when disconnected from the loop, its rise is delayed due to the delay caused by the resistor R13 and the influence of the overshoot of the current Iin.

[0051] In addition, the voltage Vin becomes low due to the influence of the overshoot of the current Iin, and it takes time to recover. The voltage Vout is maintained at a specific value during the period when the loop is selected.

[0052] In this way, when the switch SW23 connected to the error amplifier EA3 is turned on and the current Iin rises in the state where the loop of the output signal Vea3 is selected, if the switch SW12 of the error amplifier EA2 is turned off, the charging current of the capacitor C12 is determined by (V2 - Vref2) / R12. Therefore, when the resistance R12 is large, the capacitor C22 cannot be charged quickly. In this embodiment, in the error amplifier EA2 of the non-selected loop, the switch SW1 makes the resistance R12 in a short-circuit state. The resistance value of the switch SW12 is much smaller than the resistance value of the resistance R12. Therefore, the charging current of the capacitor C22 can be increased. Therefore, in the stage before switching the loop to be selected, it is possible to follow the change of the controlled object in the loop to be selected next, so that high-speed response can be achieved. And when the selection has been made, the switch SW11 is turned off and the resistance R11 becomes a non-short-circuit state. Thus, the usual control can be performed.

[0053] In addition, there is a method of adding a clamping circuit so that the output voltage of the error amplifier does not rise. For this purpose, an amplifier capable of generating an accurate clamping voltage is required. In this embodiment, as long as a selection signal is used to control the added switch, the configuration can be simplified.

[0054] [Description of symbols]

[0055] 10 Output terminal

[0056] 12 Multiplexer

[0057] 14 Modulator

[0058] 16 Predriver

[0059] 20 Controller.

Claims

1. An error amplifier circuit, comprising: a plurality of error amplifiers, each obtaining an output of an error regarding two input signals; and a multiplexer that selects or deselects the outputs of the plurality of error amplifiers and outputs the output of the selected error amplifier as a control signal for a controlled circuit; and in the multiplexer, for one of the plurality of error amplifiers whose output is not selected, a delay element provided on the input path of the one error amplifier is short-circuited to widen the frequency band of the error amplifier.

2. The error amplifier circuit according to claim 1, wherein the delay element is a resistor.

3. The error amplifier circuit according to claim 1, wherein one of the two input signals is a detection signal indicating the operation of the controlled circuit, and the other of the two input signals is a reference value regarding the detection signal.

4. The error amplifier circuit according to claim 1, wherein in the multiplexer, whether to short-circuit the delay element is controlled by a selection signal for selecting one of the plurality of error amplifiers.

5. The error amplifier circuit according to claim 4, wherein after the selection signal is delayed and the output of the error amplifier is selected, the delay element is changed from a short-circuited state to a non-short-circuited state.

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