Method of manufacturing a semiconductor structure, semiconductor structure and memory

Abstract

The application relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure preparation method, a semiconductor structure and a memory. The semiconductor structure preparation method comprises the following steps: providing a substrate; forming a stack layer on the substrate, the stack layer being provided with a plurality of active lines arranged at intervals, forming a plurality of transfer columns in the stack layer; forming an interval structure outside the transfer columns and forming an etching hole; etching a second composite mask layer and an active line of an initial semiconductor layer along the etching hole to form a plurality of discrete active region masks; and etching the substrate along the active region masks to form a plurality of discrete active regions. The application can effectively reduce the preparation difficulty of the active region, improve the LCDU of the active region, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] DRAM comprises multiple repeating memory cells disposed on a substrate, each memory cell including a capacitor and a transistor. An active layer is disposed on the substrate, comprising multiple active regions arranged in an array. Each active region includes a channel region, a source region connected to the source of the transistor, and a drain region connected to the drain of the transistor. The channel region is located between the source and drain regions. When a conduction signal is input to the gate of the transistor, the channel region conducts to the source and drain regions, completing the transistor conduction process.

[0004] However, as the feature size of DRAM continues to decrease, the fabrication difficulty of the active region increases, and its local critical dimension uniformity (LCDU) decreases, affecting the performance of DRAM. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory, which can effectively reduce the fabrication difficulty of the active region, improve the LCDU of the active region, and enhance the performance of the semiconductor structure.

[0006] To achieve the above objectives, in a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0007] Provide substrate;

[0008] A stacked layer is formed on the substrate, and multiple active lines are arranged at intervals in the stacked layer. Multiple transfer pillars are formed in the stacked layer.

[0009] A spacer structure is formed on the outside of the transfer column, and at least some of the adjacent spacer structures form the first etched hole;

[0010] Remove the transfer column to form a second etched hole in the spacer structure, the first etched hole and the second etched hole form an etched hole;

[0011] Active lines are etched along the etching holes to form multiple discrete active region masks;

[0012] The substrate is etched along the active region mask to form multiple discrete active regions.

[0013] In the above-described method for fabricating a semiconductor structure, optionally, the process of forming a spacer structure on the outside of the transfer pillar, wherein at least some of the adjacent spacer structures form a first etched hole, includes:

[0014] An initial spacing structure is formed, which covers the transfer columns. The initial spacing structure between adjacent transfer columns forms a void structure.

[0015] The initial spacer structures located at the top of the transfer column and at the bottom of the void structure are removed to form a spacer structure on the outside of the transfer column, wherein at least partially adjacent spacer structures form a first etched hole.

[0016] In the above-described method for fabricating a semiconductor structure, optionally, the at least partially adjacent spacer structures forming the first etched hole include:

[0017] At least four spacer structures are arranged around each other, and a first etched hole is formed in the area enclosed by the four spacer structures arranged around each other.

[0018] In the above-mentioned method for fabricating a semiconductor structure, optionally, the stacked layer includes an initial semiconductor layer, a second composite mask layer, an intermediate mask layer and a first composite mask layer stacked sequentially.

[0019] The process of forming a stacked layer on a substrate, wherein multiple active lines are arranged at intervals in the stacked layer, and forming multiple transfer pillars in the stacked layer includes:

[0020] An initial semiconductor layer, a second composite mask layer, an intermediate mask layer, and a first composite mask layer are sequentially formed on a substrate. The initial semiconductor layer includes multiple active lines arranged at intervals.

[0021] Two mask etching processes are performed on the first composite mask layer to form multiple initial pillars arranged in an array in the first composite mask layer;

[0022] The intermediate mask layer is etched along the initial pillar to form multiple transfer pillars arranged in an array within the intermediate mask layer.

[0023] In the above-described method for fabricating the semiconductor structure, optionally, performing two mask etching processes on the first composite mask layer includes:

[0024] A first initial mask layer is formed on the first composite mask layer;

[0025] The first composite mask layer is etched along the first initial mask layer to form a plurality of first initial pillars arranged in an array;

[0026] A sacrificial layer is formed on the first initial column;

[0027] A second initial mask layer is formed on the sacrificial layer;

[0028] The sacrificial layer is etched along the second initial mask layer to form multiple second initial pillars arranged in an array;

[0029] The first initial column and the second initial column form the initial column.

[0030] In the above-described method for fabricating the semiconductor structure, optionally, etching the intermediate mask layer along the initial pillar includes:

[0031] The intermediate mask layer is etched along the first initial pillar to form multiple first transfer pillars arranged in an array;

[0032] The intermediate mask layer is etched along the second initial pillar to form multiple second transfer pillars arranged in an array;

[0033] The first transfer column and the second transfer column form a transfer column.

[0034] In the above-mentioned method for fabricating a semiconductor structure, optionally, the plurality of transfer pillars include multiple rows of transfer pillars spaced apart along a first direction, wherein the plurality of first transfer pillars and the plurality of second transfer pillars are located in different rows of the multiple rows of transfer pillars;

[0035] Multiple rows of first transfer columns and multiple rows of second transfer columns are arranged alternately along the first direction. Multiple first transfer columns in the same row are set to correspond one-to-one with multiple second transfer columns in adjacent rows.

[0036] In the above-mentioned method for fabricating a semiconductor structure, optionally, the plurality of transfer pillars include multiple rows of transfer pillars spaced apart along a first direction, wherein the plurality of first transfer pillars and the plurality of second transfer pillars are located in the same row of the multiple rows of transfer pillars and are arranged alternately and spaced apart along a second direction.

[0037] The first transfer column in the same row is offset from the first transfer column in the adjacent row, and the second transfer column in the same row is offset from the second transfer column in the adjacent row; the first direction and the second direction intersect each other.

[0038] In the above-mentioned method for fabricating a semiconductor structure, optionally, the pitch between two adjacent rows of first transfer pillars is equal to the pitch between two adjacent rows of second transfer pillars, and both are the first pitch.

[0039] The pitch between two adjacent first transfer columns in the same row is equal to the pitch between two adjacent second transfer columns in the same row, and both are the second pitch.

[0040] The first pitch is greater than the second pitch.

[0041] In the above-mentioned method for fabricating semiconductor structures, optionally, in every three adjacent rows of transfer pillars, the pitch between the first transfer pillar in the first row and the first transfer pillar in the second row that are staggered from each other is the third pitch, and the pitch between the first transfer pillar in the second row and the first transfer pillar in the third row that are staggered from each other is the fourth pitch, and the third pitch is equal to the fourth pitch.

[0042] And / or,

[0043] In every three adjacent rows of transfer columns, the pitch between the second transfer column in the first row and the second transfer column in the second row that are offset from each other is the fifth pitch, and the pitch between the second transfer column in the second row and the second transfer column in the third row that are offset from each other is the sixth pitch. The fifth pitch is equal to the sixth pitch.

[0044] In the above-described method for fabricating a semiconductor structure, optionally, etching the active line along the etch hole includes:

[0045] The second composite mask layer and the active line are etched using the etching hole as a mask until a cut-off point is formed in the active line. The cut-off point is located at the orthogonal projection position of the etching hole on the active line.

[0046] The cutting points are etched to cut the active lines, thereby forming multiple discrete active region masks.

[0047] In the above-mentioned method for fabricating semiconductor structures, optionally, after forming the active regions, the method further includes: doping each active region to form a source region, a channel region, and a drain region in each active region, wherein the channel region is located between the source region and the drain region.

[0048] In the above-mentioned method for fabricating a semiconductor structure, optionally, the first composite mask layer includes a first hard mask layer and a first filler mask layer, wherein the first hard mask layer is located on the side of the first filler mask layer away from the substrate.

[0049] Forming a first initial mask layer on a first composite mask layer includes: forming a first initial mask layer on a first hard mask layer;

[0050] Etching the first composite mask layer along the first initial mask layer includes: etching the first hard mask layer along the first initial mask layer to form a plurality of first initial pillars arranged in an array in the first filled mask layer;

[0051] Forming a sacrificial layer on the first initial pillar includes: forming a sacrificial layer on the first filling mask layer, the sacrificial layer covering the first initial pillar.

[0052] In the above-mentioned method for fabricating a semiconductor structure, optionally, the first initial mask layer includes a first initial mask base layer and a first initial mask pattern layer, the first initial mask pattern layer is located on the side of the first initial mask base layer away from the substrate, and the first initial mask pattern layer has a plurality of first mask patterns that correspond one-to-one with a plurality of first initial pillars.

[0053] Forming a first initial mask layer on a first hard mask layer includes: forming a first initial mask base layer on the first hard mask layer, and forming a first initial mask pattern layer on the first initial mask base layer;

[0054] Etching the first hard mask layer along the first initial mask layer includes etching the first initial mask base layer and the first hard mask layer along a plurality of first mask patterns of the first initial mask pattern layer to form a plurality of first initial pillars arranged in an array in the first filling mask layer.

[0055] In the above-described method for fabricating a semiconductor structure, optionally, the second initial mask layer includes a second initial mask base layer and a second initial mask pattern layer. The second initial mask pattern layer is located on the side of the second initial mask base layer away from the substrate, and the second initial mask pattern layer has a plurality of second mask patterns that correspond one-to-one with a plurality of second initial pillars.

[0056] Forming a second initial mask layer on the sacrificial layer includes: forming a second initial mask base layer on the sacrificial layer, and forming a second initial mask pattern layer on the second initial mask base layer;

[0057] Etching the sacrificial layer along the second initial mask layer includes etching the second initial mask base layer and the sacrificial layer along a plurality of second mask patterns of the second initial mask pattern layer to form a plurality of second initial pillars arranged in an array in the first filling mask layer.

[0058] In the above-described method for fabricating a semiconductor structure, optionally, the second composite mask layer includes a second hard mask layer and a second filler mask layer, wherein the second hard mask layer is located on the side of the second filler mask layer closer to the substrate.

[0059] Etching the second composite mask layer along the etch hole includes: etching the second filling mask layer along the etch hole; and etching the second hard mask layer along the etch hole.

[0060] In the above-described method for fabricating a semiconductor structure, optionally, the substrate includes a substrate body and a transition layer, wherein the transition layer is located between the substrate body and the initial semiconductor layer; etching the substrate along the active region mask includes:

[0061] The transition layer and substrate are etched along the active region mask to form multiple discrete active regions.

[0062] In the above-mentioned method for fabricating semiconductor structures, optionally, the first hard mask layer, the second hard mask layer, and the sacrificial layer are made of the same material, and the etching selectivity ratios of the sacrificial layer and the first initial mask base layer are different.

[0063] In the above-described method for fabricating the semiconductor structure, optionally, the material of the first filling mask layer includes oxygen-rich silicon oxynitride; and / or, the material of the second filling mask layer includes silicon-rich silicon oxynitride.

[0064] Secondly, this application provides a semiconductor structure including an active region, which is prepared by the above-described preparation method.

[0065] Thirdly, this application provides a memory including the semiconductor structure described above.

[0066] The semiconductor structure fabrication method, semiconductor structure, and memory provided in this application reduce the size of the transfer pillars used to form the spacer structures and improve mask accuracy by performing two mask etching processes on the first composite mask layer of the substrate. By forming spacer structures outside the transfer pillars, adjacent spacer structures form a first etching hole, and a second etching hole is formed within the spacer structures. Active lines are etched using the first and second etching holes to form an active region mask. This effectively avoids light diffraction effects, which can lead to lower mask imaging clarity and affect the accuracy of the etching process. Therefore, using the above-mentioned active region mask to etch the substrate to form discrete active regions avoids the problem of poor etching accuracy caused by unclear mask imaging in related technologies. This application can effectively reduce the fabrication difficulty of active regions, improve the LCDU of active regions, and optimize the performance of semiconductor structures.

[0067] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0070] Figure 2 A schematic diagram of the structure of the semiconductor structure fabrication method provided in this application, showing the formation of a film layer on a substrate;

[0071] Figure 3 A schematic diagram of the structure for forming the first initial mask layer in the method for fabricating a semiconductor structure provided in this application embodiment;

[0072] Figure 4 A schematic diagram of the structure for forming the first initial pillar in the method for fabricating the semiconductor structure provided in this application embodiment;

[0073] Figure 5 This is a schematic diagram of the structure for forming a sacrificial layer in a method for fabricating a semiconductor structure provided in this application embodiment;

[0074] Figure 6 A schematic diagram of the structure for forming the second initial mask layer in the method for fabricating a semiconductor structure provided in this application embodiment;

[0075] Figure 7 A schematic diagram of the structure for forming the second initial pillar in the method for fabricating the semiconductor structure provided in this application embodiment;

[0076] Figure 8 A schematic diagram of the etching intermediate mask layer in the method for fabricating a semiconductor structure provided in this application embodiment;

[0077] Figure 9 This is a schematic diagram of the structure of the transfer column formed by the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0078] Figure 10 A schematic diagram of the formation of the initial spacer structure in the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0079] Figure 11 for Figure 10 Cross-sectional view at point A-A';

[0080] Figure 12 A schematic diagram of the formation of a spacer structure in a method for fabricating a semiconductor structure provided in an embodiment of this application;

[0081] Figure 13 for Figure 12 Cross-sectional view at point B-B';

[0082] Figure 14 A top view of the method for forming etched holes in the semiconductor structure fabrication method provided in this application embodiment;

[0083] Figure 15 for Figure 14 Cross-sectional view at point C-C';

[0084] Figure 16 A top view of the method for fabricating a semiconductor structure provided in this application, showing the etching of a second filling mask layer along an etch hole;

[0085] Figure 17 for Figure 16 Cross-sectional view at point D-D';

[0086] Figure 18 A top view of the method for fabricating a semiconductor structure according to an embodiment of this application, showing the etching of a second hard mask layer along an etch hole;

[0087] Figure 19 for Figure 18 Cross-sectional view at point E-E';

[0088] Figure 20 A top view of the active region mask formed in the method for fabricating a semiconductor structure provided in this application embodiment;

[0089] Figure 21 A cross-sectional view of the active region mask formed in the method for fabricating the semiconductor structure provided in this application embodiment;

[0090] Figure 22 A cross-sectional view of the active region formed in the method for fabricating the semiconductor structure provided in this application embodiment;

[0091] Figure 23 This is a schematic diagram of the active line structure of the semiconductor structure provided in the embodiments of this application;

[0092] Figure 24 A schematic diagram of the active region mask and transfer pillar of the semiconductor structure provided in the embodiments of this application;

[0093] Figure 25 A schematic diagram of an active region mask and transfer pillar for a semiconductor structure provided in an embodiment of this application;

[0094] Figure 26 This is a schematic diagram of another active region mask and transfer pillar structure of the semiconductor structure provided in this application embodiment.

[0095] Explanation of reference numerals in the attached figures:

[0096] 100. Substrate; 101. Substrate body; 102. Transition layer; 103. Active region; 200. Initial semiconductor layer; 201. Active line; 202. Active region mask; 300. Second composite mask layer; 301. Second hard mask layer; 302. Second filler mask layer; 400. Intermediate mask layer; 401. Transfer pillar; 401a. First transfer pillar; 401b. Second transfer pillar; 500. First composite mask layer; 501. First filler mask layer; 502. A hard mask layer; 503, initial pillar; 503a, first initial pillar; 503b, second initial pillar; 600, spacer structure; 601, first etched hole; 602, second etched hole; 603, initial spacer structure; 700, first initial mask layer; 700a, first initial mask base layer; 700b, first initial mask pattern layer; 701, second initial mask layer; 701a, second initial mask base layer; 701b, second initial mask pattern layer; 800, sacrificial layer. Detailed Implementation

[0097] The inventors of this application discovered during their research that the active layer of DRAM includes multiple discrete active regions arranged in an array. These active regions include a channel region, a source region connected to the source of a transistor, and a drain region connected to the drain of a transistor. The channel region is located between the source and drain regions. When a conduction signal is input to the gate of the transistor, the channel region conducts to the source and drain regions, completing the transistor's conduction process. In related technologies, based on the final profile of the active regions (AAcut final profile), a three-stage photolithography process (Litho-etch-litho-etch-litho-etch, photolithography-etch-photolithography-etch, abbreviated as LELELE) is typically used to form multiple discrete and arrayed active regions. During the three-stage photolithography process, three photomasks are formed. The pattern on the photomask is transferred to the substrate to be etched using an exposure process, forming the active regions in the substrate.

[0098] However, as the feature size of DRAM continues to shrink, especially in the fabrication of DRAM with feature sizes less than 15nm, the pattern size on the photomask is also decreasing. When light passes through the aforementioned pattern, diffraction occurs, leading to a reduction in the image clarity of the photomask pattern on the substrate to be etched. This not only reduces the precision of the etched pattern on the substrate and lowers the LCDU of the active region, but also increases the fabrication difficulty of the active region. When the LCDU of the active region decreases, the correspondence between the capacitors or transistors in the memory cells of the memory cells and the active region of the substrate is poor when fabricating DRAM memory cells on this substrate. This results in poor electrical connections between the substrate and capacitors, or between the substrate and transistors, which affects the structural stability and storage performance of the DRAM.

[0099] In view of this, the semiconductor structure fabrication method, semiconductor structure, and memory provided in this application, by performing two mask etching processes (Litho-etch-litho-etch, photolithography-etch-photolithography-etch, abbreviated as LELE) on the first composite mask layer of the substrate, can reduce the size of the transfer pillars used to form the spacer structure and improve the mask accuracy. By forming spacer structures outside the transfer pillars, adjacent spacer structures form a first etching hole, and a second etching hole is formed within the spacer structure. The active lines are etched using the first and second etching holes to form an active region mask. This can effectively avoid the diffraction effect of light, which leads to low image clarity of the mask and affects the accuracy of the etching process. Therefore, using the above-mentioned active region mask to etch the substrate to form discrete active regions can avoid the problem of poor etching accuracy caused by unclear image of the mask in related technologies. This application can effectively reduce the fabrication difficulty of the active region, improve the LCDU of the active region, and optimize the performance of the semiconductor structure.

[0100] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0101] In a first aspect, embodiments of this application provide a method for preparing a semiconductor structure. This method is mainly used to prepare a semiconductor structure, which includes an active region. The active region can be prepared by the above-described method.

[0102] Figure 22 A cross-sectional view of the active region formed in the method for fabricating the semiconductor structure provided in this application embodiment, referring to... Figure 22As shown, the semiconductor structure can be a substrate 100, with multiple active regions 103 in the substrate 100. The multiple active regions 103 are discretely arranged in an array within the substrate 100. An isolation structure (not shown in the figure) can be provided between adjacent active regions 103. The isolation structure can be made of an insulating material, including but not limited to silicon oxide, germanium oxide, and silicon-germanium oxide. The isolation structure can effectively block electron transmission between two adjacent active regions 103, reduce signal interference, and thus ensure the stability of the electrical signal within each active region 103, thereby improving the stability of the semiconductor structure.

[0103] Specifically, Figure 1 This is a schematic flowchart of the method for fabricating the semiconductor structure provided in the embodiments of this application, with reference to... Figure 1 As shown, the method for fabricating the semiconductor structure provided in this application includes:

[0104] S100: Providing a substrate. The substrate 100 provides a structural basis for subsequent structures and processes. The material of the substrate 100 may include any or more of silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator substrate, and germanium-on-insulator substrate. In this embodiment, at least a portion of the substrate 100 is a silicon substrate, and the silicon material may be single-crystal silicon. The substrate 100 can be prepared by chemical vapor deposition (CVD).

[0105] S200: A stacked layer is formed on the substrate, and multiple active lines are arranged at intervals in the stacked layer, and multiple transfer pillars are formed in the stacked layer.

[0106] The stacked layer includes an initial semiconductor layer, a second composite mask layer, an intermediate mask layer, and a first composite mask layer stacked sequentially. Based on this, S200 may include:

[0107] An initial semiconductor layer, a second composite mask layer, an intermediate mask layer, and a first composite mask layer are sequentially formed on a substrate. The initial semiconductor layer includes multiple active lines arranged at intervals.

[0108] Two mask etching processes are performed on the first composite mask layer to form multiple initial pillars arranged in an array in the first composite mask layer.

[0109] The intermediate mask layer is etched along the initial pillar to form multiple transfer pillars arranged in an array within the intermediate mask layer.

[0110] An initial semiconductor layer, a second composite mask layer, an intermediate mask layer, and a first composite mask layer are sequentially formed on a substrate. The initial semiconductor layer includes multiple active lines arranged at intervals. Figure 2 This is a schematic diagram of the structure of the semiconductor structure fabrication method provided in this application, showing the formation of a film layer on a substrate. Figure 11 for Figure 10 Cross-sectional view at point A-A'. (Refer to...) Figure 2 and Figure 11 As shown, the film layer on the substrate 100 may include sequentially formed stacked initial semiconductor layers 200 (e.g., ...). Figure 11 As shown), the first composite mask layer 500, the second composite mask layer 300, the intermediate mask layer 400, and the first composite mask layer 500 can all be fabricated by CVD. The initial semiconductor layer 200 has multiple active lines 201 spaced apart, and the material of the active lines 201 can be polycrystalline silicon.

[0111] Figure 23 This is a schematic diagram of the active line structure of the semiconductor structure provided in the embodiments of this application, combined with... Figure 23 As shown, the active lines 201 can be arranged at intervals on the substrate 100 along a preset direction. The preset direction can be any direction in a plane parallel to the substrate 100, and this embodiment does not limit it.

[0112] Specifically, two mask etching processes are performed on the first composite mask layer to form multiple initial pillars arranged in an array within the first composite mask layer. This application employs a two-stage mask etching process, which effectively improves etching accuracy while avoiding multiple mask etching steps, reducing the difficulty of semiconductor structure fabrication and improving fabrication efficiency. The two mask etching processes on the first composite mask layer 500 specifically include:

[0113] In this process, a first initial mask layer 700 is formed on the first composite mask layer 500. Figure 3 This is a schematic diagram of the structure for forming the first initial mask layer in the method for fabricating a semiconductor structure provided in this application embodiment, with reference to... Figure 2 and 3 As shown, the first composite mask layer 500 includes a first hard mask layer 502 and a first filler mask layer 501. The first hard mask layer 502 is located on the side of the first filler mask layer 501 away from the substrate 100. The first hard mask layer 502 can be a spin-on hard mask (SOH), and its material can be a silicon-rich compound. The material of the first filler mask layer 501 includes oxygen-rich silicon oxynitride (SiON).

[0114] Specifically, forming the first initial mask layer 700 on the first composite mask layer 500 includes forming the first initial mask layer 700 on the first hard mask layer 502.

[0115] The first initial mask layer 700 includes a first initial mask base layer 700a and a first initial mask pattern layer 700b. The first initial mask pattern layer 700b is located on the side of the first initial mask base layer 700a away from the substrate 100. The first initial mask pattern layer 700b has multiple first mask patterns that correspond one-to-one with multiple first initial pillars 503a. Each first mask pattern can be a pillar with the same shape and size as the first initial pillar 503a. There are multiple first mask patterns, and these multiple first mask patterns are arranged in an array on the first initial mask base layer 700a. Of course, the arrangement of the first mask patterns is not limited to this, as long as it is the same as the first initial pillars 503a to be formed subsequently.

[0116] Specifically, forming the first initial mask layer 700 on the first hard mask layer 502 may include: forming a first initial mask base layer 700a on the first hard mask layer 502, and forming a first initial mask pattern layer 700b on the first initial mask base layer 700a. Both the first initial mask base layer 700a and the first initial mask pattern layer 700b can be formed by CVD or atomic layer deposition (ALD). The material of the first initial mask base layer 700a can be silicon oxynitride, and the first initial mask pattern layer 700b can be a photoresist, the material of which can be a light-sensitive (e.g., ultraviolet light) organic compound, such as polyvinyl cinnamate.

[0117] In this process, the first composite mask layer 500 is etched along the first initial mask layer 700 to form a plurality of first initial pillars 503a arranged in an array. Figure 4 A schematic diagram of the structure for forming the first initial pillar in the method for fabricating the semiconductor structure provided in this application embodiment is shown below. Figure 4 As shown, the process of etching the first composite mask layer 500 along the first initial mask layer 700 may include etching the first hard mask layer 502 along the first initial mask layer 700. Specifically, the first initial mask base layer 700a and the first hard mask layer 502 are etched along a plurality of first mask patterns of the first initial mask pattern layer 700b to form a plurality of first initial pillars 503a arranged in an array on the first filling mask layer 501. Each of the formed first initial pillars 503a includes a first extension formed by the first hard mask layer 502 and a second extension formed by the first initial mask base layer 700a, the second extension being connected to the end of the first extension away from the substrate 100.

[0118] Among them, a sacrificial layer 800 is formed on the first initial column 503a. Figure 5 This is a schematic diagram of the structure for forming a sacrificial layer in the method for fabricating a semiconductor structure provided in this application embodiment, with reference to... Figure 5As shown, this step specifically includes: forming a sacrificial layer 800 on the first filling mask layer 501, the sacrificial layer 800 covering the first initial pillar 503a. The sacrificial layer 800 can be formed by CVD, and the material of the sacrificial layer 800 can be a spin-on hard mask (SOH). In this embodiment, the thickness of the sacrificial layer 800 is not limited, as long as it covers the top of the first initial pillar 503a.

[0119] After the first initial pillar 503a is formed, a sacrificial layer 800 is formed to cover it. This is mainly to perform the second mask etching process and to avoid the second mask etching process affecting the first initial pillar 503a formed by the first mask etching process.

[0120] A second initial mask layer 701 is formed on the sacrificial layer 800. Figure 6 This is a schematic diagram of the structure for forming the second initial mask layer in the method for fabricating a semiconductor structure provided in this application embodiment, with reference to... Figure 6 As shown, the second initial mask layer 701 includes a second initial mask base layer 701a and a second initial mask pattern layer 701b. The second initial mask pattern layer 701b is located on the side of the second initial mask base layer 701a away from the substrate 100. The second initial mask pattern layer 701b has a plurality of second mask patterns that correspond one-to-one with a plurality of second initial pillars 503b.

[0121] Similar to the first initial mask layer 700, the second mask pattern can be a column with the same shape as the second initial column 503b, and the column size of the second mask pattern is the same as that of the second initial column 503b. There are multiple second mask patterns, and these multiple second mask patterns are arranged in an array on the second initial mask base layer 701a. Of course, the arrangement of the second mask patterns is not limited to this, as long as it is the same as the second initial column 503b to be formed subsequently.

[0122] Specifically, forming the second initial mask layer 701 on the sacrificial layer 800 includes: forming a second initial mask base layer 701a on the sacrificial layer 800, and forming a second initial mask pattern layer 701b on the second initial mask base layer 701a. Both the second initial mask base layer 701a and the second initial mask pattern layer 701b can be formed by CVD or ALD. The material of the second initial mask base layer 701a can be the same as that of the first initial mask base layer 700a, i.e., silicon oxynitride. The second initial mask pattern layer 701b can be a photoresist, and its material can be a light-sensitive (e.g., ultraviolet light) organic compound. The material of the second initial mask pattern layer 701b can be the same as that of the first initial mask pattern layer 700b. This effectively reduces the types of materials used in semiconductor structure fabrication, reduces fabrication difficulty, and avoids the problem of high interlayer stress between layers of different materials, thereby preventing interlayer delamination and improving the stability of the semiconductor structure.

[0123] In this process, the sacrificial layer 800 is etched along the second initial mask layer 701 to form a plurality of second initial pillars 503b arranged in an array. The first initial pillars 503a and the second initial pillars 503b form the initial pillars 503. Specifically, Figure 7 A schematic diagram of the formation of the second initial pillar in the method for fabricating the semiconductor structure provided in this application embodiment is shown below. Figure 7 As shown, etching the sacrificial layer 800 along the second initial mask layer 701 includes etching the second initial mask base layer 701a and the sacrificial layer 800 along a plurality of second mask patterns of the second initial mask pattern layer 701b to form a plurality of second initial pillars 503b arranged in an array on the first filling mask layer 501.

[0124] Among them, combined Figure 1 and Figure 2 As shown, the second composite mask layer 300 includes a second hard mask layer 301 and a second filler mask layer 302. The second hard mask layer 301 is located on the side of the second filler mask layer 302 closest to the substrate 100. The second hard mask layer 301 can be a spin-on hard mask (SOH). The material of the second filler mask layer 302 includes silicon-rich silicon oxynitride (SiON).

[0125] It should be noted that, in combination Figures 4 to 7As shown, the first hard mask layer 502, the second hard mask layer 301, and the sacrificial layer 800 are made of the same material, but the etching selectivity of the sacrificial layer 800 and the first initial mask base layer 700a is different. During the etching of the sacrificial layer 800 along the second initial mask layer 701, the second extension formed by the top of the first initial pillar 503a and the first initial mask base layer 700a is made of silicon oxynitride. The material of the etched sacrificial layer 800 is SOH. Therefore, the sacrificial layer 800 and the first initial mask base layer 700a are made of different materials and have different etching selectivity for the photolithography process. During the etching of the second initial pillar 503b, the first initial pillar 503a is not affected. In this way, the first initial pillar 503a and the second initial pillar 503b can be transferred together onto the first hard mask layer 502.

[0126] Specifically, the intermediate mask layer is etched along the initial pillar to form multiple transfer pillars arranged in an array within the intermediate mask layer. Figure 8 This is a schematic diagram of the etching intermediate mask layer in the semiconductor structure fabrication method provided in this application embodiment. Figure 9 This is a schematic diagram of the structure of the transfer pillar formed by the method for fabricating the semiconductor structure provided in this application embodiment. (Refer to...) Figure 8 and Figure 9 As shown, etching the intermediate mask layer 400 along the initial pillar 503 includes: etching the intermediate mask layer 400 along the first initial pillar 503a to form a plurality of first transfer pillars 401a arranged in an array; etching the intermediate mask layer 400 along the second initial pillar 503b to form a plurality of second transfer pillars 401b arranged in an array; the first transfer pillars 401a and the second transfer pillars 401b form a transfer pillar 401.

[0127] It should be noted that the intermediate mask layer 400 can be an amorphous carbon layer (ACL). The steps of forming the first transfer pillar 401a and the second transfer pillar 401b can be completed simultaneously; or, the first transfer pillar 401a can be formed first, and then the second transfer pillar 401b can be formed; or, the second transfer pillar 401b can be formed first, and then the first transfer pillar 401a can be formed. In this embodiment, the order of formation of the first transfer pillar 401a and the second transfer pillar 401b is not limited. Figure 8 The top of the transfer column 401 shown is covered with a first filling mask layer 501, which can be removed by wet etching to form... Figure 9 The structure shown.

[0128] In the semiconductor structure fabrication method provided in this application embodiment, the transfer pillar 401 is formed by performing two mask etching processes on the first composite mask layer 500. This effectively reduces the size of the transfer pillar 401, ensuring that the size of the subsequently formed spacer structure 600 is small, thereby improving mask accuracy. Furthermore, compared to related technologies, the two mask etching processes effectively reduce the number of photomask operations, thereby reducing the impact of light diffraction on the exposure process and improving the accuracy of photolithography.

[0129] Specifically, the arrangement of the transfer columns 401 can be adjusted. The arrangement of the transfer columns 401 in this application can include the following two:

[0130] This is the first feasible arrangement of the transfer column 401. Figure 24 This is a schematic diagram of the active region mask and transfer pillar of the semiconductor structure provided in the embodiments of this application. Figure 25 A schematic diagram of an active region mask and transfer pillar for a semiconductor structure provided in this application embodiment is shown below. Figure 24 and Figure 25 As shown, the plurality of transfer columns 401 include multiple rows of transfer columns 401 arranged at intervals along a first direction, with multiple first transfer columns 401a and multiple second transfer columns 401b located in different rows of the multiple rows of transfer columns 401.

[0131] Multiple rows of first transfer columns 401a and multiple rows of second transfer columns 401b are arranged alternately along the first direction. Multiple first transfer columns 401a located in the same row are set in one-to-one correspondence with multiple second transfer columns 401b in adjacent rows.

[0132] It should be noted that the first direction can be Figure 24 and Figure 25 In the direction indicated by y, multiple first transfer columns 401a located in the same row are configured in a one-to-one correspondence with multiple second transfer columns 401b located in adjacent rows. That is, a first transfer column 401a located in the same row is configured in a corresponding manner with a second transfer column 401b located in an adjacent row.

[0133] Among them, the pitch between two adjacent rows of first transfer columns 401a is equal to the pitch between two adjacent rows of second transfer columns 401b, and both are the first pitch. Figure 25 The diagram only shows the pitch 'a' between two adjacent rows of the first transfer column 401a, and the pitch of two adjacent rows of the second transfer column 401b is the same. The numerical range of the first pitch 'a' can be 130-150 nm. In this embodiment, the first pitch 'a' can be 135 nm, 139.2 nm, 140 nm, or 145 nm.

[0134] The pitch between two adjacent first transfer columns 401a located in the same row can be Figure 25 The portion shown in b is the same as the pitch between two adjacent second transfer columns 401b in the same row. The pitch between two adjacent first transfer columns 401a in the same row is equal to the pitch between two adjacent second transfer columns 401b in the same row, and both are the second pitch. The numerical range of the second pitch b can be 60-100nm. In this embodiment, the second pitch b can be 80nm, 85nm, 89nm, 90nm, or 95nm. The first pitch a can be greater than the second pitch b, which ensures that there is enough space between two adjacent rows of first transfer columns 401a to accommodate one row of second transfer columns 401b. Similarly, it also ensures that there is enough space between two adjacent rows of second transfer columns 401b to accommodate one row of first transfer columns 401a.

[0135] Figure 26 This is a schematic diagram of another active region mask and transfer pillar structure of the semiconductor structure provided in this application embodiment, referring to... Figure 26 As shown, as a second feasible arrangement of the transfer columns 401, the multiple transfer columns 401 include multiple rows of transfer columns 401 arranged at intervals along a first direction, with multiple first transfer columns 401a and multiple second transfer columns 401b located in the same row of the multiple rows of transfer columns 401, and arranged alternately at intervals along a second direction.

[0136] The first transfer column 401a in the same row is staggered from the first transfer column 401a in the adjacent row, and the second transfer column 401b in the same row is staggered from the second transfer column 401b in the adjacent row; the first direction and the second direction intersect each other.

[0137] It should be noted that the first direction can be Figure 26 The y-direction shown in the figure is related to the direction of ... Figure 24 The y-direction is the same in both directions. The second direction can be... Figure 26 The x in the figure indicates the direction. In the two adjacent rows of transfer columns 401, a first transfer column 401a in the same row corresponds to a second transfer column 401b in the adjacent row.

[0138] For example, in every three adjacent rows of transfer columns 401, the pitch between the first transfer column 401a in the first row and the first transfer column 401a in the second row that are staggered from each other is the third pitch, and the pitch between the first transfer column 401a in the second row and the first transfer column 401a in the third row that are staggered from each other is the fourth pitch, and the third pitch is equal to the fourth pitch.

[0139] It should be noted that, Figure 26 In the four rows of transfer columns shown, the first three rows of transfer columns 401 along the -y direction are each three adjacent rows of transfer columns 401. The third pitch can be... Figure 26 The portion shown as c in the diagram can be the portion shown as d in the diagram. The numerical range of both the third pitch c and the fourth pitch d can be 90-120 nm. In this embodiment, the values ​​of the third pitch c and the fourth pitch d can be 95 nm, 100 nm, 106.2 nm, or 110 nm.

[0140] For example, in every three adjacent rows of transfer columns 401, the pitch between the second transfer column 401b in the first row and the second transfer column 401b in the second row that are staggered from each other is the fifth pitch, and the pitch between the second transfer column 401b in the second row and the second transfer column 401b in the third row that are staggered from each other is the sixth pitch, and the fifth pitch is equal to the sixth pitch.

[0141] It should be noted that the fifth pitch can be Figure 26 The portion shown in 'e', ​​the sixth pitch can be Figure 26 The portion shown in f is the fifth pitch e. ​​The numerical range of the fifth pitch e and the sixth pitch f can both be 90-120 nm. In this embodiment, the values ​​of the fifth pitch e and the sixth pitch f can be 95 nm, 100 nm, 106.2 nm, or 110 nm.

[0142] This improves the regularity of the arrangement of the transfer pillars 401, ensuring that the subsequently formed active regions 103 can also be regularly arranged in the substrate 100. It is possible that the third pitch c can be equal to or unequal to the fifth pitch e; this embodiment does not impose any limitations on this.

[0143] In this embodiment, "pitch" refers to the shortest straight-line distance between two structural components on the same side. For example, the pitch between two adjacent rows of first transfer columns 401a is the shortest straight-line distance between two adjacent rows of first transfer columns 401a. Furthermore, since the cross-section of the transfer column 401 in this embodiment is circular, to ensure the accuracy of the calculated pitch, Figure 25 and Figure 26 In this diagram, the exterior of each transfer column 401 is marked with a dashed frame, and the start and end points of the pitch dimension markings are also the same corresponding positions of the dashed frames on different transfer columns 401. For example, Figure 26 The starting point of the third pitch c annotation is the upper left corner of the dashed box of the first transfer column 401a in the first row, and the ending point of the third pitch c annotation is the upper left corner of the dashed box of the first transfer column 401a in the second row.

[0144] The above two arrangements of the transfer pillars 401 are only feasible implementation methods provided in this embodiment. They can increase the arrangement density of the transfer pillars 401, thereby improving the etching accuracy.

[0145] S300: A spacer structure is formed on the outside of the transfer column, and at least some of the spacer structures arranged adjacently form a first etched hole. Figure 10 This is a schematic diagram of the initial spacer structure formed by the method for fabricating a semiconductor structure provided in this application embodiment. Figure 12 A schematic diagram of the semiconductor structure fabrication method for forming a spacer structure provided in this application embodiment. Figure 13 for Figure 12 Cross-sectional view at point B-B'. (Refer to...) Figures 10 to 13 As shown, the spacer structure 600 can be formed by ALD (Alternating Deposition), and the material of the spacer structure 600 can be silicon oxide. The thickness of the spacer structure 600 can be adjusted by adjusting the thickness of the silicon oxide layer deposited during the ALD process. The greater the thickness of the silicon oxide deposition, the smaller the aperture of the first etched hole 601 formed between adjacent spacers 600.

[0146] Specifically, the process of forming spacer structures 600 on the outside of the transfer column 401, with at least some adjacent spacer structures 600 surrounding the first etched hole 601, includes:

[0147] An initial spacing structure 603 is formed, which covers the transfer column 401. The initial spacing structures 603 between adjacent transfer columns 401 form a void structure. (See reference...) Figure 10 and Figure 11 It should be noted that the gap structure formed between adjacent transfer columns 401 can be formed by the initial spacing structure 603 between every four adjacent transfer columns 401 arranged in a ring. Along Figure 11 In the x and y directions, the initial spacing structure 603 between two adjacent transfer columns 401 has a larger thickness and is connected. Furthermore, the height of the initial spacing structure 603 between two adjacent transfer columns 401 in the x and y directions is greater than the height of the spacing structure 603 at the bottom of the void structure. For example, the height of the initial spacing structure 603 located above the transfer column 401 is greater than the height of the initial spacing structure 603 located on the side wall of the transfer column 401.

[0148] Please refer to the appendix for further details. Figure 12 and Figure 13The initial spacer structures 603 located at the top of the transfer pillar 401 and at the bottom of the void structure are removed to form spacer structures 600 on the outside of the transfer pillar 401. At least partially adjacent spacer structures 600 surround the first etched hole 601. Specifically, the at least partially adjacent spacer structures 600 surrounding the first etched hole 601 includes at least four spacer structures 600 arranged around each other, with the first etched hole 601 formed in the area surrounded by the four adjacent spacer structures 600. Removing the initial spacer structures 603 located at the top of the transfer pillar 401 and at the bottom of the void structure exposes a second filling mask layer 302 at the bottom of the initial spacer structures 603. The cross-sectional shape of the spacer structures 600 can be circular, elliptical, or quasi-elliptical. When four adjacent spacer structures 600 are arranged around each other, the cross-sectional shape of the surrounded area can be similar to a rhombus. Of course, the surrounding area can be the first etched hole 601, or the first etched hole 601 can be located in the surrounding area, and the first etched hole 601 is formed by etching the spacer structure 600 located in the surrounding area.

[0149] S400: Remove the transfer pillar 401 to form a second etched hole in the spacer structure, where the first and second etched holes form an etched hole. The removal of the transfer pillar 401 can be accomplished by wet etching, thereby exposing a second filler mask layer 302 located within the spacer structure 600 and at the bottom of the transfer pillar 401.

[0150] It should be noted that, Figure 14 This is a top view of the method for forming etched holes in the semiconductor structure fabrication process provided in this application embodiment. Figure 15 for Figure 14 Cross-sectional view at C-C'. The structure for removing transfer column 401 can be referenced. Figure 14 and Figure 15 As shown. The step of removing the transfer column 401 can be performed after removing the initial spacer structure 603 located at the top of the transfer column 401 and before removing the initial spacer structure 603 located at the bottom of the gap structure, or it can be performed after the above two steps. In this embodiment, the order of the steps of removing the transfer column 401 is not limited.

[0151] S500: Etch active lines along the etch holes to form multiple discrete active region masks. This step specifically includes etching the second composite mask layer 300 and the active lines 201 along the etch holes.

[0152] The etching of the second composite mask layer 300 along the etch hole includes: etching the second filling mask layer 302 along the etch hole; and etching the second hard mask layer 301 along the etch hole.

[0153] Figure 16This is a top view of the method for fabricating a semiconductor structure according to an embodiment of the present application, showing the etching of a second filling mask layer along an etch hole. Figure 17 for Figure 16 The cross-sectional view at point D-D' is shown in the figure. Figure 16 and Figure 17 As shown, the second filling mask layer 302 is etched along the etch hole to expose the second hard mask layer 301 located at the bottom of the second filling mask layer 302 in the etch hole.

[0154] Figure 18 This is a top view of the method for fabricating a semiconductor structure according to an embodiment of the present application, showing the etching of a second hard mask layer along an etch hole. Figure 19 for Figure 18 Cross-sectional view at point E-E'. (Refer to...) Figure 18 and Figure 19 As shown, the second hard mask layer 301 is etched along the etch hole to expose the active line 201 located in the etch hole and covered by the second hard mask layer 301.

[0155] Figure 20 This is a top view of the active region mask formed in the method for fabricating a semiconductor structure according to an embodiment of this application. Figure 21 A cross-sectional view of the active region mask formed in the method for fabricating the semiconductor structure provided in this application embodiment. (Refer to...) Figure 20 and Figure 21 As shown, specifically, etching the active line 201 along the etched hole includes:

[0156] The second composite mask layer 300 and the active line 201 are etched using the etching holes as masks until a cut-off point is formed in the active line 201. The cut-off point is located at the orthogonal projection position of the etching holes on the active line 201. The cut-off point is etched to cut the active line 201, thereby forming multiple discrete active region masks 202. For example, a schematic diagram of the active region mask structure of the semiconductor structure provided in this application embodiment can be referred to... Figure 20 As shown, the active region mask 202 can be used as the etching mask structure for the subsequent active region 103.

[0157] After forming the active region mask 202, the process further includes: S600: etching the substrate along the active region mask to form multiple discrete active regions. Its structure can be referenced. Figure 22 As shown, the etching depth of the active region 103 can be adjusted according to actual needs. In this embodiment, the depth of the active region 103 is not limited.

[0158] After forming the active region 103, the process further includes: doping each active region 103 to form a source region, a channel region, and a drain region in each active region 103, with the channel region located between the source region and the drain region. The doping process can be achieved by doping the active region 103 with ions, which may include, but are not limited to, phosphorus. The doping concentration of the dopant ions can be adjusted as needed to form heavily doped regions with higher doping concentrations and lightly doped regions with lower doping concentrations to meet different electron transport functions.

[0159] Combination Figure 1 and Figure 2 As shown, in this embodiment, the substrate 100 includes a substrate body 101 and a transition layer 102, with the transition layer 102 located between the substrate body 101 and the initial semiconductor layer 200. Etching the substrate 100 along the active region mask 202 includes etching the transition layer 102 and the substrate body 101 along the active region mask 202 to form a plurality of discrete active regions 103. It should be noted that the substrate body 101 can be silicon, and the transition layer 102 can be silicon oxide. The silicon oxide transition layer 102 is disposed on the silicon substrate body 101, which can effectively reduce the stress on the substrate body 101 and ensure the stable setting of subsequent structural layers.

[0160] In this embodiment, a spacer structure 600 is formed on the outside of the transfer pillar 401. Adjacent spacer structures 600 form a first etching hole 601, and a second etching hole 602 is formed within the spacer structure 600. The active line 201 is etched using the first etching hole 601 and the second etching hole 602 to form an active region mask 202. This allows the spacer structure 600 to replace the third photolithography-etching process in related technologies, thereby avoiding the problem of low mask imaging clarity caused by light diffraction effects. Therefore, using the active region mask 202 to etch the substrate 100 to form discrete active regions 103 can avoid the problem of poor etching accuracy caused by unclear mask imaging in related technologies. This application can effectively reduce the fabrication difficulty of the active region 103, improve the LCDU of the active region 103, and optimize the performance of the semiconductor structure.

[0161] This application also provides a memory, including the semiconductor structure described above. The memory in this embodiment may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). This application embodiment uses a DRAM memory device as an example for description.

[0162] Transistors and capacitors can be formed on the substrate 100 of the aforementioned semiconductor structure. The gate of the transistor is connected to the word line (WL), the drain is connected to the bit line, and the source is connected to the capacitor. The source of the transistor can be electrically connected to the source region of the active region 103 of the semiconductor structure, and the drain of the transistor can be electrically connected to the drain region of the active region 103 of the semiconductor structure. The gate of the transistor can be correspondingly disposed with the channel region of the active region 103, and a gate insulating layer can be disposed between them.

[0163] During memory operation, voltage signals on the word lines control the switching on and off of transistors, thereby allowing data to be read from or written to capacitors via bit lines. Word lines are connected to the word line driver via a contact structure (Local interconnect contact, LICON) located in the peripheral area of ​​the memory cell, facilitating the input of voltage signals from the word line driver to the word lines.

[0164] Based on the high LCDU of the active region 103 in the aforementioned semiconductor structure, the electrical connection stability between the transistor and the active region 103 can be guaranteed, thereby optimizing the structural stability and storage performance of the memory. Other technical features of the memory in this embodiment are the same as those in the embodiments of the aforementioned semiconductor structure and its fabrication method, and achieve the same technical effects; therefore, they will not be described in detail here.

[0165] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0166] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A stack layer is formed on the substrate, and a plurality of active lines are arranged at intervals in the stack layer, and a plurality of transfer pillars are formed in the stack layer; A spacer structure is formed on the outside of the transfer column, and at least some of the spacer structures arranged adjacently form a first etched hole; Remove the transfer column to form a second etched hole in the spacer structure, the first etched hole and the second etched hole forming an etched hole; The active lines are etched along the etching holes to form multiple discrete active region masks; The substrate is etched along the active region mask to form a plurality of discrete active regions.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of forming a spacer structure on the outside of the transfer column, wherein at least some of the spacer structures are arranged adjacently to form a first etched hole, includes: An initial spacing structure is formed, which covers the transfer column, wherein the initial spacing structure between adjacent transfer columns forms a void structure; The initial spacer structures located at the top of the transfer column and at the bottom of the void structure are removed to form a spacer structure on the outside of the transfer column, wherein at least partially adjacent spacer structures form a first etched hole.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The spacer structures, arranged at least partially adjacent to each other, form the first etched hole, comprising: At least four of the spacer structures are arranged around each other, and the first etched hole is formed in the area enclosed by the four spacer structures arranged around each other.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The stack layer includes an initial semiconductor layer, a second composite mask layer, an intermediate mask layer, and a first composite mask layer stacked sequentially. The process of forming a stacked layer on the substrate, wherein multiple active lines are arranged at intervals in the stacked layer, and forming multiple transfer pillars in the stacked layer includes: The initial semiconductor layer, the second composite mask layer, the intermediate mask layer and the first composite mask layer are sequentially formed on the substrate, wherein the initial semiconductor layer includes a plurality of active lines arranged at intervals; Two mask etching processes are performed on the first composite mask layer to form multiple initial pillars arranged in an array in the first composite mask layer; The intermediate mask layer is etched along the initial pillar to form a plurality of the transfer pillars arranged in an array in the intermediate mask layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The two mask etching processes performed on the first composite mask layer include: A first initial mask layer is formed on the first composite mask layer; The first composite mask layer is etched along the first initial mask layer to form a plurality of first initial pillars arranged in an array; A sacrificial layer is formed on the first initial column; A second initial mask layer is formed on the sacrificial layer; The sacrificial layer is etched along the second initial mask layer to form a plurality of second initial pillars arranged in an array; The first initial column and the second initial column form the initial column.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, Etching the intermediate mask layer along the initial column includes: The intermediate mask layer is etched along the first initial pillar to form a plurality of first transfer pillars arranged in an array; The intermediate mask layer is etched along the second initial pillar to form a plurality of second transfer pillars arranged in an array; The first transfer column and the second transfer column form the transfer column.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The plurality of transfer columns include multiple rows of transfer columns spaced apart along a first direction, wherein the plurality of first transfer columns and the plurality of second transfer columns are respectively located in different rows of the multiple rows of transfer columns; Multiple rows of the first transfer columns and multiple rows of the second transfer columns are arranged alternately along the first direction. The multiple first transfer columns in the same row are arranged in a one-to-one correspondence with the multiple second transfer columns in the adjacent rows.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, The plurality of transfer columns include multiple rows of transfer columns spaced apart along a first direction, wherein the plurality of first transfer columns and the plurality of second transfer columns are located in the same row of the multiple rows of transfer columns and are arranged alternately and spaced apart along a second direction. The first transfer column in the same row is offset from the first transfer column in the adjacent row, and the second transfer column in the same row is offset from the second transfer column in the adjacent row. The first direction and the second direction intersect each other.

9. The method for preparing a semiconductor structure according to claim 7, characterized in that, The pitch between two adjacent rows of the first transfer column is equal to the pitch between two adjacent rows of the second transfer column, and both are the first pitch. The pitch between two adjacent first transfer columns in the same row is equal to the pitch between two adjacent second transfer columns in the same row, and both are the second pitch. The first pitch is greater than the second pitch.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, In every three adjacent rows of the transfer columns, the pitch between the first transfer column in the first row and the first transfer column in the second row that are staggered from each other is the third pitch, and the pitch between the first transfer column in the second row and the first transfer column in the third row that are staggered from each other is the fourth pitch, and the third pitch is equal to the fourth pitch. And / or, In every three adjacent rows of the transfer columns, the pitch between the second transfer column in the first row and the second transfer column in the second row that are staggered from each other is the fifth pitch, and the pitch between the second transfer column in the second row and the second transfer column in the third row that are staggered from each other is the sixth pitch, and the fifth pitch is equal to the sixth pitch.

11. The method for preparing a semiconductor structure according to claim 4, characterized in that, Etching the active line along the etching hole includes: The second composite mask layer and the active line are etched using the etching hole as a mask until a cut-off point is formed in the active line. The cut-off point is located at the orthogonal projection position of the etching hole on the active line. The cut points are etched to cut the active lines, thereby forming multiple discrete active region masks.

12. The method for preparing a semiconductor structure according to claim 4, characterized in that, After forming the active regions, the method further includes: doping each of the active regions to form a source region, a channel region, and a drain region in each of the active regions, wherein the channel region is located between the source region and the drain region.

13. The method for preparing a semiconductor structure according to any one of claims 6-8, characterized in that, The first composite mask layer includes a first hard mask layer and a first filler mask layer, wherein the first hard mask layer is located on the side of the first filler mask layer away from the substrate; Forming a first initial mask layer on the first composite mask layer includes: forming the first initial mask layer on the first hard mask layer; Etching the first composite mask layer along the first initial mask layer includes: etching the first hard mask layer along the first initial mask layer to form a plurality of first initial pillars arranged in an array in the first filled mask layer; Forming a sacrificial layer on the first initial pillar includes: forming the sacrificial layer on the first filling mask layer, the sacrificial layer covering the first initial pillar.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The first initial mask layer includes a first initial mask base layer and a first initial mask pattern layer. The first initial mask pattern layer is located on the side of the first initial mask base layer away from the substrate. The first initial mask pattern layer has a plurality of first mask patterns that correspond one-to-one with a plurality of the first initial pillars. Forming the first initial mask layer on the first hard mask layer includes: forming the first initial mask base layer on the first hard mask layer, and forming the first initial mask pattern layer on the first initial mask base layer; Etching the first hard mask layer along the first initial mask layer includes etching the first initial mask base layer and the first hard mask layer along a plurality of first mask patterns of the first initial mask pattern layer to form a plurality of first initial pillars arranged in an array in the first filled mask layer.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, The second initial mask layer includes a second initial mask base layer and a second initial mask pattern layer. The second initial mask pattern layer is located on the side of the second initial mask base layer away from the substrate. The second initial mask pattern layer has a plurality of second mask patterns that correspond one-to-one with a plurality of second initial pillars. Forming a second initial mask layer on the sacrificial layer includes: forming a second initial mask base layer on the sacrificial layer, and forming a second initial mask pattern layer on the second initial mask base layer; Etching the sacrificial layer along the second initial mask layer includes etching the second initial mask base layer and the sacrificial layer along a plurality of second mask patterns of the second initial mask pattern layer to form a plurality of second initial pillars arranged in an array in the first filling mask layer.

16. The method for preparing a semiconductor structure according to any one of claims 6-8, characterized in that, The second composite mask layer includes a second hard mask layer and a second filler mask layer, wherein the second hard mask layer is located on the side of the second filler mask layer closer to the substrate; Etching the second composite mask layer along the etching holes includes: etching the second filling mask layer along the etching holes; The second hard mask layer is etched along the etch hole.

17. The method for preparing a semiconductor structure according to claim 4, characterized in that, The substrate includes a substrate body and a transition layer, wherein the transition layer is located between the substrate body and the initial semiconductor layer; Etching the substrate along the active region mask includes: The transition layer and the substrate body are etched along the active region mask to form a plurality of discrete active regions.

18. A semiconductor structure, characterized in that, It includes an active region, which is prepared by the method for preparing a semiconductor structure according to any one of claims 1-17.

19. A memory, characterized in that, Includes the semiconductor structure described in claim 18.

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