A protection circuit for power supply of a configuration storage array of an anti-radiation SRAM type FPGA

Abstract

The application discloses a protection circuit for anti-radiation SRAM type FPGA configuration storage array power supply, which comprises a protection voltage generating circuit and a driving circuit. The protection circuit utilizes a branch composed of the protection voltage and a MOS transistor to provide an additional current path for the driving circuit. Under radiation conditions, when radiation ionization effect causes a device to generate surface defects and the threshold voltage of a PMOS power transistor is increased, the power supply protection circuit can protect the SRAM power supply voltage and prevent the SRAM from losing data due to power failure.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuits, and more particularly relates to a protection circuit design for power supply of an anti-radiation SRAM type FPGA configuration storage array. BACKGROUND

[0002] FPGA has the advantages of high integration and flexible function, and is widely used in industrial production. The SRAM type FPGA has the advantages of large capacity and high speed, and is mostly used in this type of FPGA in mainstream high-performance application scenarios.

[0003] With the continuous improvement of the integration of semiconductor devices, large-scale integrated circuits are increasingly applied to spacecraft. The ionization total dose effect of charged particles and electrons in the space radiation environment in integrated circuits seriously affects the reliability and on-orbit life of spacecraft.

[0004] High-energy radiation particles can cause various effects on integrated circuit devices, and even directly cause irreversible damage to integrated circuit devices. Ionization effect is a common radiation effect, and high-energy radiation particles can introduce defects in the oxide layer of MOS devices, increase the threshold voltage of PMOS devices, and affect circuit performance. SRAM memory is a volatile memory, and when the threshold voltage of the PMOS power tube for SRAM power supply increases due to radiation ionization effect, it is easy to cause the loss of data stored in SRAM. SUMMARY

[0005] The purpose of the present application is to provide a protection circuit for power supply of an anti-radiation SRAM type FPGA configuration storage array, which can improve the power supply voltage of the SRAM array under radiation conditions, so as to prevent the loss of data stored in the SRAM.

[0006] The purpose of the present application is achieved by the following technical solutions:

[0007] A protection circuit for power supply of an anti-radiation SRAM type FPGA configuration storage array, comprising: a protection voltage generating circuit and a driving circuit;

[0008] The protection voltage generating circuit generates a protection voltage and outputs it to the driving circuit;

[0009] The driving circuit receives the protection voltage output by the protection voltage generating circuit, uses the protection voltage to open the current compensation path in the driving circuit, and outputs a power supply voltage to a plurality of SRAMs in the SRAM array, thereby improving the power supply voltage of the SRAM array.

[0010] Preferably, the protection voltage generating circuit generates the protection voltage by using the resistance voltage division principle and outputs the protection voltage to the driving circuit.

[0011] Preferably, the protection voltage generating circuit comprises a transistor PM1, a transistor NM1, a resistor R1, a resistor R2, a resistor R3 and a switch S1.

[0012] One end of the resistor R3 is grounded, the other end of the resistor R3 is connected to one end of the resistor R2 and the drain of the transistor NM1; the other end of the resistor R3 serves as an output terminal to output the protection voltage to the driving circuit;

[0013] The other end of the resistor R2 is connected to one end of the resistor R1 and one end of the switch S1.

[0014] The other end of the resistor R1 is connected to the other end of the switch S1 and the source of the transistor PM1; the gate of the transistor PM1 serves as an input terminal to receive an externally input start voltage.

[0015] The source of the transistor PM1 is connected to an external power supply VDD.

[0016] The gate of the transistor NM1 serves as an input terminal to receive an externally input start voltage, and the source of the transistor NM1 is grounded.

[0017] The switch S1 is connected in parallel with the resistor R1 to realize the function of adjusting the level of the output protection voltage.

[0018] Preferably, the transistor PM1 is a PMOS transistor, and the transistor NM1 is an NMOS transistor.

[0019] Preferably, the transistor PM1 and the transistor NM1 are controlled by the externally input start voltage and serve as switches of the protection voltage generating circuit.

[0020] Preferably, the switch S1 is used to adjust the level of the protection voltage; when the supply voltage level output by the SRAM is too low, the switch S1 is closed to increase the level of the protection voltage; otherwise, the switch S1 remains in an off state.

[0021] Preferably, the driving circuit comprises a transistor PM2, a transistor PM3, a transistor NM2 and a transistor NM3.

[0022] The gate of the transistor PM2 receives supply input of a secondary power supply VG; the source of the transistor PM2 receives supply of an external power supply VDD; the source of the transistor PM2 and the source of the transistor PM3 are connected to the external power supply VDD; the gate of the transistor PM3 is grounded.

[0023] The drain of the transistor PM3 is connected with the drain of the transistor NM3, the gate of the transistor NM3 receives the protection voltage outputted by the protection voltage generating circuit, the source of the transistor NM3 is connected with the drain of the transistor PM2, the drain of the transistor NM2 and the gate of the transistor NM2; the source of the transistor NM3 is an output terminal, and outputs the power supply voltage to the external SRAM array.

[0024] The source of the transistor NM2 is connected with the ground.

[0025] Preferably, the transistor PM2 and the transistor PM3 are PMOS transistors, and the transistor NM2 and the transistor NM3 are NMOS transistors.

[0026] Preferably, the transistor NM3 and the transistor PM3 are current compensation paths.

[0027] Compared with the prior art, the present application has the following beneficial effects:

[0028] The present application can provide additional power supply paths for the SRAM while ensuring the original power supply capability of the SRAM, thereby improving the power supply reliability of the SRAM under radiation conditions and laying a foundation for ensuring the data reliability of the FPGA under radiation conditions. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a principle block diagram of a protection circuit for the power supply of the configuration storage array of the anti-radiation SRAM type FPGA according to the present application;

[0030] Figure 2 is a schematic diagram of a specific implementation of the protection voltage generating circuit according to the present application;

[0031] Figure 3 is a schematic diagram of a specific implementation of the driving circuit according to the present application;

[0032] Figure 4 is a comparison diagram of the SRAM power supply voltage under the conditions of enabling / disabling the protection circuit. DETAILED DESCRIPTION

[0033] The specific implementation of the present application will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present application. It should be particularly noted that in the following description, when the detailed description of the known functions and designs may obscure the main content of the present application, these descriptions will be omitted here.

[0034] Under radiation conditions, high-energy radiation particles can cause surface defects in MOS devices, forming positive charges in the MOS oxide layer and raising the threshold voltage of PMOS devices. This increases the threshold voltage of the driver circuit's power transistors, making it difficult for the transistors to turn on, which can directly reduce the SRAM supply voltage and lead to SRAM data loss due to power failure.

[0035] To preserve SRAM data under radiation conditions, the present invention provides a protection circuit for powering a radiation-resistant SRAM FPGA configuration memory array. This circuit connects protected voltage-controlled transistors PM3 and NM3 in parallel with the amplifier powering the SRAM memory, creating a compensation current path. When radiation causes the threshold voltage of the PMOS power transistor to increase, affecting circuit performance, the protection circuit compensates for supply voltage fluctuations caused by this threshold change, preventing data loss during SRAM power failure.

[0036] Specifically, such as Figure 1 As shown, the present invention proposes a protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array, comprising: a protection voltage generating circuit and a driving circuit;

[0037] The protection voltage generating circuit generates a stable protection voltage and outputs it to the driving circuit;

[0038] The driver circuit receives the high-level protection voltage output by the protection voltage generation circuit, uses the protection voltage to activate the current compensation path (composed of NM3 and PM3) in the driver circuit, and outputs the supply voltage to multiple SRAMs in the SRAM array; thereby increasing the supply voltage of the SRAM array, improving the output capability of the driver circuit, and protecting the data security of the SRAM array.

[0039] The protection voltage generating circuit uses the principle of resistor voltage division to generate a stable protection voltage and output it to the driving circuit.

[0040] like Figure 2 As shown, the protection voltage generating circuit includes: a transistor PM1, a transistor NM1, a resistor R1, a resistor R2, a resistor R3 and a switch S1.

[0041] The transistor PM1 is a PMOS transistor, and the transistor NM1 is an NMOS transistor. The MOS transistor PM1 is connected in series with a plurality of resistors to form a voltage divider circuit to generate a required protection voltage.

[0042] The transistor PM1 and the transistor NM1 are controlled by the external input start voltage and serve as switches of the protection voltage generating circuit;

[0043] The switch S1 is used for adjusting the level of the protection voltage. When the supply voltage level output by the SRAM is too low, the switch S1 is closed to increase the level of the protection voltage output by the protection voltage generating circuit, so that greater driving capability is obtained. Otherwise, the switch S1 remains in the off state.

[0044] The transistor PM1 is connected in series with the resistor R1, the resistor R2 and the resistor R3, and outputs the protection voltage to the driving circuit. The switch S1 is connected in parallel with the resistor R1, and realizes the level adjustment function of the output protection voltage.

[0045] One end of the resistor R3 is connected to the ground, and the other end of the resistor R3 is connected to one end of the resistor R2 and the drain of the transistor NM1. The other end of the resistor R3 is used as an output end, and outputs the protection voltage to the driving circuit.

[0046] The other end of the resistor R2 is connected to one end of the resistor R1 and one end of the switch S1.

[0047] The other end of the resistor R1 is connected to the other end of the switch S1 and the source of the transistor PM1. The gate of the transistor PM1 is used as an input end, and receives the externally input start voltage.

[0048] The source of the transistor PM1 is connected to the external power supply VDD.

[0049] The gate of the transistor NM1 is used as an input end, and receives the externally input start voltage. The source of the transistor NM1 is connected to the ground.

[0050] The power transistor NM3 controlled by the protection voltage is connected in parallel with the power transistor PM2, and provides an additional current compensation path for the SRAM.

[0051] As shown in Figure 3 , the driving circuit comprises the transistor PM2, the transistor PM3, the transistor NM2 and the transistor NM3.

[0052] The transistor PM2 and the transistor PM3 are PMOS transistors, and the transistor NM2 and the transistor NM3 are NMOS transistors. The transistor PM2 and the transistor NM2 are connected in series as a common-source amplifier, and cooperate with the current compensation path to output the supply voltage for the SRAM array.

[0053] The protection voltage generating circuit outputs the high-level protection voltage to the gate of the transistor NM3, and provides an additional current path for the power supply of the SRAM. When the threshold voltage of the PMOS power transistor PM2 is increased due to particle radiation, the power transistor PM2 is prevented from being difficult to turn on, so that the data loss caused by power failure of the SRAM is prevented.

[0054] The transistor PM2 and the transistor NM2 are connected in series as the driving circuit for the power supply of the SRAM array.

[0055] The transistor PM3 and the transistor NM3 are connected in series and are connected in parallel with the transistor PM2; the transistor NM3 and the transistor PM3 serve as a current compensation path.

[0056] The gate of the transistor PM2 receives a supply input of a secondary power supply VG; the source of the transistor PM2 receives a supply of an external power supply VDD; the source of the transistor PM2 and the source of the transistor PM3 are connected to the external power supply VDD; the gate of the transistor PM3 is connected to the ground processing;

[0057] The drain of the transistor PM3 is connected to the drain of the transistor NM3; the gate of the transistor NM3 receives a protection voltage output by a protection voltage generating circuit; the source of the transistor NM3 is connected to the drain of the transistor PM2, the drain of the transistor NM2 and the gate of the transistor NM2; the source of the transistor NM3 serves as an output terminal and outputs a supply voltage to an external SRAM array;

[0058] The source of the transistor NM2 is connected to the ground processing.

[0059] In the present application, the output voltage fluctuation is inhibited, and specifically:

[0060] The protection voltage generating circuit outputs a high-level protection voltage, which opens the NMOS transistor NM3 in the driving circuit to provide a parallel current path for the SRAM supply, and the current path keeps an open state. The key of the driving circuit supply is the power transistor PM2. Without the parallel current path, the current I flowing through the transistor PM2 in the driving circuit is PM2 :

[0061]

[0062] Wherein, r OPM2 is the output resistance of the transistor PM2. k is a parameter related to the MOS tube process, and the value is related to the specific process adopted and the width-length ratio of the transistor. Under general application conditions, k < 10000 μA / V 2 ; V GS is the voltage between the gate and the source of the transistor PM2, V th is the threshold voltage of the transistor PM2, V DD is the voltage of the external power supply VDD, V SRAM is the supply voltage output to the SRAM array.

[0063] The ionization effect caused by radiation can cause the absolute value |V th of the threshold voltage of the transistor PM2 to rise. At this time, in order to maintain the SRAM working current, the supply voltage V SRAM will be significantly reduced. In order to prevent the SRAM from losing data due to power failure, after adding the parallel current path controlled by the protection voltage, the total current I 支路总 is:

[0064]

[0065] wherein, r PM3 and r NM3 respectively represent the equivalent resistance of the transistor PM3 and the transistor NM3, from the formula, it can be seen that after the bypass current is increased, the threshold voltage of the power transistor PM2 is increased, the SRAM supply voltage V SRAM of the working current is maintained, and the amplitude of the decrease is inhibited.

[0066] Working process: the protection voltage generating circuit works in the circuit power-on process, outputs the protection voltage to open the branch of the driving circuit, and the protection voltage keeps open. Under the radiation condition, the PMOS power transistor of the driving circuit has obvious threshold rise due to the radiation ionization effect, which causes the SRAM supply voltage to decrease, and the current compensation path controlled by the protection voltage can compensate the decrease of the SRAM supply voltage caused by the threshold voltage increase of the power transistor PM2, thereby avoiding the data power loss of the SRAM.

[0067] Embodiment

[0068] Figure 1 A protection circuit principle block diagram for the anti-radiation SRAM type FPGA configuration storage array power supply provided by the embodiment of the application is shown in the figure, which mainly comprises: a protection voltage generating circuit and a driving circuit, and the connection relationship is as follows: the protection voltage generating circuit outputs the protection voltage, the driving circuit is controlled by the protection voltage, the protection voltage keeps high level, and the power supply branch of the driving circuit keeps open, thereby protecting the SRAM supply voltage when the power transistor of the driving circuit is affected by radiation. Figure 1

[0069] As shown in the figure, the main body of the protection voltage generating circuit is a simple common source amplifier, which comprises a transistor PM1 and a transistor NM1, voltage dividing resistors R1, R2 and R3, and a switch S1. Figure 2

[0070] The transistor PM1 is a PMOS transistor, and the transistor NM1 is an NMOS transistor; wherein the PM1 and the NM1 are responsible for the start and shutdown of the protection voltage generating circuit under the control of the start voltage. The voltage dividing resistors R1, R2 and R3 output the required protection voltage level after the circuit is turned on. The switch S1 can adjust the level of the protection voltage as needed.

[0071] As shown in the figure, the driving circuit comprises transistors PM2, PM3 and NM2, and NM3. The transistors PM2 and PM3 are PMOS transistors. The PM2 and the NM2 are connected in series as an amplifier for the SRAM power supply, the PM3 and the NM3 are connected in parallel with the PM2, and a branch current is provided. Figure 3

[0072] As​​​Figure 4 As shown in the figure, the maximum variation of threshold voltage under the selected radiation condition, the fluctuation of supply voltage under the condition of opening / closing of the protection circuit. The black dotted line part in the figure is the variation of SRAM supply voltage when the threshold of power tube varies under the condition of not opening the protection circuit. At 50us, the threshold voltage of the supply power tube rises due to the ionization effect of radiation, at this time the SRAM supply voltage decreases by about 600mV, to about 0.5V. The red solid line part in the figure is the variation of SRAM supply voltage under the condition of opening the protection circuit, from the figure, it can be seen that according to the application, the protection circuit is opened, at 50us, the threshold voltage of the supply power tube rises due to the ionization effect of radiation, the SRAM supply voltage decreases from 1.15V to 0.8V. The protection circuit can effectively suppress the decrease of SRAM supply voltage caused by radiation, and protect the SRAM data.

[0073] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application, any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application, therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not deviate from the technical solutions of the present application, belongs to the protection scope of the present application. In the case of no conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0074] The contents not described in detail in the specification of the present application are the known technology of the person skilled in the art.

Claims

1. A protection circuit for powering a radiation-resistant SRAM-type FPGA configuration memory array, characterized by: include: Protect voltage generating circuit and driving circuit; The protection voltage generating circuit generates a protection voltage and outputs it to the driving circuit; The driving circuit receives the protection voltage output by the protection voltage generating circuit, uses the protection voltage to open a current compensation path in the driving circuit, and outputs a power supply voltage to multiple SRAMs in the SRAM array, thereby increasing the power supply voltage of the SRAM array; The driving circuit includes: a transistor PM2, a transistor PM3, a transistor NM2 and a transistor NM3; The gate of the transistor PM2 receives a power supply input from a secondary power supply VG; the source of the transistor PM2 receives power from an external power supply VDD; the source of the transistor PM2 and the source of the transistor PM3 are connected to the external power supply VDD; the gate of the transistor PM3 is grounded; The drain of transistor PM3 is connected to the drain of transistor NM3, the gate of transistor NM3 receives the protection voltage output by the protection voltage generating circuit, the source of transistor NM3 is connected to the drain of transistor PM2, the drain of transistor NM2 and the gate of transistor NM2; the source of transistor NM3 serves as an output terminal, outputting the supply voltage to the external SRAM array; The source of transistor NM2 is grounded.

2. A protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to claim 1, characterized in that: The protection voltage generating circuit utilizes the principle of resistor voltage division to generate protection voltage and output it to the driving circuit.

3. The protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to claim 1, characterized in that: The protection voltage generating circuit includes: a transistor PM1, a transistor NM1, a resistor R1, a resistor R2, a resistor R3 and a switch S1; One end of the resistor R3 is grounded, and the other end of the resistor R3 is connected to one end of the resistor R2 and the drain of the transistor NM1; the other end of the resistor R3 serves as an output end, outputting a protection voltage to the driving circuit; The other end of the resistor R2 is connected to one end of the resistor R1 and one end of the switch S1; The other end of the resistor R1 is connected to the other end of the switch S1 and the source of the transistor PM1; the gate of the transistor PM1 serves as an input end to receive an external input start voltage; The source of transistor PM1 is connected to the external power supply VDD; The gate of the transistor NM1 serves as an input terminal to receive an externally inputted startup voltage, and the source of the transistor NM1 is grounded; The switch S1 is connected in parallel with the resistor R1 to implement a level adjustment function for the output protection voltage.

4. The protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to claim 3, characterized in that: The transistor PM1 is a PMOS transistor, and the transistor NM1 is an NMOS transistor.

5. The protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to claim 3, characterized in that: The transistor PM1 and the transistor NM1 are controlled by a startup voltage input from the outside and serve as switches of the protection voltage generating circuit.

6. A protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to any one of claims 3 to 5, characterized in that: The switch S1 is used to adjust the level of the protection voltage. When the power supply voltage level output by the SRAM is too low, the switch S1 is closed to increase the protection voltage level; otherwise, the switch S1 remains in the off state.

7. The protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to claim 6, characterized in that: The transistor PM2 and the transistor PM3 are PMOS transistors, and the transistor NM2 and the transistor NM3 are NMOS transistors.

8. The protection circuit for powering a radiation-resistant SRAM FPGA configuration storage array according to claim 6, characterized in that: Transistor NM3 and transistor PM3 serve as a current compensation path.

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