EMI shielding wafer-level chip packaging structure

Abstract

The present invention relates to the technical field of chip packaging, and specifically to an EMI shielding wafer-level chip packaging structure, comprising: a wafer base plate, a wafer chip is arranged in the wafer base plate, a solder ball is arranged on the front side of the wafer chip, an insulating film is arranged on the back side of the wafer chip, a silicon oxide layer is bonded to the back side of the insulating film, and a shielding layer is arranged on the back side of the silicon oxide layer; a reinforcing layer comprises a rib mesh layer and a reinforcement layer, a thickening layer is bonded to the back side of the reinforcement layer, and the thickening layer is bonded to the front side of the shielding layer; the beneficial effect is: by arranging an insulating film on the back side of the wafer base plate, a silicon oxide layer is arranged on the back side of the insulating film, and a shielding layer is arranged on the back side of the silicon oxide layer, the shielding layer forms a covering shield for the entire wafer, reduces stray and radiation in the packaging, and the shielding layer is made of metal electroplating, and by controlling the electroplating thickness, a recessed portion can be formed on the back side of the shielding layer to improve the packaging strength and stability during subsequent plastic sealing.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an EMI shielding wafer-level chip packaging structure. Background Art

[0002] With the trend of multifunctionality and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to keep up with the development of the new generation of electronic products, the size of the chip is developing towards higher density, faster speed, smaller size and lower cost.

[0003] In the existing chip packaging structure, the redistribution layer on the front side of the chip is connected to the solder balls, the back side of the chip is plastic-sealed, and the chip is mounted on the PCB substrate in an inverted manner and maintained electrically connected through the solder balls.

[0004] However, the chip itself is extremely fragile. The chip and the substrate to which it is connected have different thermal expansion coefficients. When the chip is subjected to thermal shock, the stress generated between the chip and the substrate may cause the connection between the two to become unstable and the chip to break. Therefore, the present invention proposes an EMI shielding wafer-level chip packaging structure to solve the above problem. Summary of the invention

[0005] The object of the present invention is to provide an EMI shielding wafer-level chip packaging structure to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solution: an EMI shielding wafer-level chip packaging structure, the EMI shielding wafer-level chip packaging structure comprising:

[0007] A wafer base plate, wherein a wafer chip is arranged in the wafer base plate, a solder ball is arranged on the front side of the wafer chip, an insulating film is arranged on the back side of the wafer chip, a silicon oxide layer is attached to the back side of the insulating film, a shielding layer is arranged on the back side of the silicon oxide layer, and a reinforcing layer is arranged between the shielding layer and the silicon oxide layer;

[0008] The reinforcing layer includes a rib mesh layer and a reinforcement layer, and both the rib mesh layer and the reinforcement layer are attached to the back side of the silicon oxide layer. The back side of the reinforcement layer is attached with a thickening layer, and the thickening layer is attached to the front side of the shielding layer.

[0009] Preferably, a protrusion is provided on the front side of the shielding layer, the protrusion is in the same plane as the thickening layer, and the front side of the protrusion is in contact with the back side of the rib mesh layer.

[0010] Preferably, the shielding layer is made of metal electroplating, and the electroplated metal is one of titanium, copper, aluminum, nickel or an alloy.

[0011] Preferably, the back side of the shielding layer is polished to keep it flush after electroplating, and the thickness of the shielding layer is 0-700um.

[0012] Preferably, the back surface of the shielding layer is recessed inward to form a recessed portion, and the recessed portion corresponds to the raised portion.

[0013] Preferably, a passivation layer is provided on the surface of the wafer chip, a redistribution layer is provided on the front of the passivation layer, the redistribution layer passes through the passivation layer and is electrically connected to the wafer chip, the solder ball is installed on the front of the redistribution layer, and the solder ball is electrically connected to the redistribution layer.

[0014] Preferably, a metal bump is provided on the back side of the wafer chip, the metal bump is located between the wafer chip and the insulating film, and the insulating film is kept in contact with the back side of the metal bump.

[0015] Preferably, the rib mesh layer is in a "well"-shaped structure, the cross-sectional width of the rib mesh layer is not greater than the interval between two adjacent wafer chips, and the rib mesh layer is made of a flexible non-metallic material.

[0016] Preferably, the reinforcement layers are provided in a plurality and distributed in a rectangular array, the reinforcement layers are located in the grid of the rib mesh layer, and the thickening layers are provided in a plurality and correspond one-to-one to the plurality of reinforcement layers.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention provides an insulating film on the back of a wafer base plate, a silicon oxide layer on the back of the insulating film, and a shielding layer on the back of the silicon oxide layer. The shielding layer forms a covering shield for the entire wafer to reduce stray and radiation in the package. The shielding layer is made of metal electroplating. By controlling the thickness of the electroplating, a recessed portion can be formed on the back of the shielding layer to improve the packaging strength and stability during subsequent plastic sealing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic cross-sectional view of the overall structure of the present invention;

[0020] Figure 2 It is a schematic cross-sectional view of the overall structure of another embodiment of the present invention;

[0021] Figure 3 It is a schematic exploded cross-sectional view of the overall structure of another embodiment of the present invention;

[0022] Figure 4 It is a schematic exploded view of the overall structure of another embodiment of the present invention.

[0023] In the figure: 1. Wafer base plate; 2. Wafer chip; 3. Insulating film; 4. Silicon oxide layer; 5. Shielding layer; 51. Protrusion; 52. Recessed portion; 6. Rib mesh layer; 7. Reinforcement layer; 8. Thickening layer; 9. Metal bump; 10. Rewiring layer; 11. Solder ball. DETAILED DESCRIPTION

[0024] In order to make the purpose and technical solution of the present invention clearly and completely described, and the advantages more clearly understood, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are part of the embodiments of the present invention, rather than all of the embodiments, and are only used to explain the embodiments of the present invention, and are not used to limit the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] For example, see Figure 1-Figure 4 The present invention provides a technical solution: an EMI shielding wafer-level chip packaging structure, the EMI shielding wafer-level chip packaging structure includes:

[0026] A wafer base plate 1 is provided with a wafer chip 2 in the wafer base plate 1. The incoming wafer includes the wafer base plate 1 and the wafer chip 2. A solder ball 11 is provided on the front of the wafer chip 2 for electrically connecting with an external PCB substrate. When the wafer chip 2 is installed, it is installed on the upper surface of the PCB board in a reverse buckle form. An insulating film 3 is provided on the back of the wafer chip 2 for preventing direct contact between the metal material and the wafer chip 2 and affecting the normal operation of the wafer chip 2. A silicon oxide layer 4 is attached to the back of the insulating film 3. The silicon oxide layer 4 itself has insulation and high Hardness, with the insulating film 3, the wafer chip 2 can be better insulated, and the deformation resistance of the wafer chip 2 can be improved, so as to prevent the wafer chip 2 from being separated from the PCB substrate due to deformation, and to prevent the wafer chip 2 from being broken and damaged due to deformation. A shielding layer 5 is arranged on the back of the silicon oxide layer 4, and a reinforcing layer is arranged between the shielding layer 5 and the silicon oxide layer 4. The shielding layer 5 is used to shield the entire wafer base plate 1, reduce the stray and EMI radiation in the package, and reduce the interference between adjacent devices in the system;

[0027] Furthermore, the reinforcing layer includes a rib mesh layer 6 and a reinforcement layer 7, and the rib mesh layer 6 and the reinforcement layer 7 are both adhered to the back side of the silicon oxide layer 4, the rib mesh layer 6 and the reinforcement layer 7 are located in the same plane, the reinforcement layer 7 corresponds to the wafer chip 2, and the rib mesh layer 6 is located in the gap between two adjacent wafer chips 2. A thickening layer 8 is adhered to the back side of the reinforcement layer 7, and the thickening layer 8 is adhered to the front side of the shielding layer 5. When a single wafer chip 2 is cut off, the reinforcement layer 7 and the thickening layer 8 can further improve the resistance of the single wafer chip 2 to deformation. At the same time, the thickening layer 8 and the rib mesh layer 6 are not in the same plane. Due to the existence of the thickening layer 8, the shielding layer 5 can form an upward convex structure, and by controlling the thickness of the electroplated layer of the shielding layer 5 when electroplating metal, it is determined whether to form a recessed portion 52 (see below) on the back side of the shielding layer 5, thereby reducing the difficulty of cutting a single wafer chip 2.

[0028] In order to process the shielding layer 5, the present application also has a raised portion 51 on the front side of the shielding layer 5, and the raised portion 51 is the convex structure mentioned above. The raised portion 51 maintains the same plane as the thickened layer 8, and the front side of the raised portion 51 fits the back side of the rib mesh layer 6. The shielding layer 5 is made of metal electroplating, and the thickness of the electroplated layer (that is, the thickness of the shielding layer 5) needs to be maintained at 0-700um. The electroplated metal is one of titanium, copper, aluminum, nickel or an alloy. During the process of electroplating the metal, if the electroplated metal layer is thick, it needs to be polished and thickened. After the shielding layer 5 is electroplated, its back side will remain flush after polishing.

[0029] In the second embodiment, in order to control the thickness of the shielding layer 5, the back surface of the shielding layer 5 of the present application can also be recessed inward to form a recessed portion 52, and the recessed portion 52 corresponds to the raised portion 51, such as Figure 2 As shown, when the shielding layer 5 is electroplated, the thickness of the shielding layer 5 itself can be controlled by controlling the electroplating time and the metal material used for electroplating. If the electroplating thickness of the shielding layer 5 itself can be between 0-700um, there is no need to grind the back of the shielding layer 5. In this case, since the back of the shielding layer 5 is not polished, a recessed portion 52 will be formed at the position corresponding to the rib mesh layer 6, and when plastic sealing is performed later, the plastic raw material can be automatically filled into the recessed portion 52, thereby improving the connection strength of the plastic sealing.

[0030] In order to improve the service life of the wafer chip 2, the present application also has a passivation layer arranged on the surface of the wafer chip 2, a redistribution layer 10 arranged on the front of the passivation layer, the redistribution layer 10 passes through the passivation layer and is electrically connected to the wafer chip 2, the solder ball 11 is installed on the front of the redistribution layer 10, and the solder ball 11 is electrically connected to the redistribution layer 10. The setting of the passivation layer can prevent chemical corrosion and surface oxidation on the surface of the wafer chip 2, protect the chip from corrosion by chemicals and acidic gases, thereby extending the service life of the chip.

[0031] In order to supplement the structure of the wafer chip 2 , the present application also has a metal bump 9 disposed on the back of the wafer chip 2 . The metal bump 9 is located between the wafer chip 2 and the insulating film 3 , and the insulating film 3 is kept in contact with the back of the metal bump 9 .

[0032] For packaging, the rib mesh layer 6 of the present application is in a "well" shaped structure, such as Figure 4 The figure shows a three-dimensional structure diagram of the rib mesh layer 6. The cross-sectional width of the rib mesh layer 6 is not greater than the spacing between two adjacent wafer chips 2. The rib mesh layer 6 is made of a flexible non-metallic material. A plurality of reinforcement layers 7 are provided and distributed in a rectangular array. The reinforcement layers 7 are located in the grid of the rib mesh layer 6. A plurality of thickening layers 8 are provided and correspond one to one to the plurality of reinforcement layers 7. Figure 3 As shown, the rib mesh layer 6 is first attached to the back of the silicon oxide layer 4, and then the reinforcement layer 7 is coated in the grid of the rib mesh layer 6. After the reinforcement layer 7 is solidified and formed, the thickening layer 8 is coated on the back of the rib mesh layer 6 and the reinforcement layer 7, and the thickening layer 8 is eroded. The connection strength between the thickening layer 8 and the rib mesh layer 6 is less than the connection strength between the thickening layer 8 and the reinforcement layer 7. Therefore, the thickening layer 8 on the back of the rib mesh layer 6 will be eroded and separated to form a groove. Finally, metal electroplating is performed to form a shielding layer 5. Controlling the electroplating thickness of the shielding layer 5 can form the following Figure 1 The shielding layer 5 structure shown or as Figure 2 The structure of the shielding layer 5 is shown.

[0033] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An EMI shielding wafer-level chip packaging structure, characterized in that: The EMI shielding wafer-level chip packaging structure includes: A wafer base plate (1), wherein a wafer chip (2) is arranged in the wafer base plate (1), a solder ball (11) is arranged on the front side of the wafer chip (2), an insulating film (3) is arranged on the back side of the wafer chip (2), a silicon oxide layer (4) is bonded to the back side of the insulating film (3), a shielding layer (5) is arranged on the back side of the silicon oxide layer (4), and a reinforcing layer is arranged between the shielding layer (5) and the silicon oxide layer (4); The reinforcing layer comprises a rib mesh layer (6) and a reinforcement layer (7), and the rib mesh layer (6) and the reinforcement layer (7) are both attached to the back side of the silicon oxide layer (4), the back side of the reinforcement layer (7) is attached to a thickening layer (8), and the thickening layer (8) is attached to the front side of the shielding layer (5); The shielding layer (5) is provided with a raised portion (51) on the front side, the raised portion (51) and the thickened layer (8) are kept in the same plane, and the front side of the raised portion (51) is in contact with the back side of the rib mesh layer (6); The back surface of the shielding layer (5) is recessed inwardly to form a recessed portion (52), and the recessed portion (52) corresponds to the raised portion (51); The reinforcement layers (7) are provided in plurality and distributed in a rectangular array, the reinforcement layers (7) are located in the grid of the rib mesh layer (6), and the thickening layers (8) are provided in plurality and correspond one-to-one to the plurality of reinforcement layers (7).

2. The EMI shielding wafer-level chip packaging structure according to claim 1, characterized in that: The shielding layer (5) is made of metal electroplating, and the electroplated metal is one of titanium, copper, aluminum, nickel, or an alloy.

3. The EMI shielding wafer-level chip packaging structure according to claim 2, characterized in that: The back side of the shielding layer (5) is polished to maintain flushness after electroplating, and the thickness of the shielding layer (5) is 0-700 um.

4. The EMI shielding wafer-level chip packaging structure according to claim 1, characterized in that: A passivation layer is provided on the surface of the wafer chip (2), a redistribution layer (10) is provided on the front side of the passivation layer, the redistribution layer (10) passes through the passivation layer and is electrically connected to the wafer chip (2), the solder ball (11) is installed on the front side of the redistribution layer (10), and the solder ball (11) is electrically connected to the redistribution layer (10).

5. The EMI shielding wafer-level chip packaging structure according to claim 1, characterized in that: A metal bump (9) is provided on the back side of the wafer chip (2); the metal bump (9) is located between the wafer chip (2) and the insulating film (3); the insulating film (3) is kept in contact with the back side of the metal bump (9).

6. The EMI shielding wafer-level chip packaging structure according to claim 1, characterized in that: The rib mesh layer (6) is in a "well"-shaped structure; the cross-sectional width of the rib mesh layer (6) is no greater than the distance between two adjacent wafer chips (2); and the rib mesh layer (6) is made of a flexible non-metallic material.

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