Capacitor flipping method in analog-to-digital converter and successive approximation analog-to-digital converter

Abstract

The present disclosure relates to a capacitor flipping method in an analog-to-digital converter and a successive approximation analog-to-digital converter, the method comprising: before a comparator starts successive comparison, the first ends of the remaining conventional capacitors except the highest conventional capacitor in N-bit conventional capacitors are initially connected to 0, and the first ends of the redundant capacitors are initially connected to a reference voltage; before the comparator performs the ith comparison, the first end of the conventional capacitor corresponding to the ith comparison is flipped to connect to the reference voltage; when the comparator completes the ith comparison and the position after the conventional capacitor corresponding to the ith comparison is a redundant capacitor, according to the comparison result of the ith comparison, the first end of the conventional capacitor corresponding to the ith comparison is flipped to connect to 0 or remain connected to the reference voltage, and the first end of the redundant capacitor located after the conventional capacitor corresponding to the ith comparison is maintained to be connected to the reference voltage. Thus, the fault tolerance after the wrong flip to the reference voltage can be effectively improved, and the analog-to-digital conversion accuracy of the analog-to-digital converter can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of analog-to-digital converters, and in particular to a capacitance flipping method in an analog-to-digital converter and a successive approximation analog-to-digital converter. Background Art

[0002] The successive approximation analog-to-digital converter (SAR ADC) is widely used due to its simple structure, low power consumption and process-friendly features, such as Figure 1 The basic circuit structure of the single-channel SAR ADC shown in the figure mainly includes a sampling and holding circuit (S / H), an analog-to-digital converter DAC, a comparator, a successive approximation logic circuit (SAR Logic), etc. Among them, the sampling and holding circuit samples and holds the input analog signal Vin, and the comparator compares the Vin held by the sampling and holding circuit with the voltage signal Vdac generated by the DAC. The comparison result is digitally latched by the SAR Logic and controls the DAC to flip to generate a new voltage signal, which is compared with Vin again. SAR Logic generally uses a binary search algorithm to control the voltage signal generated by the DAC based on the comparison result of the comparator, such as Figure 2 The basic working principle of SAR ADC is shown in the figure. Vref is the reference voltage provided to DAC externally. The voltage signal Vdac output by SAR Logic for the first time is Vref / 2, the second time is Vref / 2±Vref / 4, the third time is Vref / 2±Vref / 4±Vref / 8, and the fourth time is Vref / 2±Vref / 4±Vref / 8±Vref / 16. N-bit comparisons are performed in sequence. In this process, the voltage signal Vdac established by DAC gradually approaches Vin, or it is judged bit by bit whether Vin is less than Vdac or greater than Vdac. If Vin>Vdac for the nth time, the comparator outputs a logic high level or "1", and the nth bit of SAR Logic is 1. On the contrary, Vin<Vdac, the comparator inputs a logic low level or "0", and the nth bit of SAR Logic is 0, and so on, until the least significant bit is compared. After the above operations are completed, the conversion of the analog signal Vin to the digital signal Dout is completed, and the conversion result can be locked in SAR Logic.

[0003] Among them, DAC currently generally uses capacitor DAC, which can provide better matching than resistor DAC, such as Figure 3 As shown in FIG. 1 , a schematic diagram of the structure of a SAR ADC based on a capacitive DAC is shown. The capacitive DAC mainly includes a binary capacitor array (C N , C N-1 , C N-2 , …, C2, C 1A ) and other parasitic capacitance (C 1B , CP ), each capacitor in the binary capacitor array is connected to the reference voltage Vref (that is, set to 1) or ground (that is, set to 0) through a switch, and SAR Logic controls the switch corresponding to each capacitor to switch to control whether each capacitor in the binary capacitor array is connected to the reference voltage or ground, that is, to control the binary capacitor array to perform capacitor flipping, so that different voltage signals can be output to the comparator.

[0004] For the traditional SAR ADC structure, taking 4 bits as an example, 4 comparisons are required. The weight of each capacitor in the capacitive DAC is 8-4-2-1. The weight is equivalent to the capacitance value, which is used to calculate the digital signal based on the comparison result. Under normal circumstances, if the comparator is correct every time, the final output digital signal of the SAR Logic and the input analog-to-digital signal should differ within 1LSB (Least Significant Bit). For example, assuming that the weight of each capacitor in the capacitive DAC is 8-4-2-1, if Vin = 4.2, then Figure 4 As shown in (a), the 4 comparison results are all correct, and the output Dout = 0×8+1×4+0×2+0×1=4 means the conversion result is correct. However, in actual work, due to insufficient establishment of the capacitive DAC or the accuracy of the comparator, when the voltage of the input signal at both ends of the comparator is close, an incorrect comparison result may occur. Even if the subsequent conversions are correct, the final output and input deviation will be greater than 1LSB, such as Figure 4 As shown in (b), the second comparison is wrong (i.e., an erroneous comparison result occurs), resulting in the output of an erroneous conversion result Dout=0×8+0×4+1×2+1×1=3.

[0005] In practical applications, in order to ensure the correctness of analog-to-digital conversion, additional capacitors are added to the binary capacitor array in the capacitive DAC as redundant bits to eliminate the impact of partial conversion errors on the final output. For example, if the original weight of the capacitive DAC is 8-4-2-1, it can be changed to 7-4-2-1-1. Figure 5 As shown in (a), the results of the five comparisons are all correct, and the output Dout = 0×7 + 1×4 + 0×2 + 0×1 + 0×1 = 4 represents that the conversion result is correct, and Figure 5As shown in (b), if the second bit is compared incorrectly, the output Dout = 0×7+0×4+1×2+1×1+1×1=4. It can be seen that even if the second bit is compared incorrectly, as long as the subsequent bits are compared correctly, the final output conversion result is also correct. Adding redundancy is at the cost of increasing the quantization cycle in exchange for accuracy. In the above example, 8 is split into 7 and 1, and the total capacitance remains unchanged. The weight of the capacitive DAC can also be changed to 8-4-2-2-1, that is, inserting one bit, which can increase the effective number of bits of the analog-to-digital converter. Because high-order capacitors have a greater impact on the performance of the ADC, ensuring that the high-order capacitors have sufficient redundancy is important for the performance of the ADC.

[0006] In the prior art, a shift guessing method is usually used to control a binary capacitor array to perform capacitor flipping. The main logic of the shift guessing method can be briefly described as follows: each capacitor in the binary capacitor array is initially set to 0. When any bit capacitor is compared for the first time, the bit capacitor is flipped to set to Vref, and then according to the comparison result output by the comparator, the bit capacitor is flipped to be connected to 0 or maintained at Vref. For example, if the comparison result output by the comparator is 1, the bit capacitor is flipped from Vref to 0. If the comparison result output by the comparator is 0, it is maintained at Vref, and the next bit capacitor is flipped to set to Vref for the next comparison, and so on, until the least significant bit is compared. However, when redundant bit capacitors are inserted into the binary capacitor array, the above-mentioned traditional shift guessing logic can only guarantee the redundancy of flipping to 0, that is, adding redundant bit capacitors will increase the number of low-order capacitors flipping to Vref, but the number of capacitors flipping to 0 will not increase. Therefore, the fault tolerance of high-order capacitors flipping to Vref is low, making it difficult to remedy the flipping error to Vref (that is, when the bit capacitor flips to Vref due to misjudgment) later, and a very small setup error will cause the final result to not converge, thereby reducing the analog-to-digital conversion accuracy of the analog-to-digital converter. Summary of the invention

[0007] In view of this, the present disclosure proposes a capacitor flipping method in an analog-to-digital converter and a successive approximation analog-to-digital converter, which can improve the fault tolerance after flipping to a reference voltage, which is beneficial to improving the analog-to-digital conversion accuracy of the analog-to-digital converter.

[0008] According to one aspect of the present disclosure, a method for capacitor flipping in an analog-to-digital converter is provided, wherein the analog-to-digital converter comprises: a binary capacitor array and a comparator, wherein the binary capacitor array comprises N-bit conventional capacitors and at least one redundant capacitor located between the conventional capacitors, wherein the capacitance value of the redundant capacitor is greater than or equal to the sum of the capacitance values ​​of each capacitor located after the redundant capacitor, wherein the binary capacitor array is used to output a voltage signal to the comparator according to a reference voltage, wherein the comparator is used to compare an input analog signal with the voltage signal output by the binary capacitor array to obtain a comparison result, wherein the comparison result is used to determine a digital signal corresponding to the analog signal and to control the binary capacitor array to perform capacitor flipping to output a different voltage signal; wherein the method comprises: before the comparator starts successive comparisons, initially connecting a first end of a highest-bit conventional capacitor among the N-bit conventional capacitors to a reference voltage, and connecting the remaining conventional capacitors among the N-bit conventional capacitors except the highest-bit conventional capacitor to a reference voltage. The first end of the capacitor is initially connected to 0, and the first end of the redundant capacitor is initially connected to a reference voltage; the second end of the N-bit regular capacitor and the second end of the redundant capacitor are connected to the comparator; during the period when the comparator performs successive comparisons, the binary capacitor array is controlled to perform capacitor flipping, wherein, when the i-th comparison of the comparator corresponds to the regular capacitor and before the comparator performs the i-th comparison, the first end of the regular capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage; and, when the comparator completes the i-th comparison and a capacitor after the regular capacitor corresponding to the i-th comparison is a redundant capacitor, according to the comparison result of the i-th comparison, the first end of the regular capacitor corresponding to the i-th comparison is flipped to connect to 0 or remain connected to the reference voltage, and the first end of the redundant capacitor located after the regular capacitor corresponding to the i-th comparison is kept connected to the reference voltage, i∈[1,I], I=N+M, M is the number of redundant capacitors.

[0009] In a possible implementation, the method further includes: when the i-th comparison of the comparator corresponds to a redundant bit capacitor and the comparator completes the i-th comparison, according to a comparison result of the i-th comparison, flipping the first end of the redundant bit capacitor corresponding to the i-th comparison to connect to 0 or remain connected to the reference voltage, and flipping the first end of a regular capacitor located after the redundant bit capacitor corresponding to the i-th comparison to connect to the reference voltage.

[0010] In a possible implementation, the method further includes: when the comparator completes the i-th comparison and a capacitor after the conventional capacitor corresponding to the i-th comparison is a conventional capacitor, according to a comparison result of the i-th comparison, flipping the first end of the conventional capacitor corresponding to the i-th comparison to connect to 0 or remain connected to the reference voltage, and flipping the first end of the conventional capacitor after the conventional capacitor corresponding to the i-th comparison to connect to the reference voltage.

[0011] In one possible implementation, when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is greater than the analog signal, the first end of the capacitor corresponding to the i-th comparison remains connected to the reference voltage; or, when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is less than the analog signal, the first end of the capacitor corresponding to the i-th comparison is flipped to be connected to 0; wherein the capacitor corresponding to the i-th comparison includes a conventional capacitor or a redundant bit capacitor.

[0012] In one possible implementation, the redundant bit capacitor includes a first split capacitor and a second split capacitor, wherein the method further includes: before the comparator starts successive comparison, initially connecting the first end of the first split capacitor in the redundant bit capacitor to the reference voltage, and initially connecting the first end of the second split capacitor in the redundant bit capacitor to 0; during the successive comparison of the comparator, when the comparator completes the i-th comparison and a capacitor after the conventional capacitor corresponding to the i-th comparison is the redundant bit capacitor, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage, and the initial connection state of the first ends of the two split capacitors in the redundant bit capacitor located after the conventional capacitor corresponding to the i-th comparison is maintained unchanged, and the first end of the conventional capacitor located after the two split capacitors in the redundant bit capacitor is flipped to be connected to the reference voltage.

[0013] In a possible implementation, the method further includes: when the i-th comparison of the comparator corresponds to a redundant bit capacitor and the comparator completes the i-th comparison, based on the comparison result of the i-th comparison, flipping the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison to connect to 0, or flipping the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison to connect to the reference voltage; and keeping the first end of a regular capacitor located after the redundant bit capacitor connected to the reference voltage.

[0014] In a possible implementation, according to the comparison result of the i-th comparison, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to 0, or the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage, including: when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is smaller than the analog signal, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to 0; or, when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is greater than the analog signal, the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage.

[0015] In a possible implementation manner, the method flips any capacitor in the binary capacitor array to connect to the reference voltage through a D flip-flop with a set function.

[0016] According to another aspect of the present disclosure, a successive approximation analog-to-digital converter is provided, comprising: a sampling and holding circuit, for sampling and holding an input analog signal, and outputting a sampling signal to a comparator; a binary capacitor array, the binary capacitor array comprising N-bit conventional capacitors and at least one redundant bit capacitor located between the conventional capacitors, the capacitance value of the redundant bit capacitor being greater than or equal to the sum of the capacitance values ​​of each bit capacitor located after the redundant bit capacitor, the binary capacitor array being used to output a voltage signal to the comparator according to a reference voltage under the control of a successive approximation logic circuit; the comparator being used to compare the sampling signal output by the sampling and holding circuit with the voltage signal output by the binary capacitor array, obtain a comparison result and input it to the successive approximation logic circuit; the successive approximation logic circuit being used to execute the capacitor flipping method, so as to control the binary capacitor array to perform capacitor flipping according to the comparison result output by the comparator, so as to output different voltage signals; and, according to the comparison result output by the comparator, determining a digital signal corresponding to the analog signal.

[0017] In a possible implementation, the successive approximation logic circuit includes: a D flip-flop with a set function, which is used to flip any capacitor in the binary capacitor array to connect to the reference voltage.

[0018] According to various aspects of the present disclosure, by initially connecting the redundant bit capacitors in the binary capacitor array to the reference voltage, after the comparison result is determined by the regular capacitor preceding the redundant bit capacitor, the redundant bit capacitor does not have a flipping operation from 0 to connecting to the reference voltage, and only the regular capacitor preceding the reference voltage has an operation of flipping from the reference voltage to connecting to 0 or maintaining the reference voltage. In this way, the number of capacitors flipped to 0 in the low-order segment of the binary capacitor array can be increased, and the number of capacitors flipped to the reference voltage in the high-order segment can be reduced, thereby improving the fault tolerance after an error flip to the reference voltage, that is, the binary capacitor array has a certain error correction capability after an error flip to the reference voltage, which is beneficial to improving the conversion accuracy of the analog-to-digital converter.

[0019] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0021] Figure 1 A schematic diagram showing the basic circuit structure of a single-channel SAR ADC in the related art.

[0022] Figure 2 A schematic diagram showing the basic working principle of a single-channel SAR ADC in the related art.

[0023] Figure 3 A schematic structural diagram of a SAR ADC based on a capacitive DAC in the related art is shown.

[0024] Figure 4 (a) is a schematic diagram showing the output voltage signal of a common 4-bit capacitive DAC when the comparator in the related art compares correctly.

[0025] Figure 4 (b) is a schematic diagram showing an output voltage signal of a common 4-bit capacitive DAC when an erroneous comparison occurs in the comparator in the related art.

[0026] Figure 5 (a) is a schematic diagram showing a capacitive DAC output voltage signal with redundant bits added when a comparator performs correct comparison in the related art.

[0027] Figure 5 (b) is a schematic diagram showing a capacitive DAC output voltage signal with redundant bits added when an erroneous comparison occurs in the comparator in the related art.

[0028] Figure 6 A schematic diagram showing a conventional capacitor flipping process of a binary capacitor array in an ADC in a differential mode in the related art.

[0029] Figure 7 A schematic diagram showing a capacitance flipping process of shifting a binary capacitance array with redundant bit capacitance 2C in an ADC in a single-ended mode in the related technology.

[0030] Figure 8 A schematic flow chart of a capacitance flipping method in an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0031] Fig. 9 A schematic diagram showing the capacitance state of a binary capacitor array with redundant bit capacitor 2C before successive comparison is performed according to an embodiment of the present disclosure.

[0032] Fig.10 A schematic diagram showing the capacitance flipping logic of the binary capacitance array when the comparator performs the third comparison according to an embodiment of the present disclosure is shown.

[0033] Fig.11 A schematic diagram showing the capacitance flipping logic of the binary capacitance array when the comparator performs the fourth comparison according to an embodiment of the present disclosure is shown.

[0034] Fig.12 A schematic diagram showing the capacitance state of a binary capacitance array before a comparator performs successive comparisons according to an embodiment of the present disclosure is shown.

[0035] Fig.13 1 shows the comparison of the comparator according to the embodiment of the present disclosure when the comparator performs the third comparison Fig.12 Schematic diagram of the capacitor flipping logic performed by the binary capacitor array in FIG.

[0036] Fig.14 A schematic diagram is shown showing the capacitance flipping logic of two split capacitors in the redundant bit capacitor when the comparator performs the fourth comparison according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0038] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0040] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0041] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0042] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0043] It is known that the analog-to-digital converter ADC in a practical scenario may include a differential mode ADC or a single-ended mode ADC, for example, Figure 6The figure shows the conventional shift-guess capacitor flipping process of the binary capacitor array (8C, 4C, 2C, 1C, 1C) in the ADC in the differential mode, wherein the highest-order capacitor 8C in the binary capacitor array in the initial state (i.e., before the comparator performs successive comparisons) is set to Vref, and the other capacitors are all set to 0, that is, one end of the capacitor (8C) before the first comparison is set to Vref, and the other capacitors are set to 0. It is determined whether 8C remains connected to Vref or flips to 0 according to the comparison result of the first comparison. For example, if the comparison result of the comparator output is 1, 8C connected to the P end of the comparator is flipped from Vref to 0. At this time, 4C is flipped from 0 to Vref, which is equivalent to 4C being transferred from Vref to 0. For the convenience of understanding, this process is called flipping 4C to 0. The 8C connected to the N end of the comparator remains connected to Vref unchanged, and 4C is transferred from 0 to Vref, which is equivalent to 4C being transferred from 0 to Vref. For the convenience of understanding, this process is called flipping 4C to Vref. This operation changes 1 / 2Vref. Each comparison result flips or maintains the current capacitor, and the next capacitor flips from 0 to Vref, and so on, until the least significant bit 1C is compared, and a binary search is performed to compare the results and output the converted digital signal.

[0044] It can be seen that for the single-ended ADC, the capacitor connected to the N-terminal of the comparator is not flipped, only the capacitor connected to the P-terminal of the comparator is flipped. Figure 7 The figure shows the capacitor flipping process of the binary capacitor array (7C, 4C, 2C, 2C, 1C) with redundant capacitor 2C added in the ADC in single-ended mode. In the initial state, 7C in the binary capacitor array is set to Vref, and the other capacitors are all set to 0. After the first comparison is completed, one end of the capacitor (7C) remains at the reference voltage Vref. After the second comparison is completed, one end of the 4C capacitor is set to Vref. When the first 2C (that is, the 2C circled in the figure) is compared, the redundant bit 2C is initially connected to 0. When the comparison result corresponding to the first 2C is 1, the first 2C is flipped from Vref to 0, and the redundant bit 2C is flipped from 0 to Vref, which is equivalent to no flipping. If the comparison result is 0, the redundant bit 2C is flipped from 0 to Vref, and the previous bit 2C remains connected to Vref, which is equivalent to flipping 2C to 0. Figure 7 It can be seen that after inserting the redundant bit capacitor, the original shift guessing logic can only guarantee the redundancy of flipping to 0, that is, adding redundant bit capacitors can increase the number of low-order capacitors flipping to Vref, but the number of capacitors flipping to 0 will not increase. Therefore, the error of high-order capacitors flipping to Vref is difficult to be remedied later, and a very small setup error will cause the final result to not converge.

[0045] Table 1 shows the redundancy of each bit after adding redundant bit capacitors under the traditional shift guess logic. The fault tolerance is the redundancy of the low bit, indicating that the error flip caused by the establishment error within this range can be remedied by the redundancy of the low bit, so that the final result is correct. The larger the fault tolerance, the safer it is, the stronger the self-correction ability is, and the smaller the impact of the capacitor flip error on the final result. The fault tolerance of the traditional shift guess logic flipping to Vref is 0, which means that when the high-bit comparison is wrong (when the bit capacitor flips to Vref due to misjudgment), it cannot be remedied even if the subsequent quantization is correct, resulting in the final output result differing from the input signal by more than 1LSB, making the digital-to-analog conversion performance of the digital-to-analog converter unsatisfactory.

[0046] Table 1

[0047] Each capacitor in a capacitor array 16 8 7 4 2 2 1 When the bit flips to 0, the capacitor 8 1 3 2 0 1 / When the bit is flipped towards Vref, the capacitor 8 7 4 2 2 1 / If the bit is wrong, the capacitor that is mistakenly flipped to vref 8 7 4 2 2 1 / The low bit can flip the capacitor to 0 and 7 6 3 1 1 0 / When the redundant capacitor after the bit Vref is accidentally flipped -1 -1 -1 -1 -1 -1 / The amount of error tolerance for vref 0 0 0 0 0 0 / If the capacitor is accidentally flipped to 0 when the bit is loaned 8 1 3 2 0 1 / The low bit can flip the capacitor to Vref and 16 9 5 3 1 0 / Redundant capacitance after the bit is accidentally flipped to 0 8 8 2 1 1 -1 / Fault tolerance for turning to 0 9 9 3 2 2 0 /

[0048] It can be seen that in the single-ended mode SAR ADC, the traditional shift-guess logic cannot achieve the expected redundancy effect at the redundant bit capacitor, and only has the tolerance for flipping to 0. When this traditional shift-guess logic is used in high-speed applications, the reference voltage of the binary capacitor array in the DAC is not established in time enough, resulting in the comparator outputting an erroneous comparison result, making it impossible to correct the subsequent capacitor flip error and reducing the analog-to-digital conversion accuracy of the analog-to-digital converter.

[0049] In view of this, the embodiments of the present disclosure propose a capacitor flipping method in an analog-to-digital converter, which is equivalent to an optimized shift guessing logic, or an optimization scheme based on the traditional shift guessing logic. By utilizing the capacitor flipping method of the embodiments of the present disclosure, the redundancy capability of the analog-to-digital converter can be improved by changing the connection method of the redundant bit capacitors. Regardless of whether the capacitor is flipped to 0 by mistake or to Vref by mistake, there is a certain amount of fault tolerance to make the final result correct, which is beneficial to improving the analog-to-digital conversion performance of the analog-to-digital converter.

[0050] It should be understood that the capacitance flipping method proposed in the embodiment of the present disclosure can be applied to various analog-to-digital converters using capacitance-type DACs (ie, binary capacitance arrays), for example, based on the above Figure 3 As can be seen from the SAR ADC3 shown, the analog-to-digital converter may include: a binary capacitor array and a comparator, wherein the binary capacitor array may include N-bit regular capacitors and at least one redundant bit capacitor located between the regular capacitors (eg, Figure 7 The redundant bit capacitor 2C shown in FIG. 1 ), wherein the capacitance value of the redundant bit capacitor is greater than or equal to the sum of the capacitance values ​​of each bit capacitor located after the redundant bit capacitor (eg Figure 7The redundant bit capacitance 2C in the middle is equal to the sum of the two subsequent bits 1C), the binary capacitor array is used to output a voltage signal Vdac to the comparator according to the reference voltage, and the comparator is used to compare the input analog signal Vin with the voltage signal Vdac output by the binary capacitor array to obtain a comparison result, which is used to determine the digital signal corresponding to the analog signal and control the binary capacitor array to perform capacitance flipping, so as to output different voltage signals to the comparator one by one.

[0051] Based on the above analog-to-digital converter, Figure 8 A flow chart of a method for flipping a capacitor in an analog-to-digital converter according to an embodiment of the present disclosure is shown. The method for flipping a capacitor can be executed by a successive approximation logic circuit (SAR Logic) in a successive approximation analog-to-digital converter (SAR ADC), such as Figure 8 As shown, the capacitor flipping method includes:

[0052] Step S81, before the comparator starts successive comparison, the first end of the highest-order conventional capacitor among the N-order conventional capacitors is initially connected to a reference voltage, the first ends of the remaining conventional capacitors except the highest-order conventional capacitor among the N-order conventional capacitors are initially connected to 0, and the first end of the redundant capacitor is initially connected to the reference voltage; the second ends of the N-order conventional capacitors and the second ends of the redundant capacitors are connected to the comparator to output a voltage signal to the comparator;

[0053] Step S82, during the period when the comparator performs successive comparisons, the binary capacitor array is controlled to perform capacitor flipping, wherein when the i-th comparison of the comparator corresponds to the normal capacitor and before the comparator performs the i-th comparison, the first end of the normal capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage; and

[0054] When the comparator completes the i-th comparison and a capacitor after the conventional capacitor corresponding to the i-th comparison is a redundant capacitor, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage according to the comparison result of the i-th comparison, and the first end of the redundant capacitor after the conventional capacitor corresponding to the i-th comparison is maintained to be connected to the reference voltage, i∈[1,I], I=N+M, and M is the number of redundant capacitors.

[0055] Among them, connecting 0 means grounding, or setting it to 0, and connecting the reference voltage means setting it to 1, such as Figure 3 As shown, the successive approximation logic circuit can control whether each capacitor is connected to 0 or the reference voltage Vref by controlling the switch flipping (i.e., switching) corresponding to each capacitor in the binary capacitor array. In practical applications, any capacitor in the binary capacitor array can also be flipped to connect to the reference voltage (i.e., set to 1) through a D flip-flop with a set function, and this is not limited in the embodiments of the present disclosure.

[0056] Among them, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage, including: when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is greater than the analog signal, the first end of the conventional capacitor corresponding to the i-th comparison is maintained to be connected to the reference voltage; or, when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is less than the analog signal, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0.

[0057] To facilitate understanding of the capacitor flipping method of the present disclosure, Fig. 9 The binary capacitor array (7C, 4C, 2C, 2C, 1C) with redundant bit capacitor 2C is shown for exemplary description. Fig. 9 It shows that before the comparator performs successive comparisons, the highest bit capacitor 7C in the binary capacitor array is initially connected to Vref, the remaining regular capacitors are initially connected to 0, and the redundant bit capacitor 2C is initially connected to the reference voltage Vref. Fig.10 FIG. 2 shows the capacitance flipping logic of the above binary capacitance array when the comparator performs the third comparison, wherein the first two comparisons can control 7C and 4C to perform capacitance flipping according to the traditional shift guessing logic, and the third comparison is to be performed and the third comparison corresponds to the conventional capacitance 2C, and the conventional capacitance 2C is first flipped from being connected to 0 to being connected to Vref, and since the bit after the conventional capacitance 2C is a redundant bit capacitance 2C, after the comparator outputs the comparison result of the third comparison, the conventional capacitance 2C can be flipped to be connected to 0 or kept connected to Vref according to the comparison result of the third comparison, wherein, if the comparison result is 1 (that is, the voltage signal Vdac of the ith comparison is less than the input analog signal Vin), the conventional capacitor 2C is flipped to 0, and the redundant capacitor 2C is kept connected to Vref unchanged, that is, the redundant capacitor 2C is not flipped from 0 to Vref, only the conventional capacitor 2C of the previous bit is flipped from Vref to 0, which is equivalent to flipping 2C to 0. If the comparison result is 0 (that is, the voltage signal Vdac is greater than the analog signal Vin), the conventional capacitor 2C is kept connected to Vref, and the redundant capacitor 2C is kept connected to Vref unchanged, that is, there is no flipping operation on both 2C. The above method is compared with the above Figure 7 For example, in the traditional shift guessing logic shown, the redundant bit capacitor 2C is initially connected to 0. In the embodiment of the present disclosure, the redundant bit capacitor is initially kept connected to Vref, which can increase the capacitance of the low-bit segment flipping to 0 and reduce the capacitance of the high-bit segment flipping to Vref, thereby improving the fault tolerance of the high-bit segment flipping to Vref, so that the binary capacitor array has a certain error correction capability regardless of being mistakenly flipped to 0 or to Vref.

[0058] It is understandable that the i-th comparison may also be for the redundant bit capacitor, and thus, in a possible implementation, the method further includes: when the i-th comparison of the comparator corresponds to the redundant bit capacitor and the comparator completes the i-th comparison, according to the comparison result of the i-th comparison, the first end of the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage, and the first end of the conventional capacitor located after the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage. It is understandable that, since the redundant bit capacitor is always connected to the reference voltage before the redundant bit is compared, therefore, when the i-th comparison of the comparator corresponds to the redundant bit capacitor and the comparator completes the i-th comparison, the first end of the redundant bit capacitor corresponding to the i-th comparison can be directly flipped to be connected to 0 or maintained to be connected to the reference voltage according to the comparison result of the i-th comparison, and the first end of the conventional capacitor located after the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage, without first flipping the redundant bit capacitor to be connected to the reference voltage, and then controlling the redundant bit capacitor to be connected to 0 or the reference voltage according to the comparison result.

[0059] Wherein, when the comparison result of the ith comparison indicates that the voltage signal of the ith comparison is greater than the analog signal, the first end of the redundant bit capacitor corresponding to the ith comparison remains connected to the reference voltage; or, when the comparison result of the ith comparison indicates that the voltage signal of the ith comparison is less than the analog signal, the first end of the redundant bit capacitor corresponding to the ith comparison is flipped to be connected to 0. For example, Fig.11 The capacitor flipping logic when the fourth comparison is currently being performed is shown. The redundant bit capacitor 2C corresponding to the fourth comparison, if the current comparison result is 1 (that is, the voltage signal is less than the analog signal), the redundant bit capacitor 2C is flipped to connect to 0, and the regular capacitor 1C after the redundant bit capacitor 2C is flipped to connect to the reference voltage. If the comparison result is 0 (that is, the voltage signal is greater than the analog signal), the redundant bit capacitor 2C can remain connected to the reference voltage, and the regular capacitor 1C after the redundant bit capacitor 2C is flipped to connect to the reference voltage.

[0060] It can be understood that the i-th comparison may also be for a conventional capacitor and the capacitor after the conventional capacitor corresponding to the i-th comparison is still a conventional capacitor, for example Fig. 9 The bit after the conventional capacitor 7C is still the conventional capacitor 4C. In this case, the conventional capacitor 7C can be controlled by the traditional shift guessing method to perform capacitance flipping. Thus, in a possible implementation method, when the comparator completes the i-th comparison and the capacitor after the conventional capacitor corresponding to the i-th comparison is a conventional capacitor, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage, and the first end of the conventional capacitor after the conventional capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage.

[0061] As described above, according to the comparison result of the ith comparison, the first end of the conventional capacitor corresponding to the ith comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage, including: when the comparison result of the ith comparison indicates that the voltage signal of the ith comparison is greater than the analog signal, the first end of the conventional capacitor corresponding to the ith comparison is maintained to be connected to the reference voltage; or, when the comparison result of the ith comparison indicates that the voltage signal of the ith comparison is less than the analog signal, the first end of the conventional capacitor corresponding to the ith comparison is flipped to be connected to 0. For example, the conventional capacitor 4C corresponding to the second comparison is first flipped to be connected to Vref before the comparison. If the comparison result is 1 (that is, the voltage signal is less than the analog signal), the conventional capacitor 4C can be flipped to be connected to 0, and the next conventional capacitor 2C is flipped to be connected to the reference voltage. If the comparison result is 0 (that is, the voltage signal is greater than the analog signal), the conventional capacitor 4C can be maintained to be connected to the reference voltage, and the next conventional capacitor 2C is flipped to be connected to the reference voltage, and so on. Fig. 9 The capacitance flipping logic of the 5th comparison of the binary capacitance array is the same as the 2nd comparison. It should be understood that in the first comparison, since the highest capacitor 7C is initially connected to Vref, the highest capacitor 7C can be directly kept connected to Vref or flipped to 0 according to the first comparison result.

[0062] Table 2 shows the capacitor redundancy of the capacitor flipping method of the embodiment of the present invention after adding redundant capacitors in the single-ended mode. It can be seen from Table 2 that the capacitor flipping method of the embodiment of the present invention can effectively improve the fault tolerance after the high-bit segment flips upward, at the cost of sacrificing a certain amount of fault tolerance for flipping downward, but ultimately achieves the purpose of balance, so that there is a certain error correction capability after erroneous flipping upward or downward.

[0063] Table 2

[0064] Each capacitor in a capacitor array 16 8 7 4 2 2 (set to 1) 1 When the bit flips to 0, the capacitor 8 1 3 2 2 1 / When the bit is flipped towards Vref, the capacitor 8 7 4 2 0 1 / If the bit is wrong, the capacitor that is mistakenly flipped to vref 8 7 4 2 0 1 / The low bit can flip the capacitor to 0 and 9 8 5 3 1 0 / When the redundant capacitor after the bit Vref is accidentally flipped 1 1 1 1 1 -1 / The amount of error tolerance for vref 2 2 2 2 2 0 / If the capacitor is accidentally flipped to 0 when the bit is loaned 8 1 3 2 2 1 / The low bit can flip the capacitor to Vref and 14 7 3 1 1 0 / Redundant capacitance after the bit is accidentally flipped to 0 6 6 0 -1 -1 -1 / Fault tolerance for turning to 0 7 7 1 0 0 0 /

[0065] According to the capacitor flipping method of the embodiment of the present disclosure, by initially connecting the redundant capacitor in the binary capacitor array to the reference voltage, after the comparison result is determined for the regular capacitor before the redundant capacitor, the redundant capacitor does not have a flipping operation from 0 to connecting to the reference voltage, and only the regular capacitor before the reference voltage has an operation of flipping from the reference voltage to connecting to 0 or maintaining the reference voltage. In this way, the number of capacitors flipped to 0 in the low-order segment of the binary capacitor array can be increased, and the number of capacitors flipped to the reference voltage in the high-order segment can be reduced, thereby improving the fault tolerance after an error flip to the reference voltage, that is, the binary capacitor array has a certain error correction capability after an error flip to the reference voltage, which is beneficial to improving the conversion accuracy of the analog-to-digital converter.

[0066] Considering that in actual applications, the redundant bit capacitor may also be composed of two split capacitors, that is, the logic of shift guessing and split flipping can be combined to achieve the balance of the fault tolerance of erroneous flipping to 0 and erroneous flipping to Vref, so that the error correction capability after erroneous flipping to 0 or to Vref is more balanced. Therefore, in a possible implementation, it is assumed that any redundant bit capacitor of the binary capacitor array includes a first split capacitor and a second split capacitor, wherein the method further includes:

[0067] Before the comparator starts successive comparison, the first end of the first split capacitor in the redundant bit capacitor is initially connected to the reference voltage, and the first end of the second split capacitor in the redundant bit capacitor is initially connected to 0;

[0068] During the period when the comparator performs successive comparisons, when the comparator completes the i-th comparison and the capacitor after the conventional capacitor corresponding to the i-th comparison is a redundant capacitor, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or maintained to be connected to the reference voltage, and the initial connection state of the first ends of the two split capacitors in the redundant capacitor after the conventional capacitor corresponding to the i-th comparison is maintained unchanged, and the first end of the conventional capacitor after the two split capacitors in the redundant capacitor is flipped to be connected to the reference voltage.

[0069] For example, Fig.12 The binary capacitor array (8C, 4C, 2C, 1C, 1C, 1C, 1C) before the comparator performs successive comparison is taken as an example, where: Fig.12 The two circled 1Cs are equivalent to two split capacitors 1C of a redundant bit capacitor 2C, wherein the first 1C can be a first split capacitor, and the second 1C can be a second split capacitor, that is, the first end of the first 1C is initially connected to the reference voltage Vref, and the first end of the second 1C is initially connected to 0; the first ends of other conventional capacitors (8C, 4C, 2C and the last two 1Cs) are initially connected to 0. It should be understood that if there are multiple redundant bit capacitors in the binary capacitor array, they can all be changed to a split capacitor structure, that is, they can all be changed to two split capacitors as a redundant bit capacitor.

[0070] It should be understood that the above-mentioned traditional shift guessing logic can be used to implement Fig.12 The capacitance flip logic of the conventional capacitors 8C and 4C, that is, the other capacitors in the binary capacitor array that are not redundant bit capacitors can be operated with reference to the traditional shift guessing logic, which will not be elaborated here. Fig.13 When the comparator performs the third comparison, Fig.12 The capacitance flip logic performed by the binary capacitor array in Fig.13As shown, the conventional capacitor 2C corresponding to the third comparison is first flipped to connect to Vref. After the comparator outputs the comparison result of the third comparison, according to the comparison result, the first end of the conventional capacitor 2C is flipped to connect to 0 or remain connected to Vref, and the two split capacitors in the redundant position capacitor are skipped. The initial connection state of the first ends of the two split capacitors 1C in the redundant position capacitor remains unchanged, and the first end of the conventional capacitor 1C located after the two split capacitors in the redundant position capacitor is flipped to connect to Vref. That is, after the conventional capacitor 2C is compared, the redundant position capacitor is skipped, and the next conventional 1C is set to 1, while the conventional capacitor 2C chooses to connect to Vref or 0, to achieve the operation to 0 or to Vref. In this way, the number of flips to Vref in the binary capacitor array can be reduced, and the fault tolerance for flipping to Vref can be improved. Although the fault tolerance for flipping to 0 can be reduced, the balanced error correction capability for flipping to Vref and to 0 can be achieved.

[0071] It can be understood that the i-th comparison may also be for two split capacitors in the redundant bit capacitor. Therefore, in a possible implementation, the method further includes: when the i-th comparison of the comparator corresponds to the redundant bit capacitor and the comparator completes the i-th comparison, according to the comparison result of the i-th comparison, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to 0, or the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage; and the first end of the conventional capacitor located after the redundant bit capacitor is kept connected to the reference voltage. This method can be understood as, when the redundant bit capacitor is compared, there is no need to flip the redundant bit capacitor to connect to the reference voltage first, but directly flip the first split capacitor and the second split capacitor in the redundant bit capacitor to connect to 0 or the reference voltage respectively according to the comparison result output by the comparator, that is, after the redundant bit comparison, half of the split capacitors in the redundant bit capacitor are controlled to flip to 0 or to Vref.

[0072] Specifically, according to the comparison result of the i-th comparison, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to 0, or the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage, including: when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is smaller than the analog signal, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to 0; or, when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is greater than the analog signal, the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage.

[0073] For example, Fig.14 FIG. 4 shows the capacitance flip logic of the two split capacitors in the redundant bit capacitor when the comparator performs the fourth comparison. Fig.14 As shown, if the comparison result of the 4th comparison is 1 (that is, the voltage signal of the 4th comparison is smaller than the analog signal), the first end of the first split capacitor originally connected to Vref is flipped to be connected to 0; if the comparison result of the 4th comparison is 0 (the voltage signal of the 4th comparison is larger than the analog signal), the first end of the second split capacitor originally connected to 0 is flipped to be connected to Vref, and the conventional capacitor 1C after the two split capacitors is kept connected to Vref. When the next comparison is performed, the conventional capacitor 1C can be flipped or kept according to the comparison result of the next comparison.

[0074] Table 3 shows the redundancy of the shift guess combined with the split capacitor achieved by the above-mentioned capacitor flipping method in the embodiment of the present disclosure. As can be seen from Table 3, the capacitor flipping method in the embodiment of the present disclosure can further improve the fault tolerance of the error flipping to Vref, make the fault tolerance of the error flipping to Vref and to 0 more balanced, and have a certain balanced error correction capability after the error flipping upward or downward.

[0075] Table 3

[0076]

[0077]

[0078] According to the embodiment of the present disclosure, the two split capacitors in the redundant bit capacitor are initially connected to the reference voltage and 0 respectively, so that after the comparison result is determined by the conventional capacitor before the redundant bit capacitor, the two split capacitors in the redundant bit capacitor are not flipped, and when the redundant bit capacitor is compared, half of the split capacitors in the redundant bit capacitor are flipped to 0 or to Vref. In this way, the fault tolerance of the binary capacitor array to Vref and to 0 can be more balanced, so that there is a certain balanced error correction capability after an upward or downward erroneous flip, which is beneficial to improving the conversion accuracy of the analog-to-digital converter.

[0079] The above-mentioned capacitor flipping method provided in the embodiment of the present disclosure can be a capacitor flipping method for a single-ended SAR ADC, which can improve the redundancy capability of the single-ended SAR ADC and effectively ensure the performance of the single-ended SAR ADC. Compared with the traditional shift guessing logic, it mainly improves the fault tolerance of flipping to Vref by changing the connection method of the redundant bit capacitor, thereby improving the analog-to-digital conversion accuracy of the single-ended SAR ADC. The logic implementation method is simple, but the effect is significant.

[0080] When necessary, the above Figures 9 to 14The binary capacitor array of the single-ended mode SAR ADC is used as an example for explanation. A similar capacitor flipping logic can be used for the binary capacitor array of the differential mode SAR ADC. That is, the redundant bit capacitors in the binary capacitor array of the differential mode SAR ADC can be initially connected to the reference voltage, and other conventional capacitors can be connected to 0. The conventional shift guessing logic in the differential mode can then be used to control the capacitor flipping of the binary capacitor array. No further details will be given here.

[0081] Based on the capacitor flipping method provided by the above embodiment of the present disclosure, the embodiment of the present disclosure further provides a successive approximation analog-to-digital converter, including:

[0082] A sample-and-hold circuit is used to sample and hold the input analog signal and output the sampled signal to the comparator;

[0083] A binary capacitor array, the binary capacitor array includes N conventional capacitors and at least one redundant capacitor located between the conventional capacitors, the capacitance value of the redundant capacitor is greater than or equal to the sum of the capacitance values ​​of the capacitors located after the redundant capacitor, and the binary capacitor array is used to output a voltage signal to the comparator according to a reference voltage under the control of a successive approximation logic circuit;

[0084] A comparator, used to compare the sampling signal output by the sample-and-hold circuit with the voltage signal output by the binary capacitor array, obtain a comparison result and input it into a successive approximation logic circuit;

[0085] The successive approximation logic circuit is used to execute the above-mentioned capacitor flipping method to control the binary capacitor array to perform capacitor flipping according to the comparison result output by the comparator to output different voltage signals; and to determine the digital signal corresponding to the analog signal according to the comparison result output by the comparator.

[0086] In a possible implementation, the successive approximation logic circuit includes: a D flip-flop with a set function, which is used to flip any capacitor in the binary capacitor array to connect to a reference voltage.

[0087] It should be understood that the embodiments of the present disclosure do not limit the specific circuit structure of the successive approximation logic circuit, as long as the functional logic required to be implemented by the above-mentioned successive approximation logic circuit can be implemented, that is, the above-mentioned capacitor flipping method provided by the embodiments of the present disclosure can be implemented by a hardware circuit, of course, it can also be implemented by a software program, or a combination of software and hardware, and the embodiments of the present disclosure do not limit this.

[0088] The successive approximation analog-to-digital converter of the disclosed embodiment has higher analog-to-digital conversion performance.

[0089] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the method and product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, unit, circuit, program segment or instruction, and a part of the module, unit, circuit, program segment or instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0090] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A capacitance flipping method in an analog-to-digital converter, the analog-to-digital converter comprising: A binary capacitor array and a comparator, wherein the binary capacitor array includes N conventional capacitors and at least one redundant capacitor located between the conventional capacitors, the capacitance value of the redundant capacitor being greater than or equal to the sum of the capacitance values ​​of each capacitor located after the redundant capacitor, the binary capacitor array being used to output a voltage signal to the comparator according to a reference voltage, the comparator being used to compare an input analog signal with the voltage signal output by the binary capacitor array to obtain a comparison result, the comparison result being used to determine a digital signal corresponding to the analog signal and to control the binary capacitor array to perform capacitor flipping to output different voltage signals; wherein the method comprises: Before the comparator starts successive comparison, the first end of the highest-order conventional capacitor among the N-order conventional capacitors is initially connected to a reference voltage, the first ends of the remaining conventional capacitors among the N-order conventional capacitors except the highest-order conventional capacitor are initially connected to 0, and the first end of the redundant capacitor is initially connected to a reference voltage; the second end of the N-order conventional capacitor and the second end of the redundant capacitor are connected to the comparator; During the period when the comparator performs successive comparisons, the binary capacitor array is controlled to perform capacitor flipping, wherein, when the i-th comparison of the comparator corresponds to a conventional capacitor and before the comparator performs the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage; and When the comparator completes the i-th comparison and a capacitor after the conventional capacitor corresponding to the i-th comparison is a redundant capacitor, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or kept connected to the reference voltage, and the first end of the redundant capacitor after the conventional capacitor corresponding to the i-th comparison is kept connected to the reference voltage, i∈[1,I], I=N+M, M is the number of redundant capacitors; In the case where the i-th comparison of the comparator corresponds to a redundant bit capacitor and the comparator completes the i-th comparison, according to the comparison result of the i-th comparison, the first end of the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to 0 or remain connected to the reference voltage, and the first end of a regular capacitor located after the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage; When the comparator completes the i-th comparison and a capacitor after the conventional capacitor corresponding to the i-th comparison is a conventional capacitor, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or to remain connected to the reference voltage, and the first end of the conventional capacitor after the conventional capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage.

2. The method according to claim 1, characterized in that When the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is greater than the analog signal, the first end of the capacitor corresponding to the i-th comparison remains connected to the reference voltage; or, when the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is less than the analog signal, the first end of the capacitor corresponding to the i-th comparison is flipped to be connected to 0; The capacitor corresponding to the i-th comparison includes a conventional capacitor or a redundant capacitor.

3. The method according to claim 1, characterized in that The redundant bit capacitor includes a first split capacitor and a second split capacitor, wherein the method further includes: Before the comparator starts successive comparison, the first end of the first split capacitor in the redundant bit capacitor is initially connected to the reference voltage, and the first end of the second split capacitor in the redundant bit capacitor is initially connected to 0; During the period when the comparator performs successive comparisons, when the comparator completes the i-th comparison and the capacitor after the conventional capacitor corresponding to the i-th comparison is the redundant capacitor, according to the comparison result of the i-th comparison, the first end of the conventional capacitor corresponding to the i-th comparison is flipped to be connected to 0 or to remain connected to the reference voltage, and the initial connection state of the first ends of the two split capacitors in the redundant capacitor after the conventional capacitor corresponding to the i-th comparison is maintained unchanged, and the first end of the conventional capacitor after the two split capacitors in the redundant capacitor is flipped to be connected to the reference voltage.

4. The method according to claim 1, characterized in that: The method further comprises: When the i-th comparison of the comparator corresponds to a redundant bit capacitor and the comparator completes the i-th comparison, based on the comparison result of the i-th comparison, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to 0, or the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage; and the first end of a regular capacitor located after the redundant bit capacitor is kept connected to the reference voltage.

5. The method according to claim 4, characterized in that According to the comparison result of the i-th comparison, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to 0, or the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to the reference voltage, including: When the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is smaller than the analog signal, the first end of the first split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to be connected to 0; or When the comparison result of the i-th comparison indicates that the voltage signal of the i-th comparison is greater than the analog signal, the first end of the second split capacitor in the redundant bit capacitor corresponding to the i-th comparison is flipped to connect to the reference voltage.

6. The method according to claim 1, characterized in that The method flips any capacitor in the binary capacitor array to connect to the reference voltage through a D flip-flop with a setting function.

7. A successive approximation analog-to-digital converter, characterized in that: include: A sample-and-hold circuit is used to sample and hold the input analog signal and output the sampled signal to the comparator; A binary capacitor array, the binary capacitor array comprising N conventional capacitors and at least one redundant capacitor located between the conventional capacitors, the redundant capacitor having a capacitance greater than or equal to the sum of capacitances of the capacitors located after the redundant capacitor, the binary capacitor array being used to output a voltage signal to the comparator according to a reference voltage under the control of a successive approximation logic circuit; The comparator is used to compare the sampling signal output by the sample-and-hold circuit with the voltage signal output by the binary capacitor array, obtain a comparison result and input it into the successive approximation logic circuit; The successive approximation logic circuit is used to execute the method described in any one of claims 1 to 6, so as to control the binary capacitor array to perform capacitor flipping to output different voltage signals according to the comparison result output by the comparator; and, according to the comparison result output by the comparator, determine the digital signal corresponding to the analog signal.

8. The analog-to-digital converter according to claim 7, characterized in that: The successive approximation logic circuit includes: a D flip-flop with a setting function, which is used to flip any capacitor in the binary capacitor array to connect to the reference voltage.

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