A continuous integer frequency divider

Abstract

The present invention relates to the technical field of integrated circuits, and discloses a continuous integer frequency divider, comprising: at least two frequency divider circuits and a selection circuit, wherein the frequency divider circuit, the output end of which is connected to an input end of the selection circuit; the selection circuit, the input end of which also inputs a control signal; the control signal is determined by the size of the initial frequency division coefficient; the control signal is used to determine the selection of a frequency divider circuit to divide the clock signal, or to determine the selection of multiple frequency divider circuits to form a cascade frequency divider circuit, and the cascade frequency divider circuit sequentially performs pre-division and editable frequency division on the clock signal. The present invention sets multiple frequency dividers, the number of which can be selected and added according to demand, and the frequency division ratio of the frequency divider is determined according to the actual working conditions, thereby realizing the expansion of the duty cycle of the frequency divider.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a continuous integer frequency divider. Background Art

[0002] The schematic diagram of the traditional phase-locked loop circuit is as follows Figure 1 As shown in the figure, it includes a reference clock divider (division ratio is R), a loop feedback clock divider (division ratio is N), a frequency detector, a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator. After the phase-locked loop is locked, the output frequency of the voltage controlled oscillator is Fref*N / R, where Fref is the frequency of the input signal.

[0003] In order to achieve continuous adjustable frequency output of voltage-controlled oscillator, the reference clock divider and loop feedback clock divider are generally set as continuously programmable dividers. However, ordinary continuously programmable dividers have a significant disadvantage, that is, the high level time of its output within each frequency division cycle is generally only one input clock cycle. Assuming that the frequency division ratio of the divider is N, the duty cycle of the frequency division output is 1 / N. Figure 2 The following is a schematic diagram of the input and output waveforms of the divider when N=7. If the input frequency of the divider is very high, then it can be seen that the pulse width of the divided output will be very narrow. Assuming that the voltage-controlled oscillator frequency is 1GHz, the pulse width of each divided output cycle of the loop feedback clock divider is only 1ns, and this pulse width has nothing to do with the specific value of the division ratio. Under the old semiconductor process, an output pulse width that is too narrow may not be able to properly drive the subsequent circuit, causing the subsequent circuit to fail. In order to ensure the reliability of the phase-locked loop circuit function, the pulse width of the output clock must be increased, which can also be understood as increasing the duty cycle of the divider output clock. Summary of the invention

[0004] In view of this, the present invention provides a continuous integer frequency divider to solve the problem of how to extend the duty cycle of the frequency divider.

[0005] The present invention provides a continuous integer frequency divider, comprising: at least two frequency dividing circuits and a selection circuit, wherein the frequency dividing circuit has an output end connected to an input end of the selection circuit; the selection circuit has an input end that also inputs a control signal; the control signal is determined by the size of an initial frequency dividing coefficient; the control signal is used to determine the selection of a frequency dividing circuit to divide a clock signal, or to determine the selection of multiple frequency dividing circuits to form a cascaded frequency dividing circuit, and the cascaded frequency dividing circuit performs pre-division and editable frequency division on the clock signal in sequence.

[0006] The present invention sets a plurality of frequency dividers, the number of which can be selected and added according to demand, and the frequency division ratio of the frequency divider is determined according to actual working conditions, thereby realizing the expansion of the duty cycle of the frequency divider.

[0007] In an optional embodiment, there are two frequency division circuits, namely a first frequency division circuit and a second frequency division circuit, wherein the first frequency division circuit has a first input terminal inputting a clock signal, a second input terminal inputting a first digit of an initial frequency division coefficient in binary form, a third input terminal inputting a control signal, and a first output terminal connected to a first input terminal of a selection circuit; the second frequency division circuit has a first input terminal connected to a first output terminal of the first frequency division circuit, a second input terminal connected to a second output terminal of the first frequency division circuit, an output terminal connected to a second input terminal of the selection circuit, and an output terminal also connected to a fourth input terminal of the first frequency division circuit; the selection circuit has a third input terminal inputting a control signal; when the initial frequency division coefficient is less than a preset threshold value, the control signal controls the output terminal of the selection circuit to be connected to the first output terminal of the first frequency division circuit, and the first frequency division circuit performs frequency division based on the initial frequency division coefficient; when the initial frequency division coefficient is greater than or equal to the preset threshold value, the control signal controls the output terminal of the selection circuit to be connected to the second output terminal of the second frequency division circuit, the first frequency division circuit performs dual-mode pre-division of the initial frequency division coefficient, and the second frequency division circuit performs editable frequency division based on the frequency division signal output by the first frequency division circuit.

[0008] The present invention is composed of some simple peripheral circuits added to the traditional programmable divider, and is very simple to implement. The number of peripheral circuit modules added can be selected according to the needs to achieve arbitrary frequency division, so it has strong applicability. The signal after the duty cycle is expanded can effectively prevent the functional failure of the subsequent circuit of the divider due to the input clock duty cycle being too small under the old semiconductor process. In addition, the working principle of this circuit is to pre-allocate the dual-mode first, and then perform programmable frequency division. Because of the addition of the dual-mode pre-divider, the maximum operating frequency of the divider is further improved, because the dual-mode divider can use a customized circuit to obtain a higher input operating frequency. Therefore, the frequency division scheme provided by the present invention can be said to kill two birds with one stone.

[0009] In an optional embodiment, the first frequency division circuit includes: a first inverter, a first OR gate, a first AND gate and a dual-mode frequency divider, wherein the first inverter, whose input terminal inputs a control signal, whose output terminal is connected to the first input terminal of the first OR gate, and whose output terminal is also connected to the second input terminal of the second frequency division circuit; the first OR gate, whose second input terminal is connected to the output terminal of the second frequency division circuit, and whose output terminal is connected to the first input terminal of the first AND gate; the first AND gate, whose second terminal inputs the first digit of the initial frequency division coefficient in binary form, and whose output terminal is connected to the first input terminal of the dual-mode frequency divider; the dual-mode frequency divider, whose second input terminal inputs a clock signal, whose output terminal is connected to the first input terminal of the selection circuit, and whose output terminal is also connected to the first input terminal of the second frequency division circuit; when the initial frequency division coefficient is less than a preset threshold value, the control signal is at a low level, the output terminal of the selection circuit is connected to the output terminal of the dual-mode frequency divider, and the dual-mode frequency divider performs frequency division based on the initial frequency division coefficient.

[0010] In an optional embodiment, the dual-mode frequency divider includes: a first NAND gate, a second NAND gate, a first D flip-flop, and a second D flip-flop, wherein the first D flip-flop has a D terminal connected to the output terminal of the first NAND gate, a CLK terminal inputs a clock signal, a Q terminal connected to the first input terminal of the selection circuit, the first input terminal of the second frequency dividing circuit, and the first input terminal of the first NAND gate, and a QN terminal connected to the first input terminal of the second NAND gate; a second NAND gate has a second input terminal connected to the output terminal of the first AND gate; a second D flip-flop has a D terminal connected to the output terminal of the second NAND gate, a CLK terminal inputs a clock signal, a Q terminal connected to the second input terminal of the first NAND gate, and a QN terminal is left floating.

[0011] In an optional embodiment, the second frequency division circuit includes: a second NOT gate, a second OR gate and an editable frequency divider, wherein the second NOT gate, its input end is connected to the first output end of the first frequency division circuit, and its output end is connected to the first input end of the second OR gate; the second OR gate, its second input end is connected to the first output end of the first frequency division circuit, and its output end is connected to the first input end of the editable frequency divider; the editable frequency divider, its second input end inputs the other digits of the initial frequency division coefficient in binary form, and its output end is connected to the second input end of the selection circuit; when the initial frequency division coefficient is greater than or equal to a preset threshold value, the control signal is high level, the output end of the selection circuit is connected to the output end of the editable frequency divider, the first frequency division circuit dual-mode pre-divides the initial frequency division coefficient, and the editable frequency divider performs re-division based on the frequency division signal output by the first frequency division circuit.

[0012] In an optional implementation, the preset threshold is 4, and the dual-mode frequency divider is a 2 / 3 dual-mode frequency divider.

[0013] In an optional embodiment, when the initial frequency division coefficient is 2, the duty cycle of the frequency division signal output by the 2 / 3 dual-mode divider is 1 / 2; when the initial frequency division coefficient is 3, the duty cycle of the frequency division signal output by the 2 / 3 dual-mode divider is 2 / 3; when the initial frequency division coefficient is an even number greater than or equal to 4, the duty cycle of the frequency division signal output by the editable divider is 2 / N; when the initial frequency division coefficient is an odd number greater than or equal to 4, the duty cycle of the frequency division signal output by the editable divider is 3 / N, where N is the initial frequency division coefficient; where N is the initial frequency division coefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 is a schematic diagram of a conventional phase-locked loop circuit;

[0016] Figure 2 is the timing diagram of a traditional continuous integer divider;

[0017] Figure 3 is a composition diagram of a continuous integer frequency divider according to an embodiment of the present invention;

[0018] Figure 4 is a composition diagram of another continuous integer frequency divider according to an embodiment of the present invention;

[0019] Figure 5 is a structural diagram of a continuous integer frequency divider according to an embodiment of the present invention;

[0020] Figure 6 is a structural diagram of a dual-mode frequency divider according to an embodiment of the present invention;

[0021] Figure 7 is a structural diagram of another continuous integer frequency divider according to an embodiment of the present invention;

[0022] Figure 8 is a structural diagram of another continuous integer frequency divider according to an embodiment of the present invention;

[0023] Fig. 9 It is a waveform timing diagram of an embodiment of the present invention when the frequency division ratio is 7. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] In this embodiment, a continuous integer frequency divider is provided, such as Figure 3 As shown, it includes: at least two frequency division circuits 1 and a selection circuit 2.

[0029] like Figure 3 As shown, the output end of the frequency dividing circuit 1 is connected to an input end of the selection circuit 2; the input end of the selection circuit 2 also inputs a control signal; the control signal is determined by the size of the initial frequency dividing coefficient.

[0030] Specifically, the control signal is used to determine the selection of a frequency division circuit 1 to divide the clock signal, or to determine the selection of multiple frequency division circuits 1 to form a cascade frequency division circuit, which performs pre-division and editable frequency division on the clock signal in sequence.

[0031] Specifically, for different initial frequency division coefficients, a corresponding frequency division circuit 1 is selected, and the frequency division circuit 1 divides the clock signal to obtain a clock signal of a corresponding frequency. For a clock signal of a certain frequency that needs to be applied, when it is inconvenient to use one frequency division circuit 1, at least two or more frequency division circuits can be cascaded to obtain a clock signal of a corresponding frequency by using multiple frequency divisions.

[0032] In some optional embodiments, such as Figure 4 As shown, there are two frequency dividing circuits 1, namely a first frequency dividing circuit 11 and a second frequency dividing circuit 12.

[0033] like Figure 4 As shown, the first frequency dividing circuit 11 has a first input terminal inputting a clock signal (Fin), a second input terminal inputting a first digit (b0) of the initial frequency dividing coefficient (N) in binary form, a third input terminal inputting a control signal (sel), and a first output terminal connected to the first input terminal of the selection circuit 2.

[0034] like Figure 4As shown, the second frequency dividing circuit 12 has a first input terminal connected to the first output terminal of the first frequency dividing circuit 11, a second input terminal connected to the second output terminal of the first frequency dividing circuit 11, an output terminal connected to the second input terminal of the selection circuit 2, and an output terminal also connected to the fourth input terminal of the first frequency dividing circuit 11.

[0035] like Figure 4 As shown, the selection circuit 2 has a third input terminal that inputs a control signal.

[0036] For different initial frequency division coefficients, this embodiment involves the following two frequency division situations:

[0037] (1) When the initial frequency division coefficient is less than the preset threshold, the control signal controls the output terminal of the selection circuit 2 to be connected to the first output terminal of the first frequency division circuit 11, and the first frequency division circuit 11 performs frequency division based on the initial frequency division coefficient.

[0038] Specifically, the first frequency division circuit 11 has a built-in dual-mode frequency division circuit or a multi-film frequency division circuit, which performs frequency division for an initial frequency division coefficient that is less than a preset threshold value according to the size of the initial frequency division coefficient, wherein the dual-mode frequency division can be 2 / 3 dual-mode frequency division, that is, 2 division or 3 division.

[0039] (2) When the initial frequency division coefficient is greater than or equal to a preset threshold value, the control signal controls the output end of the selection circuit 2 to be connected to the second output end of the second frequency division circuit 12, the first frequency division circuit 11 performs dual-mode pre-division on the initial frequency division coefficient, and the second frequency division circuit 12 performs editable frequency division based on the frequency division signal output by the first frequency division circuit 11.

[0040] Specifically, for an initial frequency division coefficient greater than or equal to a preset threshold, since it is not easy to obtain a signal of a corresponding frequency using only one frequency division circuit, multiple frequency divisions may be performed.

[0041] In some optional embodiments, such as Figure 5 As shown, the first frequency dividing circuit 11 includes: a first inverter INV1, a first OR gate OR1, a first AND gate AND1 and a dual-mode frequency divider Div2 / 3.

[0042] like Figure 5 As shown, the first inverter INV1 has its input terminal inputted with a control signal, its output terminal connected to the first input terminal of the first OR gate OR1 , and its output terminal also connected to the second input terminal of the second frequency dividing circuit 12 .

[0043] like Figure 5 As shown, the second input terminal of the first OR gate OR1 is connected to the output terminal of the second frequency dividing circuit 12, and the output terminal of the first OR gate OR1 is connected to the first input terminal of the first AND gate AND1.

[0044] like Figure 5As shown, the first AND gate AND1 has its second terminal inputted with the first digit of the initial frequency division coefficient in binary form, and its output terminal is connected to the first input terminal of the dual-mode frequency divider Div2 / 3.

[0045] like Figure 5 As shown, the dual-mode frequency divider Div2 / 3 has a second input terminal inputting a clock signal, an output terminal connected to a first input terminal of the selection circuit 2, and an output terminal also connected to a first input terminal of the second frequency divider circuit 12.

[0046] Specifically, when the initial frequency division coefficient is less than the preset threshold, the control signal is at a low level, the output of the selection circuit 2 is connected to the output of the dual-mode frequency divider Div2 / 3, and the dual-mode frequency divider Div2 / 3 performs frequency division based on the initial frequency division coefficient.

[0047] Specifically, refer to Figure 5 When the initial frequency division coefficient is less than the preset threshold, sel is a low level, the first inverter INV1 outputs 1, the first OR gate OR1 outputs 1, and AND1 outputs b0, wherein when the initial frequency division coefficient is an even number, AND1 outputs 0, and when the initial frequency division coefficient is an odd number, AND1 outputs 1, and the dual-mode divider Div2 / 3 inputs the clock signal (Fin), and the dual-mode divider divides the clock signal based on mc, and the selection circuit 2 outputs the output signal of the first frequency division circuit 11.

[0048] In some optional embodiments, such as Figure 6 As shown, the dual-mode frequency divider Div2 / 3 includes: a first NAND gate NAND1, a second NAND gate NAND2, a first D flip-flop DFF1, and a second D flip-flop DFF2.

[0049] like Figure 6 As shown, the first D flip-flop DFF1 has its D terminal connected to the output terminal of the first NAND gate NAND1, and its CLK terminal inputs a clock signal (ie, CLK, which is connected to the output terminal of the first NAND gate NAND1). Figure 5 Its Q end is connected to the first input end of the selection circuit 2, the first input end of the second frequency dividing circuit 12, and the first input end of the first NAND gate NAND1, and its QN end is connected to the first input end of the second NAND gate NAND2.

[0050] like Figure 6 As shown, the second input terminal of the second NAND gate NAND2 is connected to the output terminal of the first AND gate AND1.

[0051] like Figure 6 As shown, the second D flip-flop DFF2 has its D terminal connected to the output terminal of the second NAND gate NAND2, its CLK terminal inputs the clock signal, its Q terminal is connected to the second input terminal of the first NAND gate NAND1, and its QN terminal is suspended.

[0052] Optionally, the dual-mode divider Div2 / 3 is a 2 / 3 dual-mode divider. Figure 6 There are two types of mid-frequency division:

[0053] (1) When the control terminal (mc) is at a low level, the second NAND gate NAND2 is blocked, and the Q terminal of the second D flip-flop DFF2 outputs a fixed high level. Then, the dual-mode frequency divider Div2 / 3 is cascaded with the first NAND gate NAND1 and the first flip-flop to achieve 2-frequency division.

[0054] (2) When the control terminal (mc) is at a high level, driven by the clock, the levels of the Q terminals [Q1Q2] of the first D flip-flop DFF1 and the second D flip-flop DFF2 appear [11, 01, 10] in a cycle, and the dual-mode divider Div2 / 3 achieves 3-division, and the output duty cycle is 2 / 3.

[0055] In some optional embodiments, such as Figure 7 As shown, the second frequency dividing circuit 12 includes: a second invertor INV2, a second OR gate OR2 and an editable frequency divider P.

[0056] like Figure 7 As shown, the second NOT gate INV2 has its input end connected to the first output end of the first frequency dividing circuit 11, and its output end connected to the first input end of the second OR gate OR2.

[0057] like Figure 7 As shown, the second OR gate OR2 has its second input terminal connected to the first output terminal of the first frequency dividing circuit 11, and its output terminal connected to the first input terminal of the editable frequency divider P.

[0058] like Figure 7 As shown, the editable frequency divider P has its second input terminal inputted with other bits of the initial frequency division coefficient in binary form, and its output terminal is connected to the second input terminal of the selection circuit 2.

[0059] Specifically, when the initial frequency division coefficient is greater than or equal to a preset threshold value, the control signal is at a high level, the output end of the selection circuit 2 is connected to the output end of the editable frequency divider P, the first frequency division circuit 11 performs dual-mode pre-division on the initial frequency division coefficient, and the editable frequency divider P performs re-division based on the divided signal output by the first frequency division circuit 11.

[0060] Specifically, refer to Figure 8 , the first frequency dividing circuit 11 is Figure 5 The structure shown in FIG. 1 is as follows: the second frequency dividing circuit 12 is Figure 7 The structure shown, 2 / 3 dual-mode divider is Figure 6As shown in the structure, the continuous integer divider includes: two inverters INV1 and INV2, two two-input OR gates OR1 and OR2, a two-input AND gate AND1, a 2 / 3 dual-mode divider, and a two-to-one selector. Figure 8 The initial frequency division coefficient N has n bits, which are written as bn-1bn-2…b2b1b0 in binary. The lowest bit b0 is sent to the first input of the two-input AND gate AND1. The remaining n-1 bits bn-1bn-2…b2b1 control the frequency division ratio of the continuous programmable frequency divider P. Assuming N=13, the 4-bit binary is 1101, then b0=1, b3b2b1=110, that is, the frequency division ratio sent to the programmable frequency divider is 110 in binary, that is, 6 in decimal. If the control bit of the programmable frequency divider is greater than 3 bits, fill the high bit with 0.

[0061] Figure 8 The output of the middle two-input AND gate AND1 is the mc signal, which controls the frequency division ratio of the 2 / 3 dual-mode frequency divider. The selection signal sel of the two-to-one selector can be obtained by the n-bit frequency division ratio control bn-1bn-2…b2b1b0 through simple combinational logic. For example, when the initial frequency division coefficient N is 2 or 3 in decimal, sel is a low level, and the input selects the 0 input terminal of the two-to-one selector; when the frequency division ratio is greater than or equal to 4, sel is a high level, and the input selects the 1 input terminal of the two-to-one selector.

[0062] Specifically, when the preset threshold is 4, when the initial division coefficient is 2, the duty cycle of the division signal output by the 2 / 3 dual-mode divider is 1 / 2; when the initial division coefficient is 3, the duty cycle of the division signal output by the 2 / 3 dual-mode divider is 2 / 3; when the initial division coefficient is an even number greater than or equal to 4, the duty cycle of the division signal output by the editable divider P is 2 / N; when the initial division coefficient is an odd number greater than or equal to 4, the duty cycle of the division signal output by the editable divider P is 3 / N, where N is the initial division coefficient; where N is the initial division coefficient.

[0063] Exemplarily, when the preset threshold is 4, Figure 8 The operation principle of the consecutive integer divider shown is as follows:

[0064] (1) When the initial frequency division coefficient is 2, sel is at a low level, the two-to-one selector (i.e., selection circuit 2) selects the upper branch, and the clock input of the editable frequency divider P is blocked by the second OR gate OR2. Since the binary number b1b0=10 for frequency division by 2, i.e., b0=0, will result in mc=0, the frequency divider achieves frequency division by 2, and the output duty cycle is 1 / 2.

[0065] (2) When the initial frequency division coefficient is 3, sel is low level, the two-choice selector selects the upper branch, and the second OR gate OR2 of the clock input of the programmable frequency divider is blocked. Since the binary b1b0 of the frequency division is 11, that is, b0 is 1, and the output of the first NOT gate is 1, the output of the first OR gate OR1 is 1, so the output of the first AND gate is 1, then mc is 1, so the continuous integer frequency divider realizes 3 division, and the output duty cycle is 2 / 3.

[0066] (3) When the initial frequency division coefficient is an even number greater than or equal to 4, b0=0 is a low level, sel is a high level, and the two-choice selector selects the lower branch. At this time, the frequency division ratio control terminal mc=0 of the 2 / 3 dual-mode divider, so it is a 2-division. The 2-division signal is sent to the programmable divider P, and its frequency division output high level must be 2 input clock cycles. Therefore, the duty cycle of the output waveform of the entire divider must be 2 / N.

[0067] (4) When the initial frequency division coefficient is an odd number greater than or equal to 5, b0=1 is high level, sel is high level, and the two-choice selector selects the lower branch. At this time, the frequency division ratio control terminal mc of the 2 / 3 dual-mode divider is programmable for feedback control of the divider, and the control logic is slightly complicated.

[0068] Taking the initial frequency division coefficient N = 7 as an example, combined with Figure 8 First, the initial frequency division coefficient is converted to binary: b2b1b0=111. Fig. 9 The timing diagram of the important nodes inside the divider is given. Fig. 9 The first curve is the input clock, the second curve is the control terminal mc of the 2 / 3 dual-mode frequency divider, and the third curve is the output of the 2 / 3 dual-mode frequency divider. It can be seen that when mc is low, it is divided by 2; when mc is high, it is divided by 3. The fourth curve is the output of the internal programmable divider, which is also the output of the entire divider. This waveform achieves a 3-way frequency divider relative to the 2 / 3 dual-mode frequency divider (convert the divider 7 to binary and take the highest two digits to get a decimal 3). Global analysis Fig. 9 From the timing relationship, we can see that the divided output is divided by 7 compared to the input, and the duty cycle of the output clock is 3 / 7.

[0069] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A continuous integer frequency divider, characterized in that: include: At least two frequency division circuits and selection circuits, wherein: A frequency dividing circuit, an output end of which is connected to an input end of the selection circuit; The selection circuit also inputs a control signal to its input terminal; the control signal is determined by the size of the initial frequency division coefficient; The control signal is used to determine the selection of a frequency division circuit to divide the clock signal, or to determine the selection of multiple frequency division circuits to form a cascade frequency division circuit, and the cascade frequency division circuit sequentially performs pre-division and editable frequency division on the clock signal; There are two frequency division circuits, namely a first frequency division circuit and a second frequency division circuit, wherein: A first frequency dividing circuit, having a first input terminal inputting a clock signal, a second input terminal inputting a first digit of an initial frequency dividing coefficient in binary form, a third input terminal inputting a control signal, and a first output terminal connected to the first input terminal of the selection circuit; a second frequency dividing circuit, wherein a first input terminal is connected to a first output terminal of the first frequency dividing circuit, a second input terminal is connected to a second output terminal of the first frequency dividing circuit, an output terminal is connected to a second input terminal of the selection circuit, and an output terminal is further connected to a fourth input terminal of the first frequency dividing circuit; A selection circuit, a third input terminal of which inputs the control signal; When the initial frequency division coefficient is less than a preset threshold, the control signal controls the output end of the selection circuit to be connected to the first output end of the first frequency division circuit, and the first frequency division circuit performs frequency division based on the initial frequency division coefficient; When the initial frequency division coefficient is greater than or equal to a preset threshold, the control signal controls the output end of the selection circuit to be connected to the second output end of the second frequency division circuit, the first frequency division circuit performs dual-mode pre-division on the initial frequency division coefficient, and the second frequency division circuit performs editable frequency division based on the frequency division signal output by the first frequency division circuit.

2. The continuous integer frequency divider according to claim 1, characterized in that: The first frequency dividing circuit includes: a first inverter, a first OR gate, a first AND gate and a dual-mode frequency divider, wherein: A first inverter, whose input terminal is input with the control signal, whose output terminal is connected with the first input terminal of the first OR gate, and whose output terminal is also connected with the second input terminal of the second frequency dividing circuit; A first OR gate, a second input terminal of which is connected to the output terminal of the second frequency dividing circuit, and an output terminal of which is connected to the first input terminal of the first AND gate; A first AND gate, a second end of which inputs the first digit of the initial frequency division coefficient in binary form, and an output end of which is connected to the first input end of the dual-mode frequency divider; A dual-mode frequency divider, whose second input terminal is input with the clock signal, whose output terminal is connected with the first input terminal of the selection circuit, and whose output terminal is also connected with the first input terminal of the second frequency divider circuit; When the initial frequency division coefficient is less than a preset threshold, the control signal is at a low level, the output end of the selection circuit is connected to the output end of the dual-mode frequency divider, and the dual-mode frequency divider performs frequency division based on the initial frequency division coefficient.

3. The continuous integer frequency divider according to claim 2, characterized in that: The dual-mode frequency divider includes: a first NAND gate, a second NAND gate, a first D flip-flop, and a second D flip-flop, wherein: A first D flip-flop, whose D terminal is connected to the output terminal of the first NAND gate, whose CLK terminal inputs the clock signal, whose Q terminal is connected to the first input terminal of the selection circuit, the first input terminal of the second frequency dividing circuit, and the first input terminal of the first NAND gate, and whose QN terminal is connected to the first input terminal of the second NAND gate; A second NAND gate, a second input terminal of which is connected to the output terminal of the first AND gate; The second D flip-flop has its D terminal connected to the output terminal of the second NAND gate, its CLK terminal inputs the clock signal, its Q terminal connected to the second input terminal of the first NAND gate, and its QN terminal suspended.

4. The continuous integer frequency divider according to claim 3, characterized in that: The second frequency dividing circuit includes: a second NOT gate, a second OR gate and an editable frequency divider, wherein: A second NOT gate, whose input end is connected to the first output end of the first frequency dividing circuit, and whose output end is connected to the first input end of the second OR gate; A second OR gate, a second input terminal of which is connected to the first output terminal of the first frequency dividing circuit, and an output terminal of which is connected to the first input terminal of the editable frequency divider; An editable frequency divider, whose second input terminal inputs other digits of the initial frequency division coefficient in binary form, and whose output terminal is connected to the second input terminal of the selection circuit; When the initial frequency division coefficient is greater than or equal to a preset threshold, the control signal is at a high level, the output end of the selection circuit is connected to the output end of the editable frequency divider, the first frequency division circuit performs dual-mode pre-division on the initial frequency division coefficient, and the editable frequency divider performs re-division based on the divided signal output by the first frequency division circuit.

5. The continuous integer frequency divider according to claim 4, characterized in that: The preset threshold is 4, and the dual-mode frequency divider is a 2 / 3 dual-mode frequency divider.

6. The continuous integer frequency divider according to claim 5, characterized in that: When the initial frequency division coefficient is 2, the duty cycle of the frequency division signal output by the 2 / 3 dual-mode frequency divider is 1 / 2; When the initial frequency division coefficient is 3, the duty cycle of the frequency division signal output by the 2 / 3 dual-mode frequency divider is 2 / 3; When the initial frequency division coefficient is an even number greater than or equal to 4, the duty cycle of the frequency division signal output by the editable frequency divider is 2 / N; When the initial frequency division coefficient is an odd number greater than or equal to 4, the duty cycle of the frequency division signal output by the editable frequency divider is 3 / N, where N is the initial frequency division coefficient.

Images