Avalanche-resistant planar superjunction MOSFET and its preparation method and chip

Abstract

The present application belongs to the technical field of power devices, and provides an anti-avalanche planar super junction MOSFET and a preparation method and chip thereof, wherein a concave first dielectric layer is arranged between a first P-type base region and a first N-type source region, a concave second dielectric layer is arranged between a second P-type base region and a second N-type source region, and the first N-type source region and the second N-type source region are of a T-type structure, a vertical portion of the first N-type source region is located in a groove of the first dielectric layer, and a horizontal portion of the first N-type source region is in contact with the first P-type base region, a vertical portion of the second N-type source region is located in a groove of the second dielectric layer, and a horizontal portion of the second N-type source region is in contact with the second P-type base region, thereby suppressing the conduction of a parasitic BJT in the device, suppressing the conduction between the N-type source region and the P-type base region, and improving the anti-avalanche capability and reliability of the planar SJ MOS.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular relates to an avalanche-resistant planar superjunction MOSFET and a preparation method and chip thereof. Background Art

[0002] Planar super junction metal-oxide-semiconductor field-effect transistor (SJMOSFET) is widely used in many electrical fields due to its excellent high voltage resistance. Reliability is becoming an important issue in the design of super junction MOSFET (SJ-MOS). The failure mechanism and improvement in the unclamped inductive switching (UIS) process have always been the research focus of SJ-MOS reliability. UIS is often used to evaluate the avalanche resistance of SJ MOS. Avalanche is a key working condition that SJ MOS often encounters in practical applications. Therefore, improving the avalanche resistance of SJ MOS is of great significance to improving its reliability. Summary of the invention

[0003] In order to solve the above technical problems, the embodiments of the present application provide an avalanche-resistant planar super junction MOSFET and a preparation method and chip thereof, aiming to improve the avalanche resistance and robustness of the planar super junction MOSFET device.

[0004] A first aspect of an embodiment of the present application provides an avalanche-resistant planar superjunction MOSFET, comprising:

[0005] N-type substrate;

[0006] A first P column, an N-type drift layer, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift layer is located between the first P column and the second P column;

[0007] A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P column, and the second P-type base region is formed on the second P column;

[0008] a buffer region formed on the N-type drift layer and located between the first P-type base region and the second P-type base region;

[0009] A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located at the bottom and sidewalls of the groove of the first P-type base region, and the second dielectric layer is located at the bottom and sidewalls of the groove of the second P-type base region;

[0010] A first N-type source region and a second N-type source region, wherein the first N-type source region and the second N-type source region are of a T-type structure, a vertical portion of the first N-type source region is located in the groove of the first dielectric layer, and a horizontal portion of the first N-type source region is in contact with the first P-type base region, and a vertical portion of the second N-type source region is located in the groove of the second dielectric layer, and a horizontal portion of the second N-type source region is in contact with the second P-type base region;

[0011] A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the buffer region, the first P-type base region, and the second P-type base region, and the gate dielectric layer wraps the gate polysilicon layer;

[0012] A source layer formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region and a portion of the gate dielectric layer;

[0013] The drain layer is formed on the back side of the N-type substrate.

[0014] In some embodiments, the first dielectric layer and the second dielectric layer are made of high-k dielectric material.

[0015] In some embodiments, the first dielectric layer and the second dielectric layer are made of hafnium oxide material or silicon oxide material.

[0016] In some embodiments, the buffer region is an N-type 3C-SiC material.

[0017] In some embodiments, the first P-type base region and the second P-type base region are P-type 3C-SiC materials.

[0018] In some embodiments, two ends of the horizontal portion of the first N-type source region are respectively in contact with the first P-type base region; and / or

[0019] Both ends of the horizontal portion of the second N-type source region are in contact with the second P-type base region, respectively.

[0020] In some embodiments, the vertical portions of the first N-type source region and the second N-type source region are trapezoidal structures.

[0021] In some embodiments, widths of the vertical portions of the first N-type source region and the second N-type source region gradually increase in a direction from the drain layer to the source layer.

[0022] A second aspect of the embodiment of the present application further provides a method for preparing an avalanche-resistant planar superjunction MOSFET, the method comprising:

[0023] An N-type drift region is generated by epitaxy on the front side of an N-type substrate;

[0024] A first P column, an N-type drift layer, and a second P column are formed in a partial area of ​​the N-type drift region by using trenching and epitaxial processes; wherein the N-type drift layer is located between the first P column and the second P column;

[0025] Continue to epitaxially grow N-type buffer material on the first P column, the N-type drift layer, and the second P column, and implant P-type doping ions into a partial region of the N-type buffer material to form a first P-type base region, a second P-type base region, and a buffer region; wherein the first P-type base region is formed on the first P column, the second P-type base region is formed on the second P column, and the buffer region is located between the first P-type base region and the second P-type base region;

[0026] Etching partial regions on the first P-type base region and the second P-type base region to form a first groove and a second groove, respectively, and forming a first dielectric layer at the bottom and sidewalls of the first groove, and forming a second dielectric layer at the bottom and sidewalls of the second groove;

[0027] A first N-type source region is formed in the groove of the first dielectric layer, and a second N-type source region is formed in the groove of the second dielectric layer; the first N-type source region and the second N-type source region are of a T-type structure, a vertical portion of the first N-type source region is located in the groove of the first dielectric layer, and a horizontal portion of the first N-type source region is in contact with the first P-type base region, a vertical portion of the second N-type source region is located in the groove of the second dielectric layer, and a horizontal portion of the second N-type source region is in contact with the second P-type base region;

[0028] Depositing polysilicon material on the gate dielectric layer to form a gate polysilicon layer, and continuing to epitaxially grow a gate oxide material to form the gate dielectric layer wrapping the gate polysilicon layer;

[0029] A source layer is formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region and a portion of the gate dielectric layer, and a drain layer is formed on the back side of the N-type substrate.

[0030] A third aspect of the embodiments of the present application further provides a chip, comprising the avalanche-resistant planar superjunction MOSFET as described in any of the above embodiments.

[0031] The beneficial effects of the embodiments of the present application are as follows: by arranging a concave first dielectric layer between the first P-type base region and the first N-type source region, arranging a concave second dielectric layer between the second P-type base region and the second N-type source region, and the first N-type source region and the second N-type source region are T-type structures, the vertical portion of the first N-type source region is located in the groove of the first dielectric layer, and the horizontal portion of the first N-type source region is in contact with the first P-type base region, the vertical portion of the second N-type source region is located in the groove of the second dielectric layer, and the horizontal portion of the second N-type source region is in contact with the second P-type base region, thereby suppressing the conduction of the parasitic BJT in the device, suppressing the conduction between the N-type source region and the P-type base region, and improving the avalanche resistance and reliability of the planar SJ MOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the structure of the avalanche-resistant planar superjunction MOSFET provided in the embodiment of the present application Figure 1 ;

[0033] Figure 2 Schematic diagram of the structure of the avalanche-resistant planar superjunction MOSFET provided in the embodiment of the present application Figure 2 ;

[0034] Figure 3a It is a schematic diagram of the simulation structure of the traditional planar super junction MOSFET;

[0035] Figure 3b A schematic diagram of the simulation structure of an avalanche-resistant planar superjunction MOSFET in an embodiment of the present application;

[0036] Figure 4 The UIS simulation waveforms of the conventional planar super junction MOSFET and the avalanche resistant planar super junction MOSFET in the embodiment of the present application;

[0037] Figure 5 Schematic diagram of current density distribution of a conventional planar super junction MOSFET and an avalanche-resistant planar super junction MOSFET in an embodiment of the present application when the avalanche current IAS=4A and UIS ends;

[0038] Figure 6 : are simulated output characteristic curves of a conventional planar super junction MOSFET and an avalanche resistant planar super junction MOSFET in an embodiment of the present application;

[0039] Figure 7 : are breakdown voltage curves of a conventional planar super junction MOSFET and an avalanche resistant planar super junction MOSFET in an embodiment of the present application;

[0040] Figure 8 : are transfer characteristic curves of a conventional planar super junction MOSFET and an avalanche resistant planar super junction MOSFET in an embodiment of the present application;

[0041] Fig. 9 It is a schematic flow chart of a method for preparing an avalanche-resistant planar superjunction MOSFET provided in an embodiment of the present application;

[0042] Fig.10 is a schematic diagram of forming an N-type drift layer on an N-type substrate provided by an embodiment of the present application;

[0043] Fig.11 is a schematic diagram of forming a first P column and a second P column provided in an embodiment of the present application;

[0044] Fig.12 is a schematic diagram of forming a buffer zone provided in an embodiment of the present application;

[0045] Fig.13 is a schematic diagram of forming a first P-type base region and a second P-type base region provided in an embodiment of the present application;

[0046] Fig.14 is a schematic diagram of forming a first dielectric layer and a second dielectric layer provided in an embodiment of the present application;

[0047] Fig.15 It is a schematic diagram of forming a first N-type source region and a second N-type source region provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0050] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0052] Traditional planar SJ MOS has an inevitable JFET effect, and the JFET resistance will increase the conduction loss of the device and reduce the saturation current.

[0053] In order to solve the above technical problems, the present application embodiment provides an avalanche resistant planar super junction MOSFET, see Figure 1 As shown, the avalanche-resistant planar superjunction MOSFET in this embodiment includes: an N-type substrate 110, a first P-column 121, an N-type drift layer 124, a second P-column 122, a first P-type base region 125, a second P-type base region 127, a buffer region 210, a first dielectric layer 141, a second dielectric layer 142, a first N-type source region 126, a second N-type source region 128, a gate dielectric layer 130, a gate polysilicon layer 131, a source layer 132, and a drain layer 133. The first P-column 121, the N-type drift layer 124, and the second P-column 122 are formed on the front side of the N-type substrate 110; wherein the N-type drift layer 124 is located between the first P-column 121 and the second P-column 122; the first P-type base region 125 is formed on the first P-column 121, and the second P-type base region 127 is formed on the second P-column 122.

[0054] The buffer zone 210 is formed on the N-type drift layer 124, and the buffer zone 210 is located between the first P-type base region 125 and the second P-type base region 127. The first dielectric layer 141 is located at the bottom and sidewalls of the groove of the first P-type base region 125, and the second dielectric layer 142 is located at the bottom and sidewalls of the groove of the second P-type base region 127. The first N-type source region 126 and the second N-type source region 128 are T-type structures, the vertical portion of the first N-type source region 126 is located in the groove of the first dielectric layer 141, and the horizontal portion of the first N-type source region 126 contacts the first P-type base region 125, the vertical portion of the second N-type source region 128 is located in the groove of the second dielectric layer 142, and the horizontal portion of the second N-type source region 128 contacts the second P-type base region 127.

[0055] The gate dielectric layer 130 is formed on the buffer region 210, the first P-type base region 125, and the second P-type base region 127, and the gate dielectric layer 130 wraps the gate polysilicon layer 131. The source layer 132 is formed on the first N-type source region 126, the second N-type source region 128, the first P-type base region 125, the second P-type base region 127 and a portion of the gate dielectric layer 130; the drain layer 133 is formed on the back side of the N-type substrate 110.

[0056] In this embodiment, a parasitic bipolar junction transistor (BJT) is formed by the first N-type source region 126, the second N-type source region 128, the first P-type base region 125, the second P-type base region 127, and the buffer region. In the parasitic BJT, the first N-type source region 126 and the second N-type source region 128 serve as an emitter, the first P-type base region 125 and the second P-type base region 127 serve as a base, and the N-drift region serves as a collector. The condition for the BJT to be turned on is that the base and the emitter are turned on, that is, when the N-type source region and the corresponding P-type base region are turned on, the parasitic BJT of the SJ MOS is turned on. A concave first dielectric layer 141 is provided between the first P-type base region 125 and the first N-type source region 126, and a concave second dielectric layer 142 is provided between the second P-type base region 127 and the second N-type source region 128. The first N-type source region 126 and the second N-type source region 128 are of a T-type structure. The vertical portion of the first N-type source region 126 is located in the groove of the first dielectric layer 141, and the horizontal portion of the first N-type source region 126 is in contact with the first P-type base region 125. The vertical portion of the second N-type source region 128 is located in the groove of the second dielectric layer 142, and the horizontal portion of the second N-type source region 128 is in contact with the second P-type base region 127. Thus, the conduction of a parasitic bipolar junction transistor (BJT) in the device is suppressed, the conduction between the N-type source region and the P-type base region is suppressed, and the avalanche resistance and reliability of the planar SJ MOS are improved.

[0057] In some embodiments, the first dielectric layer 141 and the second dielectric layer 142 are made of high-k dielectric materials.

[0058] In some embodiments, the first dielectric layer 141 and the second dielectric layer 142 are made of hafnium oxide material or silicon oxide material.

[0059] In some embodiments, the buffer region 210 is made of N-type 3C-SiC material.

[0060] In this embodiment, by setting the semiconductor material between the first P-type base region 125 and the second P-type base region 127 to 3C-SiC material and performing N-type ion doping treatment, the heat dissipation of the parasitic BJT area in the device can be further increased, the misconduction of the BJT device can be suppressed, and the device's avalanche resistance can be increased.

[0061] In some embodiments, the first P-type base region 125 and the second P-type base region 127 are P-type 3C-SiC materials.

[0062] In this embodiment, the semiconductor material of the first P-type base region 125 and the second P-type base region 127 is consistent with the semiconductor material of the buffer region 210, both of which are 3C-SiC materials, and the doping types of the first P-type base region 125 and the second P-type base region 127 are opposite to the doping types of the buffer region 210.

[0063] In some embodiments, both ends of the horizontal portion of the first N-type source region 126 are in contact with the first P-type base region 125 , and PN junctions are formed between both ends of the horizontal portion of the first N-type source region 126 and the first P-type base region 125 .

[0064] In some embodiments, both ends of the horizontal portion of the second N-type source region 128 are in contact with the second P-type base region 127 , and PN junctions are formed between both ends of the horizontal portion of the second N-type source region 128 and the second P-type base region 127 .

[0065] In some embodiments, the vertical portions of the first N-type source region 126 and the second N-type source region 128 are trapezoidal structures.

[0066] In this embodiment, combined with Figure 2 As shown, the vertical portions of the first N-type source region 126 and the second N-type source region 128 are arranged as a trapezoidal structure, and the top of the trapezoidal structure serves as the bottom of the first N-type source region 126 and the second N-type source region 128. By so arranging, the current density distribution on both sides of the first N-type source region 126 and the second N-type source region 128 can be adjusted, so that the device can avoid mis-conduction caused by the parasitic BJT effect in the device during UIS testing, thereby improving the device's anti-avalanche capability.

[0067] In some embodiments, the widths of the vertical portions of the first N-type source region 126 and the second N-type source region 128 gradually increase in a direction from the drain layer 133 to the source layer 132 .

[0068] In this embodiment, the width of the vertical portion of the first N-type source region 126 and the second N-type source region 128 gradually increases in the direction from the drain layer 133 to the source layer 132. In this way, the current density distribution on both sides of the first N-type source region 126 and the second N-type source region 128 can be adjusted, so that the device can avoid mis-conduction caused by the parasitic BJT effect in the device during the UIS test, thereby improving the device's avalanche resistance.

[0069] In some embodiments, the gate dielectric layer 130 is formed in the buffer zone 210 as a concave structure, the gate dielectric layer 130 is formed on the groove sidewalls and the bottom of the groove of the buffer zone 210 and the first P-type base region 125 and the second P-type base region 127, and the gate dielectric layer 130 wraps the gate polysilicon layer 131, the gate polysilicon layer 131 is a T-shaped structure, and the vertical portion of the gate polysilicon layer 131 extends into the groove of the buffer zone 210 between the adjacent first P column 121 and the second P column 122, and the first P-type base region 125 and the gate polysilicon layer 131 are connected to each other. A side of the buffer zone 210 is provided between the silicon layers 131, and another side of the buffer zone 210 is provided between the second P-type base region 127 and the gate polysilicon layer 131. The gate dielectric layer 130 isolates the gate polysilicon layer 131 and the buffer zone 210. When an appropriate gate voltage is applied to the gate polysilicon layer 131, an electron current high-speed channel can be formed in the buffer zone 210, and the electron current density in the JFET region is greatly improved, thereby successfully eliminating the JFET effect, increasing the saturation current of the device, and solving the problem of the JFET effect existing in the traditional planar SJ MOS.

[0070] The buffer of the avalanche-resistant planar superjunction MOSFET in the embodiment of the present application is an N-type doped silicon material, the first dielectric layer and the second dielectric layer are hafnium oxide materials, Figure 3a This is a schematic diagram of the simulation structure of a traditional planar superjunction MOSFET. Figure 3b is a schematic diagram of the simulation structure of the avalanche-resistant planar superjunction MOSFET in the embodiment of the present application. Table 1 shows the characteristic parameters of the conventional planar superjunction MOSFET and the avalanche-resistant planar superjunction MOSFET in the embodiment of the present application. Figure 3a , Figure 3bAs shown in Table 1, by setting a concave first dielectric layer 141 between the first P-type base region 125 and the first N-type source region 126, and setting a concave second dielectric layer 142 between the second P-type base region 127 and the second N-type source region 128, the ion doping concentration in the avalanche-resistant planar superjunction MOSFET of the embodiment of the present application can be redistributed, so that the ion doping concentration at the bottom of the first P-type base region 125 and the second P-type base region 127 is at a higher level, and two PN junctions are formed at both ends of the top of the first P-type base region 125 and the second P-type base region 127. In this way, the vertical portion of the first N-type source region 126 is located in the groove of the first dielectric layer 141, and the horizontal portion of the first N-type source region 126 contacts the first P-type base region 125, and the vertical portion of the second N-type source region 128 is located in the groove of the second dielectric layer 142, and the horizontal portion of the second N-type source region 128 contacts the second P-type base region 127, so that the current density and electric field distribution on both sides of the first N-type source region 126 and the second N-type source region 128 can be adjusted, thereby suppressing the conduction of the parasitic bipolar junction transistor (BJT) in the device, suppressing the conduction between the N-type source region and the P-type base region, and improving the avalanche resistance and reliability of the planar SJ MOS.

[0071] Table 1:

[0072]

[0073] Figure 4 : are UIS simulation waveforms of the conventional planar super junction MOSFET and the avalanche resistant planar super junction MOSFET in the embodiment of the present application, Figure 4 The waveform diagram (a) in FIG. 1 is a UIS simulation curve of a conventional planar super junction MOSFET (curve 2) and an avalanche-resistant planar super junction MOSFET (curve 1) in an embodiment of the present application when the avalanche current IAS=3.7A. Figure 4 The waveform diagram (b) in FIG. 1 is a UIS simulation curve of a conventional planar superjunction MOSFET (curve 4) and an anti-avalanche planar superjunction MOSFET (curve 3) in the embodiment of the present application when the avalanche current IAS=4A. In the UIS test, the inductance connected to the test device is 20mH, the power supply connected to the test device is 50V, and the control voltage of the test device is 10V. Figure 4 As shown in Table 1, in the UIS test, when the avalanche current IAS=3.7A, both devices did not fail. When the avalanche current IAS=4A, the traditional planar super junction MOSFET suffered an avalanche failure. The avalanche-resistant planar super junction MOSFET in the embodiment of the present application was normal and did not fail.

[0074] In order to analyze the failure cause, the current density distribution of the conventional planar superjunction MOSFET and the avalanche-resistant planar superjunction MOSFET in the embodiment of the present application was investigated at the end of UIS when the avalanche current IAS=4A. Figure 5 The simulation diagram (a) is a schematic diagram of the current density distribution of a traditional planar superjunction MOSFET. Figure 5 The simulation schematic diagram (b) in FIG. 1 is a schematic diagram of the current density distribution of the avalanche-resistant planar superjunction MOSFET in the embodiment of the present application, wherein the abscissa is the source-drain voltage VDS and the ordinate is the source-drain current IDS. Figure 5 As shown, the main reason for the failure of traditional planar super junction MOSFET is the mis-conduction of parasitic BJT. The avalanche-resistant planar super junction MOSFET in the embodiment of the present application suppresses the conduction of BJT due to the presence of the first dielectric layer and the second dielectric layer, thereby enhancing the device's avalanche resistance.

[0075] Figure 6 These are the simulated output characteristic curves of the traditional planar super junction MOSFET and the avalanche-resistant planar super junction MOSFET in the embodiment of the present application, wherein the horizontal axis is the source-drain voltage VDS, the vertical axis is the source-drain current IDS, curve 5 represents the simulated output characteristic curve of the avalanche-resistant planar super junction MOSFET in the embodiment of the present application, and curve 6 represents the simulated output characteristic curve of the traditional planar super junction MOSFET. Figure 7 : is the breakdown voltage curve of the conventional planar super junction MOSFET and the avalanche resistant planar super junction MOSFET in the embodiment of the present application, wherein the abscissa is the source-drain voltage VDS and the ordinate is the source-drain current IDS. Figure 7 As shown, the breakdown voltages of the conventional planar super junction MOSFET and the avalanche-resistant planar super junction MOSFET in the embodiment of the present application are almost the same. Figure 8 Curve 7 in FIG. 1 is a transfer characteristic curve of an avalanche-resistant planar superjunction MOSFET in an embodiment of the present application. Figure 8 Curve 8 in FIG. 8 is a transfer characteristic curve of a conventional planar super junction MOSFET and an avalanche resistant planar super junction MOSFET in an embodiment of the present application. As shown in Table 1 and Figure 6 , Figure 7 , Figure 8 As shown, the avalanche-resistant planar superjunction MOSFET in the embodiment of the present application does not reduce the static characteristics of the device, and its saturated drain current (IDsat), breakdown voltage (BV), and on-resistance (Ron) do not change significantly.

[0076] The present application also provides a method for preparing an avalanche-resistant planar superjunction MOSFET, see Fig. 9 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0077] In step S100 , an N-type drift region 120 is epitaxially grown on the front surface of an N-type substrate 110 .

[0078] Combination Fig.10 As shown, an N-type drift region 120 may be formed on the front side of the N-type substrate 110 by an epitaxial growth process, and the thickness of the N-type drift region 120 is greater than the thickness of the N-type substrate 110 .

[0079] In some embodiments, the thickness of the N-type substrate 110 may be 3-10 um.

[0080] In some embodiments, the doping concentration of N-type doping ions in the N-type substrate 110 may be 1e 20 cm-3.

[0081] In some embodiments, the thickness of the N-type drift region 120 epitaxially grown on the front side of the N-type substrate 110 in step S100 may be 20-60 um.

[0082] In some embodiments, the doping concentration of N-type doping ions in the N-type drift region 120 epitaxially generated on the front side of the N-type substrate 110 in step S100 may be 1e 15 ~1e 17 cm -3 .

[0083] In step S200 , a first P column 121 , an N-type drift layer 124 , and a second P column 122 are formed in a partial area of ​​the N-type drift region 120 by using trenching and epitaxial growth processes.

[0084] In this embodiment, combined with Fig.11 As shown, deep grooves are formed by etching the two side areas of the N-type drift region, and then P-type semiconductor materials are epitaxially grown in the deep grooves to form a first P column 121 and a second P column 122 respectively, and the N-type drift layer 124 is located between the first P column 121 and the second P column 122.

[0085] In some embodiments, the widths of the N-type drift layer 124 , the first P column 121 , and the second P column 122 are the same.

[0086] In some embodiments, the doping concentration of the P-type doping ions in the first P column 121 and the second P column 122 may be 1e 15 ~1e 17 cm -3 .

[0087] In step S300 , N-type buffer material is epitaxially grown on the first P column 121 , the N-type drift layer 124 , and the second P column 122 , and P-type dopant ions are implanted into a portion of the N-type buffer material 123 to form a first P-type base region 125 and a second P-type base region 127 .

[0088] In this embodiment, combined with Fig.12 As shown, epitaxial growth of N-type buffer material continues on the first P column 121, the N-type drift layer 124, and the second P column 122 to form a buffer zone 210. The thickness of the N-type buffer material on the first P column 121 and the second P column 122 may be 1-5 um, and the doping concentration of the N-type buffer material on the first P column 121 and the second P column 122 may be 1e 15 ~1e 17 cm -3 .

[0089] In some embodiments, in combination Fig.13 As shown, a portion of the N-type buffer material on the first P column 121 and the second P column 122 is implanted with P-type doping ions to form a first P-type base region 125 and a second P-type base region 127, respectively. The doping concentration of the first P-type base region 125 and the second P-type base region 127 is 1e 17 ~5e 18 cm -3 , a first P-type base region 125 is formed on the first P-column 121 , and a second P-type base region 127 is formed on the second P-column 122 .

[0090] In step S400, etching is performed on partial areas of the first P-type base region 125 and the second P-type base region 127 to form a first groove 101 and a second groove 102, and a first dielectric layer 141 is formed at the bottom and sidewalls of the first groove 101, and a second dielectric layer 142 is formed at the bottom and sidewalls of the second groove 102.

[0091] In this embodiment, a first groove 101 and a second groove 102 are formed by etching a part of the first P-type base region 125 and the second P-type base region 127. The depth of the first groove 101 and the second groove 102 may be 0.3-2.0 um, and the width of the first groove 101 and the second groove 102 may be 0.3-2.0 um. Fig.13 As shown, a first dielectric layer 141 is formed at the bottom and sidewall of the first groove 101, and a second dielectric layer 142 is formed at the bottom and sidewall of the second groove 102. Fig.14 shown.

[0092] In step S500 , a first N-type source region 126 is formed in the groove of the first dielectric layer 141 , and a second N-type source region 128 is formed in the groove of the second dielectric layer 142 .

[0093] In this embodiment, the first N-type source region 126 is formed by filling the groove of the first dielectric layer 141 with an N-type source material and etching the N-type source material. The first N-type source region 126 is formed by filling the groove of the second dielectric layer 142 with an N-type source material and etching the N-type source material to form the second N-type source region 128. Fig.15 The first N-type source region 126 forms the second N-type source region 128 in a T-type structure, the vertical portion of the first N-type source region 126 is located in the groove of the first dielectric layer 141, and the horizontal portion of the first N-type source region 126 is in contact with the first P-type base region 125, the vertical portion of the second N-type source region 128 is located in the groove of the second dielectric layer 142, and the horizontal portion of the second N-type source region 128 is in contact with the second P-type base region 127.

[0094] In some embodiments, the thickness of the gate dielectric layer 130 is 50-100 nm.

[0095] In step S600, a gate dielectric layer 130 is formed on the first N-type source region 126, the second N-type source region 128, the first P-type base region 125, the second P-type base region 127, and the buffer region 210, and polysilicon material is deposited on the gate dielectric layer 130 to form a gate polysilicon layer 131, and gate oxide material is continued to be epitaxially grown to form the gate dielectric layer 130 that wraps the gate polysilicon layer 131.

[0096] In this embodiment, combined with Figure 1 As shown, a gate oxide material is epitaxially grown on the first N-type source region 126, the second N-type source region 128, the first P-type base region 125, the second P-type base region 127, and the buffer region 210 to form a gate dielectric layer 130, and a polysilicon material is deposited on the gate dielectric layer 130 to form a gate polysilicon layer 131, and then the gate oxide material is epitaxially grown to form the gate dielectric layer 130 that wraps the gate polysilicon layer 131. Figure 1 As shown, after depositing the polysilicon material, the polysilicon material on the first P-type base region 125 and the second P-type base region 127 and the gate dielectric layer 130 are etched, and then the gate oxide material is epitaxially grown so that the gate dielectric layer 130 can wrap the gate polysilicon layer 131 .

[0097] In some embodiments, a partial area on the buffer zone 210 may be etched to form a deep groove, and then a concave gate dielectric layer 130 is formed at the bottom and sidewalls of the deep groove, and then polysilicon material is filled in the groove of the gate dielectric layer 130. After etching the polysilicon material and the gate dielectric layer 130 on the first P-type base region 125 and the second P-type base region 127, the polysilicon material may be oxidized to form a gate dielectric layer 130 that wraps the gate polysilicon layer 131.

[0098] In some embodiments, the width of the vertical portion of the gate polysilicon layer 131 is 4-8 um.

[0099] In some embodiments, after the polysilicon material is deposited, the polysilicon material may be etched so that the width of the vertical portion of the gate polysilicon layer 131 gradually decreases in the direction from the drain layer 133 to the source layer 132 .

[0100] In this embodiment, the vertical portion of the gate polysilicon layer 131 is gradually reduced in the direction from the drain layer 133 to the source layer 132, so that the bottom area of ​​the vertical portion of the gate polysilicon layer 131 begins to gradually widen until the horizontal portion of the gate polysilicon layer 131 reaches the minimum width at the interface position with the horizontal portion of the gate polysilicon layer 131. With such a design, the vertical portion of the gate polysilicon layer 131 is related to the depth of the drift region where it is located, and is matched with the first P-type base region 125 and the second P-type base region 127 on both sides of the vertical portion of the gate polysilicon layer 131, so as to avoid a large sudden change in the electron current density in the electron current high-speed channel, reduce the negative effect of the increase in the electron current density, ensure the stability of the device, and help eliminate the JEFT effect in the device and increase the saturation current of the device.

[0101] In some embodiments, the gate polysilicon layer 131 has a trapezoidal structure.

[0102] In step S700 , a source layer 132 is formed on the first N-type source region 126 , the second N-type source region 128 , the first P-type base region 125 , the second P-type base region 127 and a portion of the gate dielectric layer 130 , and a drain layer 133 is formed on the back side of the N-type substrate 110 .

[0103] In this embodiment, combined with Figure 1 As shown, electrode material is deposited on and on both sides of the gate dielectric layer 130 to form a source layer 132, and the source layer 132 is in contact with the first N-type source region 126, the second N-type source region 128, the first P-type base region 125, the second P-type base region 127, and a portion of the gate dielectric layer 130. An electrode material is deposited on the back side of the N-type substrate 110 to form a drain layer 133.

[0104] An embodiment of the present application also provides a chip, including the avalanche-resistant planar superjunction MOSFET as described in any of the above embodiments.

[0105] In this embodiment, the chip includes a chip substrate, on which one or more avalanche-resistant planar super junction MOSFETs are arranged. The avalanche-resistant planar super junction MOSFET can be prepared by the preparation method in any of the above embodiments, or the avalanche-resistant planar super junction MOSFET in any of the above embodiments can be arranged on the chip substrate.

[0106] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit with the avalanche-resistant planar superjunction MOSFET.

[0107] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0108] The beneficial effects of the embodiments of the present application are as follows: by arranging a concave first dielectric layer between the first P-type base region and the first N-type source region, arranging a concave second dielectric layer between the second P-type base region and the second N-type source region, and the first N-type source region and the second N-type source region are T-type structures, the vertical portion of the first N-type source region is located in the groove of the first dielectric layer, and the horizontal portion of the first N-type source region is in contact with the first P-type base region, the vertical portion of the second N-type source region is located in the groove of the second dielectric layer, and the horizontal portion of the second N-type source region is in contact with the second P-type base region, thereby suppressing the conduction of the parasitic BJT in the device, suppressing the conduction between the N-type source region and the P-type base region, and improving the avalanche resistance and reliability of the planar SJ MOS.

[0109] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0110] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0111] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0112] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0113] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An avalanche-resistant planar superjunction MOSFET, characterized in that: include: N-type substrate; A first P column, an N-type drift layer, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift layer is located between the first P column and the second P column; A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P-pillar, and the second P-type base region is formed on the second P-pillar; a buffer region formed on the N-type drift layer and located between the first P-type base region and the second P-type base region; A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is located at the bottom and sidewalls of the groove of the first P-type base region, and the second dielectric layer is located at the bottom and sidewalls of the groove of the second P-type base region; A first N-type source region and a second N-type source region, wherein the first N-type source region and the second N-type source region are of a T-type structure, a vertical portion of the first N-type source region is located in the groove of the first dielectric layer, and a horizontal portion of the first N-type source region is in contact with the first P-type base region, and a vertical portion of the second N-type source region is located in the groove of the second dielectric layer, and a horizontal portion of the second N-type source region is in contact with the second P-type base region; A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the buffer region, the first P-type base region, and the second P-type base region, and the gate dielectric layer wraps the gate polysilicon layer; A source layer formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region and a portion of the gate dielectric layer; A drain layer is formed on the back side of the N-type substrate; the buffer zone is made of N-type 3C-SiC material and is subjected to N-type ion doping treatment; the width of the vertical portion of the first N-type source region and the second N-type source region gradually increases in the direction from the drain layer to the source layer.

2. The avalanche-resistant planar superjunction MOSFET according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are made of high-k dielectric material.

3. The avalanche-resistant planar superjunction MOSFET according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are made of hafnium oxide material or silicon oxide material.

4. The avalanche-resistant planar superjunction MOSFET according to claim 1, characterized in that: The first P-type base region and the second P-type base region are made of P-type 3C-SiC material.

5. The avalanche-resistant planar superjunction MOSFET according to claim 1, characterized in that: Two ends of the horizontal portion of the first N-type source region are respectively in contact with the first P-type base region; and / or Both ends of the horizontal portion of the second N-type source region are in contact with the second P-type base region, respectively.

6. The avalanche-resistant planar superjunction MOSFET according to any one of claims 1 to 5, characterized in that: The vertical portions of the first N-type source region and the second N-type source region are trapezoidal structures.

7. A method for preparing an avalanche-resistant planar superjunction MOSFET, characterized in that: The preparation method comprises: An N-type drift region is generated by epitaxy on the front side of the N-type substrate; A first P column, an N-type drift layer, and a second P column are formed in a partial area of ​​the N-type drift region by using trenching and epitaxial processes; wherein the N-type drift layer is located between the first P column and the second P column; Continue to epitaxially grow N-type buffer material on the first P column, the N-type drift layer, and the second P column, and implant P-type doping ions into a partial region of the N-type buffer material to form a first P-type base region, a second P-type base region, and a buffer region; wherein the first P-type base region is formed on the first P column, the second P-type base region is formed on the second P column, and the buffer region is located between the first P-type base region and the second P-type base region; Etching partial regions on the first P-type base region and the second P-type base region to form a first groove and a second groove, respectively, and forming a first dielectric layer at the bottom and sidewalls of the first groove, and forming a second dielectric layer at the bottom and sidewalls of the second groove; A first N-type source region is formed in the groove of the first dielectric layer, and a second N-type source region is formed in the groove of the second dielectric layer; wherein the first N-type source region and the second N-type source region are of a T-type structure, a vertical portion of the first N-type source region is located in the groove of the first dielectric layer, and a horizontal portion of the first N-type source region is in contact with the first P-type base region, and a vertical portion of the second N-type source region is located in the groove of the second dielectric layer, and a horizontal portion of the second N-type source region is in contact with the second P-type base region; Forming a gate dielectric layer on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, and the buffer region, depositing polysilicon material on the gate dielectric layer to form a gate polysilicon layer, and continuing to epitaxially grow a gate oxide material to form the gate dielectric layer wrapping the gate polysilicon layer; A source layer is formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, and a partial area of ​​the gate dielectric layer, and a drain layer is formed on the back side of the N-type substrate; the buffer zone is an N-type 3C-SiC material, and is subjected to N-type ion doping treatment; the width of the vertical portion of the first N-type source region and the second N-type source region gradually increases in the direction from the drain layer to the source layer.

8. A chip, characterized in that: It comprises the avalanche resistant planar super junction MOSFET as described in any one of claims 1 to 6.

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