Antifuse structure and forming method thereof

Abstract

The present disclosure relates to an antifuse structure and a method for forming the same. The antifuse structure includes: a substrate; an antifuse device; a transistor device, including a first doping region, a second doping region, and a third doping region, all located within the substrate. The first doping region is electrically connected to the antifuse device, the second doping region is located on a side of the transistor device away from the antifuse device, and the third doping region is located on a side of the transistor device away from the antifuse device. The first doping region and the second doping region both include first doping ions, the third doping region includes at least the first doping ions and the second doping ions, and the doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region. The present disclosure can reduce the leakage current of the antifuse structure and increase the turn-on current of the antifuse structure, thereby improving the performance of the antifuse structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to an antifuse structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] Semiconductor structures such as DRAMs are often equipped with redundant memory cells, which are used to replace defective memory cells when they become defective, thereby repairing the semiconductor structure. Antifuse structures are commonly used to repair semiconductor structures such as DRAMs. Antifuse structures are non-conductive when inactive and conductive when activated. However, existing antifuse structures suffer from low turn-on current and high leakage current, which reduces their performance.

[0004] Therefore, how to increase the turn-on current of the anti-fuse structure and reduce the leakage current of the anti-fuse structure to improve the performance of the anti-fuse structure is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide an antifuse structure and a method for forming the same, which are used to increase the turn-on current of the antifuse structure and reduce the leakage current of the antifuse structure, so as to improve the performance of the antifuse structure.

[0006] According to some embodiments, the present disclosure provides an antifuse structure, including:

[0007] substrate;

[0008] an antifuse device, at least partially located on the substrate;

[0009] A transistor device is at least partially located on the substrate, the transistor device includes a first doping region, a second doping region and a third doping region, all of which are located in the substrate, the first doping region is electrically connected to the anti-fuse device, the second doping region is located on a side of the transistor device away from the anti-fuse device, and the third doping region is located on a side of the transistor device away from the anti-fuse device, the first doping region and the second doping region both include first doping ions, the third doping region includes at least the first doping ions and the second doping ions, and the doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region.

[0010] In some embodiments, the third doped region includes:

[0011] a first region, contacting the second doping region, the first region including the first doping ions;

[0012] The second region is located below the first region and contacts the first region. The second region includes the second dopant ions, and the dopant ion concentration of the first region is greater than the dopant ion concentration of the second region.

[0013] In some embodiments, in a direction from the transistor device to the anti-fuse device, the first region protrudes beyond the second doped region;

[0014] The second region is located below a portion of the first region protruding from the second doping region.

[0015] In some embodiments, the first region further includes third doping ions, and the third doping ions are used to hinder diffusion of the first doping ions.

[0016] In some embodiments, the first doping ion is a Group IIIA ion, the second doping ion is a Group VA ion, and the third doping ion is a Group IVA ion.

[0017] In some embodiments, the first doping ion is a boron ion, the second doping ion is an arsenic ion, and the third doping ion is a carbon ion.

[0018] In some embodiments, the anti-fuse device includes an anti-fuse dielectric layer located on the substrate, and an anti-fuse gate layer located on the anti-fuse dielectric layer;

[0019] The transistor device includes a transistor dielectric layer located on the substrate and a transistor gate layer located on the transistor dielectric layer. The thickness of the transistor dielectric layer is equal to the thickness of the antifuse dielectric layer.

[0020] According to some other embodiments, the present disclosure further provides a method for forming an antifuse structure, comprising the following steps:

[0021] providing a substrate;

[0022] An anti-fuse device and a transistor device are formed, both of which are at least partially located on the substrate. The transistor device includes a first doping region, a second doping region, and a third doping region, all of which are located within the substrate. The first doping region is electrically connected to the anti-fuse device. The second doping region is located on a side of the transistor device away from the anti-fuse device. The third doping region is located on a side of the transistor device away from the anti-fuse device. The first doping region and the second doping region both include first doping ions. The third doping region includes at least the first doping ions and the second doping ions. The doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region.

[0023] In some embodiments, forming an antifuse device and a transistor device each at least partially located on the substrate includes:

[0024] forming an antifuse dielectric layer, an antifuse gate layer located above the antifuse dielectric layer, a transistor dielectric layer, and a transistor gate layer located above the transistor dielectric layer on the substrate;

[0025] forming the third doped region in the substrate;

[0026] The first doped region and the second doped region are formed in the substrate to form the anti-fuse device including the anti-fuse dielectric layer and the anti-fuse gate layer, and to form the transistor device including the transistor dielectric layer, the transistor gate layer, the first doped region, the second doped region and the third doped region.

[0027] In some embodiments, the steps of forming an antifuse dielectric layer, an antifuse gate layer located above the antifuse dielectric layer, a transistor dielectric layer, and a transistor gate layer located above the transistor dielectric layer on the substrate include:

[0028] Simultaneously forming the antifuse dielectric layer and the transistor dielectric layer that are spaced apart on the substrate;

[0029] The antifuse gate layer is formed above the antifuse dielectric layer, and the transistor gate layer is simultaneously formed above the transistor dielectric layer.

[0030] In some embodiments, the specific steps of forming the third doped region in the substrate include:

[0031] forming a photoresist layer on the substrate, covering the antifuse gate layer, the antifuse dielectric layer, the transistor dielectric layer, and the transistor gate layer, wherein an opening is formed in the photoresist layer, and the opening at least exposes the substrate on a side of the transistor dielectric layer away from the antifuse dielectric layer;

[0032] At least the first doping ions and the second doping ions are implanted along the opening to form the third doping region.

[0033] In some embodiments, the specific steps of implanting at least the first doping ions and the second doping ions along the opening to form the third doping region include:

[0034] Implanting the first dopant ions into a first region in the substrate, where the first region is located on a side of the transistor dielectric layer away from the antifuse dielectric layer;

[0035] The second dopant ions are implanted into a second region within the substrate, where the second region is located on a side of the transistor dielectric layer away from the antifuse dielectric layer and is below the first region, the second region is in contact with the first region, and the dopant ion concentration of the first region is greater than the dopant ion concentration of the second region.

[0036] In some embodiments, before implanting the first dopant ions into the first region in the substrate, the method further includes the following steps:

[0037] Third doping ions are implanted into the first region, where the third doping ions are used to hinder diffusion of the first doping ions.

[0038] In some embodiments, the specific steps of forming the first doped region and the second doped region in the substrate include:

[0039] forming a first spacer covering the sidewalls of the antifuse dielectric layer and the sidewalls of the antifuse gate layer, and forming a second spacer covering the sidewalls of the transistor dielectric layer and the sidewalls of the transistor gate layer;

[0040] The first doping ions are implanted into the substrate from the outer side of the second sidewall to form the first doping region and the second doping region.

[0041] Some embodiments of the present disclosure provide an anti-fuse structure and a method for forming the same. By setting a third doping region on and only on a side of a transistor device away from the anti-fuse device, and making the third doping region include at least first doping ions of the same type as the second doping region and second doping ions of a different type from the second doping region, on the one hand, the leakage current of the anti-fuse structure can be reduced, thereby improving the electrical performance of the anti-fuse structure; on the other hand, the turn-on current of the anti-fuse structure can be increased, reducing the probability of false turn-on, thereby further improving the performance of the anti-fuse structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Attachment Figure 1 is a schematic top view of an antifuse structure in a specific embodiment of the present disclosure;

[0043] Attachment Figure 2 is a schematic cross-sectional view of an antifuse structure in a specific embodiment of the present disclosure;

[0044] Attachment Figure 3 is a flow chart of a method for forming an antifuse structure in a specific embodiment of the present disclosure;

[0045] Attachment Figure 4 -Attached Figure 9 It is a schematic diagram of the main process structure in the process of forming the antifuse structure in a specific embodiment of the present disclosure;

[0046] Attachment Figure 10 is a schematic diagram of an antifuse structure in which a third doped region is distributed on opposite sides of a transistor gate layer;

[0047] Attachment Figure 11 is a schematic diagram of another antifuse structure in which the third doped region is distributed on opposite sides of the transistor gate layer;

[0048] Attachment Figure 12 It is attached Figure 10 The antifuse structure in Figure 11 Performance comparison diagram of the antifuse structure in FIG and the antifuse structure in this specific embodiment. DETAILED DESCRIPTION

[0049] The specific implementation of the anti-fuse structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0050] This specific embodiment provides an anti-fuse structure, Figure 1 is a top view of the antifuse structure in a specific embodiment of the present disclosure, Figure 2 FIG. 1 is a schematic cross-sectional view of an antifuse structure in a specific embodiment of the present disclosure. Figure 1 and Figure 2 As shown, the antifuse structure 11 includes:

[0051] substrate 10;

[0052] an anti-fuse device 33 , at least partially located on the substrate 10 ;

[0053] The transistor device 34 is at least partially located on the substrate 10. The transistor device 34 includes a first doping region 20, a second doping region 21 and a third doping region 15, all of which are located in the substrate 10. The first doping region 20 is electrically connected to the anti-fuse device 33. The second doping region 21 is located on the side of the transistor device 34 away from the anti-fuse device 33. The third doping region 15 is located on the side of the transistor device 34 away from the anti-fuse device 33. The first doping region 20 and the second doping region 21 both include first doping ions. The third doping region 15 includes at least first doping ions and second doping ions, and the doping ion concentration of the third doping region 15 is less than the doping ion concentration of the second doping region 21.

[0054] The antifuse structure 11 may be located in a semiconductor structure such as a DRAM. The substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 10 as a silicon substrate as an example. In other embodiments, the substrate 10 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 10 may include a first direction (e.g., Figure 1 X direction in the ) and the second direction (e.g. Figure 1 A plurality of antifuse structures 11 are arranged at intervals (in the Y direction in the figure), and adjacent antifuse structures 11 are isolated from each other by shallow trench isolation structures 31. Each antifuse structure 11 includes an antifuse device 33, a transistor device 34 electrically connected to the antifuse device 33, and a portion of the substrate 10 corresponding to the antifuse device 33 and the transistor device 34. In one example, the antifuse device 33 also includes an antifuse dielectric layer 28 located on the substrate 10, and an antifuse gate layer 29 located on the antifuse dielectric layer 28. The transistor device 34 includes a transistor dielectric layer 25 located on the substrate 10, and a transistor gate layer 26 located on the transistor dielectric layer 25. One end of the transistor device 34 is electrically connected to the bit line 14, and the other end is electrically connected to the antifuse device 33, as shown in FIG. Figure 1 and Figure 2 As shown. Among them, Figure 2 yes Figure 1Partial cross-sectional diagram at position AA. When the anti-fuse structure 11 performs a write operation, a high voltage (e.g., a voltage of 5.5V to 6V) is applied to the anti-fuse gate layer 29 in the anti-fuse device 33, and a low voltage (e.g., a voltage of 0V) is applied to the bit line 14 electrically connected to the transistor device 34, and the transistor device 34 is turned on, so that the anti-fuse gate layer 29 in the anti-fuse device 33 is broken down under the high voltage and the resistance is reduced, ultimately achieving the purpose of data writing. The second doping ions in the third doping region 15 are used to reduce the leakage current in the transistor device 34. The first doping region 20 can be the drain region of the transistor device 34, and the second doping region 21 is correspondingly the source region of the transistor device 34.

[0055] This specific embodiment compares the relationship between different third doping region positions and the performance of the antifuse structure. Figure 10 This is a schematic diagram of an antifuse structure where the third doped region is distributed on opposite sides of the transistor gate layer. Figure 11 is a schematic diagram of another antifuse structure in which the third doped region is distributed on opposite sides of the transistor gate layer. Figure 12 It is attached Figure 10 The antifuse structure in Figure 11 The performance comparison diagram of the antifuse structure in FIG and the antifuse structure in this specific embodiment. Figure 10 In the antifuse structure shown, the third doped region 15 is distributed in the substrate 10 below the antifuse gate layer 29 and in the substrate 10 on opposite sides of the transistor gate layer 29 along the X-axis direction (i.e., the third doped region 15 is located on the side of the transistor device 34 away from the antifuse device 33, and on the side of the transistor device 34 close to the antifuse device 33 and extending to the substrate 10 below the antifuse device 33); Figure 11 In the anti-fuse structure shown, the third doped regions 15 are distributed in the substrate 10 on two opposite sides of the transistor gate layer 29 along the X-axis direction and do not extend below the anti-fuse gate layer 29 .

[0056] Figure 12 The first curve S1 in the figure is the antifuse structure in this embodiment (ie Figure 1 and Figure 2 A curve showing a relationship between a gate voltage Vg in a transistor device having an antifuse structure as shown and a drain current Id in the transistor device; Figure 12 The second curve S2 in Figure 10 A relationship curve between the gate voltage Vg and the drain current Id of the transistor device in the anti-fuse structure shown; Figure 12 The third curve S3 in Figure 11 The relationship curve between the gate voltage Vg and the drain current Id in the transistor device in the anti-fuse structure shown in FIG. Figure 12It can be seen that the threshold voltage of the transistor device in the antifuse structure in this specific embodiment is less than Figure 10 The threshold voltage of the transistor device in the antifuse structure shown, and Figure 10 The threshold voltage of the transistor device in the antifuse structure shown is less than Figure 11 The threshold voltage of the transistor device in the anti-fuse structure shown. The turn-on current of the transistor device in the anti-fuse structure in this embodiment is greater than Figure 10 The turn-on current of the transistor device in the antifuse structure shown, and Figure 10 The turn-on current of the transistor device in the antifuse structure shown is greater than Figure 11 The turn-on current of the transistor device in the anti-fuse structure shown in FIG. The gate-induced drain leakage current (GIDL) of the transistor device in the anti-fuse structure in this embodiment is less than Figure 10 The gate-induced drain leakage current of the transistor device in the antifuse structure shown is Figure 10 The gate induced drain leakage current of the transistor device in the antifuse structure shown is less than Figure 11 The gate-induced drain leakage current of the transistor device in the antifuse structure is shown.

[0057] This embodiment reduces the leakage current of the antifuse structure 11 by providing a third doping region 15 having a lower dopant ion concentration than the second doping region 21 only on the side of the transistor device 34 away from the antifuse device 33. The third doping region 15 includes at least a first dopant ion and a second dopant ion of a different type than the first dopant ion. Furthermore, the breakdown voltage of the antifuse device 33 is increased, reducing the probability of false activation and thereby improving the performance of the antifuse structure. Simultaneously, the subthreshold swing of the transistor device 34 in the antifuse structure 11 is reduced, thereby improving the gate control capability of the transistor device 34 and further reducing the leakage current in the antifuse structure 11 (particularly the transistor device 34 in the antifuse structure 11). A smaller subthreshold swing indicates that the transistor device is completely off in the subthreshold region (i.e., when the voltage applied to the gate layer is less than the threshold voltage), with zero source-drain current. When the voltage applied to the gate layer reaches the threshold voltage, the transistor device quickly turns on, meaning that the source-drain current is highly sensitive to the voltage applied to the gate layer.

[0058] In some embodiments, the third doping region 15 includes:

[0059] A first region 22 , contacting the second doping region 21 , wherein the first region 22 includes first doping ions;

[0060] The second region 23 is located below the first region 22 and contacts the first region 22 . The second region 23 includes second dopant ions, and the dopant ion concentration of the first region 22 is greater than the dopant ion concentration of the second region 23 .

[0061] For example, if Figure 1 and Figure 2 As shown, the antifuse device 33 and transistor device 34 in the antifuse structure 11 are arranged along the X-axis. The transistor device 34 includes a channel region, and a first doped region 20 and a second doped region 21 distributed on opposite sides of the channel region along the X-axis. The third doped region 15 is located on the side of the channel region away from the first doped region 20 along the X-axis. The third doped region 15 includes a first region 22 that contacts the second doped region 21 and is located above the second doped region 21 along the Z-axis, and a second region 23 located below the first region 22. The first region 22 can serve as an LDD (Lightly Doped Drain) for the transistor device 34. The first region 22 contains a first dopant ion, and the doping concentration of the first dopant ion in the first region 22 is lower than the doping concentration of the first dopant ion in the second doped region 21, thereby reducing leakage current in the transistor device 34. The doping depth of the first dopant ion in the first region 22 is lower than the doping depth of the first dopant ion in the second doped region 21. The second region 23 serves as a HALO (halo) region for the transistor device 34. The second region 23 includes at least a second dopant ion having a different conductivity type than the first dopant ion, thereby reducing the short channel effect of the transistor device 34. The second region 23 contacts the first region 22, thereby forming a PN junction. In one example, the doping concentration of the first dopant ion in the first region 22 is lower than the doping concentration of the second dopant ion in the second doping region 21. The doping concentration of the second dopant ion in the second region 23 is lower than the doping concentration of the first dopant ion in the second doping region 21.

[0062] In some embodiments, in a direction from the transistor device 34 to the anti-fuse device 33 , the first region 22 protrudes from the second doped region 21 ;

[0063] The second region 23 is located below the portion of the first region 22 protruding from the second doping region 21 .

[0064] For example, the first region 22 protrudes toward the first doping region 20 relative to the second doping region 21 along the X-axis, thereby shortening the conductive distance between the first doping region 20 and the second doping region 21 and reducing the hot electron effect. The second region 23 is located below the portion of the first region 22 that protrudes from the second doping region 21 along the X-axis, and the second region 23 is located between the first doping region 20 and the second doping region 21. This suppresses leakage current caused by diffusion of first doping ions in the second doping region 21, suppresses punch-through between the first doping region 20 and the second doping region 21, and reduces the short channel effect of the transistor device 34.

[0065] In some embodiments, the first region 22 further includes third doping ions, which are used to hinder the diffusion of the first doping ions, that is, the third doping ions fix the first doping ions in the first region 22 and reduce the diffusion of the first doping ions in the first region 22 .

[0066] In some embodiments, the first doping ion is a Group IIIA ion, the second doping ion is a Group VA ion, and the third doping ion is a Group IVA ion, where A represents the main group.

[0067] In some embodiments, the first doping ion is a boron ion, the second doping ion is an arsenic ion, and the third doping ion is a carbon ion.

[0068] In some embodiments, the anti-fuse device 33 includes an anti-fuse dielectric layer 28 located on the substrate 10 , and an anti-fuse gate layer 29 located on the anti-fuse dielectric layer 28 ;

[0069] Transistor device 34 includes a transistor dielectric layer 25 located on substrate 10, and a transistor gate layer 26 located on transistor dielectric layer 25. The thickness of transistor dielectric layer 25 is equal to the thickness of antifuse dielectric layer 28. This structure allows for simultaneous formation of antifuse dielectric layer 28 and transistor dielectric layer 25, thereby simplifying the fabrication process of antifuse structure 11. It also helps reduce the threshold voltage of transistor device 34 and minimizes the overall size of antifuse structure 11.

[0070] In one example, the antifuse structure 11 further includes a first spacer 30 covering the sidewalls of the antifuse dielectric layer 28 and the sidewalls of the antifuse gate layer 29. The first spacer 30 is used to support the antifuse dielectric layer 28 and the antifuse gate layer 29 to improve the stability of the antifuse device 33 and reduce the impact of the external environment on the antifuse gate layer 29. The antifuse structure 11 further includes a second spacer 27 covering the sidewalls of the transistor dielectric layer 25 and the sidewalls of the transistor gate layer 26. The second spacer 27 is used to support the transistor dielectric layer 25 and the transistor gate layer 26 to improve the stability of the transistor device 34.

[0071] This embodiment also provides a method for forming an antifuse structure. Figure 3 is a flow chart of a method for forming an antifuse structure in a specific embodiment of the present disclosure, Figure 4 -Attached Figure 9 This is a schematic diagram of the main process structure in the process of forming the anti-fuse structure in the specific embodiment of the present disclosure. The schematic diagram of the anti-fuse structure formed in this specific embodiment can be found in Figure 1 and Figure 2 .like Figures 1-9 As shown, the method for forming an antifuse structure includes the following steps:

[0072] Step S31, providing a substrate 10;

[0073] In step S32, an anti-fuse device 33 and a transistor device 34 are formed, both of which are at least partially located on the substrate 10. The transistor device 34 includes a first doping region 20, a second doping region 21, and a third doping region 15, all of which are located in the substrate 10. The first doping region 20 is electrically connected to the anti-fuse device 33. The second doping region 21 is located on a side of the transistor device 34 away from the anti-fuse device 33. The third doping region 15 is located on a side of the transistor device 34 away from the anti-fuse device 33. The first doping region 20 and the second doping region 21 both include first doping ions. The third doping region 15 includes at least the first doping ions and the second doping ions. The doping ion concentration of the third doping region 15 is less than the doping ion concentration of the second doping region 21. Figure 1 and Figure 2 shown.

[0074] In some embodiments, forming the antifuse device 33 and the transistor device 34 each at least partially located on the substrate 10 includes:

[0075] An antifuse dielectric layer 28, an antifuse gate layer 29 located above the antifuse dielectric layer 28, a transistor dielectric layer 25, and a transistor gate layer 26 located above the transistor dielectric layer 25 are formed on the substrate 10. Figure 6 As shown;

[0076] A third doping region 15 is formed in the substrate 10, such as Figure 2 and Figure 8 As shown;

[0077] A first doped region 20 and a second doped region 21 are formed in the substrate 10 to form an anti-fuse device 33 including an anti-fuse dielectric layer 28 and an anti-fuse gate layer 29, and a transistor device 34 including a transistor dielectric layer 25, a transistor gate layer 26, a first doped region 20, a second doped region 21 and a third doped region 15, as shown in FIG. Figure 2 shown.

[0078] In some embodiments, the steps of forming the antifuse dielectric layer 28 , the antifuse gate layer 29 located above the antifuse dielectric layer 28 , the transistor dielectric layer 25 , and the transistor gate layer 26 located above the transistor dielectric layer 25 on the substrate 10 include:

[0079] An antifuse dielectric layer 28 and a transistor dielectric layer 25 are formed on the substrate 10 in an alternating manner.

[0080] An anti-fuse gate layer 29 is formed on the anti-fuse dielectric layer 28 , and a transistor gate layer 26 is formed on the transistor dielectric layer 25 at the same time.

[0081] For example, a plurality of shallow trenches are formed in the substrate 10 by etching the substrate 10. The plurality of shallow trenches separate the substrate 10 into a plurality of active areas. Then, an insulating material such as silicon dioxide is filled in the shallow trenches to form a shallow trench isolation structure 31. Figure 4 As shown. Afterwards, along Figure 5 The first dopant ions (e.g., boron ions) are implanted into the substrate 10 in the direction indicated by the solid arrow to form a well region in the substrate 10 and a channel region of the transistor device 34 in the active region. Next, an anti-fuse dielectric layer 28 and a transistor dielectric layer 25 are simultaneously formed on the substrate 10, which are spaced apart along the X-axis direction, and the transistor dielectric layer 25 is located above the channel region. In one example, the transistor dielectric layer 25 and the anti-fuse dielectric layer 28 can be formed by thermal oxidation or in-situ water vapor generation process. Then, an anti-fuse gate layer 29 is formed above the anti-fuse dielectric layer 28, and a transistor gate layer 26 is simultaneously formed above the transistor dielectric layer 25, as shown in FIG. Figure 6 shown.

[0082] In some embodiments, the antifuse gate layer 29 and the transistor gate layer 26 each include multiple layers of conductive materials stacked along the Z-axis direction to enhance the conductivity of the antifuse gate layer 29 and the transistor gate layer 26. In one example, the antifuse gate layer 29 and the transistor gate layer 26 each include a titanium nitride layer, a polysilicon layer, a titanium nitride layer, and a metal tungsten layer stacked sequentially along the Z-axis direction.

[0083] In some embodiments, the specific steps of forming the third doped region 15 in the substrate 10 include:

[0084] A photoresist layer 70 is formed on the substrate 10 to cover the antifuse gate layer 29, the antifuse dielectric layer 28, the transistor dielectric layer 25, and the transistor gate layer 26. An opening is formed in the photoresist layer 70, and the opening exposes at least the substrate 10 on a side of the transistor dielectric layer 25 away from the antifuse dielectric layer 28.

[0085] At least first doping ions and second doping ions are implanted along the opening to form a third doping region 15 .

[0086] In some embodiments, the specific steps of implanting at least the first doping ions and the second doping ions along the opening to form the third doping region 15 include:

[0087] Implanting first dopant ions into a first region 22 in the substrate 10 , where the first region 22 is located on a side of the transistor dielectric layer 25 away from the antifuse dielectric layer 28 ;

[0088] Second dopant ions are implanted into the second region 23 in the substrate 10 . The second region 23 is located on a side of the transistor dielectric layer 25 away from the antifuse dielectric layer 28 and is below the first region 22 . The dopant ion concentration of the first region 22 is greater than that of the second region 23 .

[0089] In some embodiments, before implanting the first dopant ions into the first region 22 in the substrate 10 , the following steps are further included:

[0090] The third doping ions are implanted into the first region 22 , and the third doping ions are used to hinder the diffusion of the first doping ions.

[0091] For example, after forming the transistor gate layer 26 and the antifuse gate layer 29, a photoresist material is deposited on the top surface of the substrate 10 to form a photoresist layer 70 that continuously covers the antifuse gate layer 29, the antifuse dielectric layer 28, the transistor dielectric layer 25, and the transistor gate layer 26. The photoresist layer 70 is patterned to form an opening in the photoresist layer 70 that exposes at least the top surface of the substrate 10 on the side of the transistor dielectric layer 25 away from the antifuse dielectric layer 28. The position of the first region 22 and the position of the second region 23 are pre-defined in the substrate 10. Thereafter, by adjusting the energy, injection angle and other parameters of the ion implantation, the third dopant ions (e.g., carbon ions) are implanted into the first region 22 along the opening. Next, by adjusting the energy, injection angle and other parameters of the ion implantation, the second dopant ions (e.g., arsenic ions) are implanted into the second region 23 along the opening. Then, by adjusting the energy, injection angle and other parameters of the ion implantation again, the first dopant ions (e.g., boron ions) are implanted into the first region 22 along the opening to form a third doped region 15 including the first region 22 and the second region 23, as shown in FIG. Figure 2 and Figure 8 In one example, the injection energy and injection angle when the first dopant ions are injected into the first region 22 are the same as the injection energy and injection angle when the third dopant ions are injected into the first region 22, so that the first dopant ions in the first region 22 can be better fixed by the third dopant ions. The positions of the first and second dopant ions after injection can be adjusted by adjusting the energy and angle of the ion injection. In one example, the ion injection energy when the third dopant ions are injected into the first region 22 can be 7keV to 12keV, and the injection dose can be 2.5×10 14 atoms / cm 2~5×10 14 atoms / cm 2 , the injection angle is 15° to 30°; the ion injection energy when injecting the second doping ion into the second region 23 can be 1.5keV to 4keV, and the injection dose is 4×10 14 pieces / cm 2 ~8×10 14 atoms / cm 2 , the injection angle is 0° (vertical injection); the ion injection energy when injecting the first doping ion into the first region 22 can be 7keV~12keV, and the injection dose is 3×10 13 atoms / cm 2 ~8×10 13 atoms / cm 2 , the injection angle is 15°~30°.

[0092] In one example, after injecting first doping ions into the first region 22 and injecting second doping ions into the second region 23, the substrate 10 can be annealed so that the second doping ions in the second region 23 diffuse toward the first region 22 and / or the first doping ions in the first region 22 diffuse toward the second region 23, thereby causing the first doping ions in the first region 22 to contact the second doping ions in the second region, thereby forming a PN junction.

[0093] In some embodiments, the specific steps of forming the first doping region 20 and the second doping region 21 in the substrate 10 include:

[0094] A first spacer 30 is formed covering the sidewalls of the antifuse dielectric layer 28 and the antifuse gate layer 29, and a second spacer 27 is formed covering the sidewalls of the transistor dielectric layer 25 and the transistor gate layer 26. Figure 9 As shown;

[0095] First doping ions are implanted into the substrate 10 from the outer side of the second spacer 27 to form a first doping region 20 and a second doping region 21 .

[0096] Specifically, after forming the first sidewall spacer 30 and the second sidewall spacer 27, the transistor dielectric layer 25, the transistor gate layer 26, and the second sidewall spacer 27 are used as masks to implant first doping ions into the substrate 10 to form the first doping region 20 and the second doping region 21. The depth of the first doping ions implanted in the first doping region 20 and the second doping region 21 is greater than the depth of the first doping ions implanted in the first region 22, so that the bottom surface of the first doping region 20 and the bottom surface of the second doping region 21 are both located below the bottom surface of the first region 22. In order to further reduce the leakage current in the antifuse structure, in some embodiments, the specific steps of forming the first doping region 20 and the second doping region 21 include: using a first ion implantation process to implant the first doping ions from the outside of the second sidewall spacer 27 into the substrate 10; using a second ion implantation process to implant the first doping ions from the outside of the second sidewall spacer 27 into the substrate 10, and the ion implantation energy of the first ion implantation process is greater than the ion implantation energy of the second ion implantation process. For example, the ion implantation energy of the first ion implantation process is 45 keV and the implantation dose is 6×10 13 atoms / cm 2 The ion implantation energy of the second ion implantation process is 12keV and the implantation dose is / 2×10 15 atoms / cm 2 .

[0097] The anti-fuse structure and the method for forming the same provided in some embodiments of the present specific embodiment, by setting a third doping region on and only on a side of the transistor device away from the anti-fuse device, and making the third doping region include at least first doping ions of the same type as the second doping region and second doping ions of a different type from the second doping region, on the one hand, can reduce the leakage current of the anti-fuse structure, thereby improving the electrical performance of the anti-fuse structure; on the other hand, can increase the turn-on current of the anti-fuse structure, reduce the probability of false turn-on, and further improve the performance of the anti-fuse structure.

[0098] The above are only preferred embodiments of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. An antifuse structure, characterized in that: include: substrate; an antifuse device, at least partially located on the substrate; a transistor device, at least partially located on the substrate, the transistor device comprising a first doping region, a second doping region, and a third doping region all located within the substrate, the first doping region being electrically connected to the anti-fuse device, the second doping region being located on a side of the transistor device away from the anti-fuse device, and the third doping region being located on a side of the transistor device away from the anti-fuse device, the first doping region and the second doping region both comprising first doping ions, the third doping region comprising at least the first doping ions and second doping ions having a conductivity type different from that of the first doping ions, and the doping ion concentration of the third doping region being less than the doping ion concentration of the second doping region; Wherein, the third doping region includes: a first region, contacting the second doping region, the first region including the first doping ions; a second region, serving as a halo region, located below and in contact with the first region, the second region comprising the second dopant ions, and a dopant ion concentration of the first region being greater than a dopant ion concentration of the second region; The third doped region is provided on and only on a side of the transistor device away from the anti-fuse device, and neither the first region nor the second region is provided on a side of the transistor device close to the anti-fuse device.

2. The antifuse structure according to claim 1, wherein: In a direction from the transistor device to the anti-fuse device, the first region protrudes beyond the second doped region; The second region is located below a portion of the first region protruding from the second doping region.

3. The antifuse structure according to claim 1, wherein: The first region further includes third doping ions, and the third doping ions are used to hinder the diffusion of the first doping ions.

4. The antifuse structure according to claim 3, wherein: The first doping ions are group IIIA ions, the second doping ions are group VA ions, and the third doping ions are group IVA ions.

5. The antifuse structure according to any one of claims 1 to 4, characterized in that: The anti-fuse device includes an anti-fuse dielectric layer located on the substrate, and an anti-fuse gate layer located on the anti-fuse dielectric layer; The transistor device includes a transistor dielectric layer located on the substrate and a transistor gate layer located on the transistor dielectric layer. The thickness of the transistor dielectric layer is equal to the thickness of the antifuse dielectric layer.

6. A method for forming an antifuse structure, characterized in that: The steps include: providing a substrate; forming an anti-fuse device and a transistor device, both of which are at least partially located on the substrate, wherein the transistor device includes a first doping region, a second doping region, and a third doping region, all of which are located within the substrate, wherein the first doping region is electrically connected to the anti-fuse device, the second doping region is located on a side of the transistor device away from the anti-fuse device, and the third doping region is located on a side of the transistor device away from the anti-fuse device, wherein the first doping region and the second doping region both include first doping ions, the third doping region includes at least the first doping ions and second doping ions having a conductivity type different from that of the first doping ions, and the doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region; Wherein, the third doping region includes: a first region, contacting the second doping region, the first region including the first doping ions; a second region, serving as a halo region, located below and in contact with the first region, the second region comprising the second dopant ions, and a dopant ion concentration of the first region being greater than a dopant ion concentration of the second region; The third doped region is provided on and only on a side of the transistor device away from the anti-fuse device, and neither the first region nor the second region is provided on a side of the transistor device close to the anti-fuse device.

7. The method for forming an antifuse structure according to claim 6, wherein: forming an antifuse device and a transistor device each at least partially located on the substrate, comprising: forming an antifuse dielectric layer, an antifuse gate layer located above the antifuse dielectric layer, a transistor dielectric layer, and a transistor gate layer located above the transistor dielectric layer on the substrate; forming the third doped region in the substrate; The first doped region and the second doped region are formed in the substrate to form the anti-fuse device including the anti-fuse dielectric layer and the anti-fuse gate layer, and to form the transistor device including the transistor dielectric layer, the transistor gate layer, the first doped region, the second doped region and the third doped region.

8. The method for forming an antifuse structure according to claim 7, wherein: The specific steps of forming the third doped region in the substrate include: implanting the first dopant ions into the first region within the substrate; The second dopant ions are implanted into the second region in the substrate.

9. The method for forming an antifuse structure according to claim 8, wherein: Before implanting the first dopant ions into the first region in the substrate, the method further includes the following steps: Third doping ions are implanted into the first region, where the third doping ions are used to hinder diffusion of the first doping ions.

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