Error injection method, electronic device and storage medium

Abstract

The present invention relates to the field of chip verification technology, and in particular to a method, electronic device, and storage medium for error injection. The method initializes each target model, including: the target model obtains a model instance of the error injection model; the target model registers all of the target model's own hardware error types to the error injection model through the model instance; the stimulus end injects some or all of all registered hardware error types into the error injection model and saves the information; when the target model is simulated or tested and reaches an error occurrence point, the hardware error type saved in the error injection model is read, and if the reading is successful, it is determined that a corresponding hardware error has occurred; otherwise, no corresponding hardware error has occurred. This achieves the purpose of simulating real errors and ensuring the functional integrity of the target model.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to an error injection method, electronic equipment and storage medium. Background Art

[0002] With the recent development of the chip industry, chip structures have become increasingly complex, and traditional design methods are no longer able to meet the demands of new product designs. This has led to the emergence of a new design methodology and concept: Electronic System Level (ELS) design. The core of the ELS design methodology is a joint HW / SW development environment, the ultimate output of which is a system behavioral model. ELS design features functional verification, performance evaluation, partitioning, pre-development of software, risk identification, accelerated schedules, and the deployment of a system-level testbed. The main application areas of ELS design include: First, Performance / Architecture Models (CA / AT): for architectural exploration, evaluation, and optimization during the architectural design phase. Second, Functional Models (TL): for pre-development of software, parallel development of hardware and software, and shortened R&D cycles. Third, Power Models: for power consumption estimation. Fourth, System Level Design: for hardware and software co-design, verification, and partitioning. Fifth, Hybrid Co-simulation: including functional and performance simulation. Sixth, High-Level Synthesis (HLS): using tools to directly synthesize C++ / SystemC + TLM2.0 models into RTL code.

[0003] The functional model (TL) models the chip's functionality and does not model the physical error mechanisms of the hardware. Actual physical chips will produce certain errors. However, the target model does not contain real hardware errors such as physical wiring errors, false transmission errors, and electromagnetic errors. To ensure verification integrity, the functional model is used as the target model. The target model is used to simulate the correctness of the target model's internal error handling mechanisms when the corresponding hardware errors occur. In other words, to ensure functional integrity, functional verification requires timely "errors."

[0004] Existing techniques typically use active error injection. However, because the stimulus and model sides operate in different clock domains—the stimulus side in the C++ thread domain, and the model side in the model clock domain—active error injection makes it difficult to generate errors at the target model's point of failure. Therefore, a method that can simulate real errors to ensure the functional integrity of the target model is urgently needed. Summary of the Invention

[0005] In response to the above technical problems, the present invention adopts a technical solution: an error injection method, the method comprising the following steps:

[0006] S100, obtaining a stimulus end and a model end, wherein the model end includes an error injection model and a set of N target models LTset; wherein the error injection model includes a registration error interface registerError and an acquisition error interface getError; the i-th target model LT in LTset i is the functional model of the chip, LT i ErrTypeSet includes a set of M preset hardware error types i , where the qth hardware error type is ErrType i,q ;ErrType i,q In LT i The set of K error occurrence points ErrOccSet is preset in i,q , where N, M, and K are greater than or equal to 1, i ranges from 1 to N, and q ranges from 1 to M.

[0007] S200, initialize each target model, where LT i The initialization steps include:

[0008] S210,LT i Get the model instance inst of the fault injection model.

[0009] S220,LT i Register ErrTypeSet to the error injection model through registerError of inst i .

[0010] S300, perform error injection on each target model, where LT i The error injection steps include: the stimulus end sets ErrTypeSet i Inject the M1 hardware error type into the error injection model and save it as LT i Error collection LT i _subErrSet, where LT i _subErrSet is ErrTypeSet i A subset of , 0≤M1≤M.

[0011] S400, when LT i During simulation or testing, the ErrOccSet i,q When the error occurs in the i,q Automatically call getError; getError reads the LT saved in the error injection model through inst i_subErrSet, when ErrType i,q With LT i When the hardware error matching in _subErrSet succeeds, it is determined that ErrType has occurred i,q Otherwise, ErrType i,q The error did not occur.

[0012] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0013] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0014] The present invention has at least the following beneficial effects:

[0015] The method provided by the present invention obtains the errors stored by the error injection model according to the error occurrence point of the target model, and judges whether the specified type of error has occurred based on the error acquisition result. Through this passive error injection method, the problem of the timing of active error injection is solved, and the effect of timely error injection into the target model is achieved without modeling the hardware physical error mechanism, thereby simulating real errors and ensuring the functional integrity of the target model. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flow chart of an error injection method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] See also Figure 1 , which shows an error injection method, the method comprising the following steps:

[0020] S100, obtaining a stimulus end and a model end, wherein the model end includes an error injection model and a set of N target models LTset; wherein the error injection model includes a registration error interface registerError and an acquisition error interface getError; the i-th target model LT in LTset i is the functional model of the chip, LT i ErrTypeSet includes a set of M preset hardware error types i , where the qth hardware error type is ErrType i,q ;ErrType i,q In LT i The set of K error occurrence points ErrOccSet is preset in i,q , where N, M, and K are greater than or equal to 1, i ranges from 1 to N, and q ranges from 1 to M.

[0021] The stimulus end is used to initiate stimulus that generates a certain error.

[0022] The model side is the object of the current simulation. The stimulus side and the model side are in different clock domains. The stimulus side is in the C++ thread domain, and the model side is in the model clock domain.

[0023] The fault injection model is used to store the error types registered by each target model and the errors injected by the stimulus. This allows the target model to retrieve the errors stored in the fault injection model by calling the error acquisition interface when an error occurs during simulation or testing. The fault injection model defines the operations or logical functions performed by the current model, interface specifications, and parameterized design. After the fault injection model is instantiated, the interface specifications in the model instance enable interaction between the current model and other models.

[0024] The target model is a design model of a virtual chip to be simulated or tested.

[0025] Optionally, the target model is a functional model. Preferably, the target model is a loosely-timed model (LT). The LT model is a type of functional model.

[0026] Error occurrence points are pre-defined conditions or event locations in chip design that determine whether corresponding errors occur during simulation or testing. Error occurrence points are used to assess whether the target model can respond correctly and take appropriate measures when errors occur, ensuring system stability and reliability.

[0027] The hardware error type refers to the actual error type generated by the hardware chip, such as a physical connection error, a mis-transmission error, an electromagnetic error, a CRC error, or a bus-off error.

[0028] Among them, the registration error interface registerError is called by the target model through the model instance inst and reads the saved error.

[0029] S200, initialize each target model, where LT i The initialization steps include:

[0030] S210,LT i Get the model instance inst of the fault injection model.

[0031] Optionally, the model instances of the N target models LT are different, or may be partially the same and partially different, and configured according to user needs.

[0032] Preferably, N target models LT share one inst.

[0033] After initialization, each target model registers its own error type with the error injection model, ensuring isolation of error types across target models. Each target model can only receive errors related to its registered error type, and cannot receive errors across target models. This isolation ensures that injected error types are only received by target models that have registered the corresponding error type, ensuring accurate and orderly verification.

[0034] S220,LT i Register ErrTypeSet to the error injection model through registerError of inst i .

[0035] Among them, LT i Set all M hardware error types ErrTypeSet i All are registered in the fault injection model to prepare for the next fault injection.

[0036] S300, perform error injection on each target model, where LT i The error injection steps include: the stimulus end sets ErrTypeSet i Inject the M1 hardware error type into the error injection model and save it as LT i Error collection LT i _subErrSet, where LT i _subErrSet is ErrTypeSet iA subset of , 0≤M1≤M.

[0037] Optionally, LT i The fault injection steps in LT i It is completed during the initialization process, or during simulation or testing.

[0038] S400, when LT i During simulation or testing, the ErrOccSet i,q When the error occurs in the i,q Automatically call getError; getError reads the LT saved in the error injection model through inst i _subErrSet, when ErrType i,q With LT i When the hardware error matching in _subErrSet succeeds, it is determined that ErrType has occurred i,q Otherwise, ErrType i,q The error did not occur.

[0039] For errors caused by the physical characteristics of the chip, the method provided by the present invention obtains the errors stored by the error injection model according to the error occurrence point of the target model, and determines whether a specified type of error has occurred based on the error acquisition result. Through this passive error injection method, the problem of the timing of active error injection is solved, and the effect of timely error injection into the target model is achieved without modeling the hardware physical error mechanism, simulating real errors and ensuring the integrity of the target model function.

[0040] From the perspective of error frequency, the present invention further abstracts error types, with each error type supporting two error modes: random error mode and continuous error mode. The random error mode is an error that occurs with a preset probability, and is used to simulate random errors in a real hardware environment. The continuous error mode is a continuous, uninterrupted generation of a preset number of identical errors, and is used to simulate the continuous occurrence of the same error in a real hardware environment. Without modeling the hardware error mechanism in the target model, this facilitates the simulation of random or continuous errors, and further models the error handling mechanism of the target model.

[0041] Methods of reclassifying the error generation pattern by other means and injecting the error type and its pattern attribute data into the model at the same time also fall within the protection scope of the present invention.

[0042] As a preferred embodiment, in S400, when ErrType i,q When it is a random error, LTi Call getError to get errors at a preset frequency. Errors occur randomly under the preset frequency.

[0043] As a preferred embodiment, when ErrType i,q When the error is continuous, LT i Call getError num times to get num errors of the same type according to the preset number of consecutive errors num. Optional, when ErrType is specified i,q When the random error frequency is 0, the current error will not be obtained after num errors of the same error type.

[0044] As a preferred embodiment, after num identical errors are obtained, if an error of the same error type is obtained again and the preset error type is a random error, the error obtained again is a random error.

[0045] As a preferred embodiment, in S300, ErrTypeSet i The M1 hardware error types are injected into the error injection model by writing registers.

[0046] Optionally, the error injection model includes multiple registers, and the stimulus end injects corresponding errors into the error injection model by writing to the registers. The multiple registers have the same function, and the more registers there are, the more error types are supported.

[0047] As a preferred embodiment, the fields of the register include an error type ID field idx, a continuous error number field cst, and a random error frequency field rand.

[0048] Among them, idx is the unique identifier of the error type, and idx is globally unique.

[0049] Where cst is the number of consecutive errors. 0 indicates no consecutive errors, and non-zero indicates the number of consecutive errors.

[0050] Where rand is the frequency of random errors. 0 indicates no random errors. If it is non-zero, 1 / rand indicates the frequency of errors. For example, during the period of obtaining rand errors, one random error is generated.

[0051] When the fields of the register also include other fields, it also falls within the protection scope of the present invention.

[0052] As a preferred embodiment, in S300, ErrTypeSet iThe M1 hardware error types are injected into the error injection model by calling the injection function.

[0053] In a preferred embodiment, the model side also includes a jump module, and the step of injecting by calling the injection function further includes: the stimulus side initiating a request to inject an error to the jump module on the model side; the jump module receiving and parsing the injection function data packet sent by the test side, and sending the error attribute data obtained by the parsing to the error injection model for storage. After the model side injects the error into the target model, a success or failure result is returned to the stimulus side.

[0054] Optionally, the error attribute data includes the model instance name, the unique identifier of the error type, the random error frequency and the number of consecutive errors. When the error attribute data includes other attribute data, it also falls within the protection scope of the present invention.

[0055] Methods for implementing the function of injecting the error type of the excitation end into the error injection model and saving the result by other means also fall within the protection scope of the present invention.

[0056] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0057] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0058] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0059] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for error injection, characterized in that: The method comprises the following steps: S100, obtaining a stimulus end and a model end, wherein the model end includes an error injection model and a set of N target models LTset; wherein the error injection model includes a registration error interface registerError and an acquisition error interface getError; the i-th target model LT in LTset i is the functional model of the chip, LT i ErrTypeSet includes a set of M preset hardware error types i , where the qth hardware error type is ErrType i,q ;ErrType i,q In LT i The set of K error occurrence points ErrOccSet is preset in i,q , where N, M, and K are greater than or equal to 1, i ranges from 1 to N, and q ranges from 1 to M; S200, initialize each target model, where LT i The initialization steps include: S210,LT i Obtain a model instance inst of the fault injection model; S220,LT i Register ErrTypeSet to the error injection model through registerError of inst i ; S300, perform error injection on each target model, where LT i The error injection steps include: the stimulus end sets ErrTypeSet i Inject the M1 hardware error type into the error injection model and save it as LT i Error collection LT i _subErrSet, where LT i _subErrSet is ErrTypeSet i A subset of , 0≤M1≤M; S400, when LT i During simulation or testing, the ErrOccSet i,q When the error occurs in the i,q Automatically call getError; getError reads the LT saved in the error injection model through inst i _subErrSet, when ErrType i,q With LT i When the hardware error matching in _subErrSet succeeds, it is determined that ErrType has occurred i,q Otherwise, ErrType i,q The error did not occur.

2. The method according to claim 1, characterized in that In S400, when ErrType i,q When it is a random error, LT i Call getError to get errors according to the preset frequency.

3. The method according to claim 1, characterized in that When ErrType i,q When the error is continuous, LT i Call getError num times to obtain num errors of the same type, based on the preset number of consecutive errors num.

4. The method according to claim 3, characterized in that After num identical errors are obtained, if an error of the same error type is obtained again and the preset error type is a random error, the error obtained again is a random error.

5. The method according to claim 1, wherein S300 Lieutenant General ErrTypeSet i The M1 hardware error types are injected into the error injection model by writing registers.

6. The method according to claim 5, characterized in that The fields of the register include an error type ID field idx, a continuous error number field cst, and a random error frequency field rand.

7. The method according to claim 1, characterized in that S300 Lieutenant General ErrTypeSet i The M1 hardware error types are injected into the error injection model by calling the injection function.

8. The method according to claim 7, characterized in that The model end also includes a jump module, and the step of injecting by calling the injection function also includes: the stimulation end initiates a request to inject an error to the jump module of the model end; the jump module receives the data packet of the injection function sent by the test end and parses it, and sends the error attribute data obtained by the analysis to the error injection model for storage.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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