Back contact solar cells and photovoltaic modules

Abstract

The present application provides a back-contact solar cell and photovoltaic module, belonging to the field of solar cell technology. The back-contact solar cell includes a silicon wafer, and an electrode collection area is formed on the back of the silicon wafer. The electrode collection area includes a plurality of first polarity carrier collection areas and a plurality of second polarity carrier collection areas of opposite polarities that are alternately distributed along a first direction, and an isolation area is provided between adjacent first polarity carrier collection areas and second polarity carrier collection areas; wherein, the width of at least one of the two edge carrier collection areas adjacent to the edge of the silicon wafer along the first direction is greater than the width of any inner carrier collection area of ​​the same polarity away from the edge of the silicon wafer. The present application promotes carrier collection in the edge area of ​​the silicon wafer by controlling the width of the edge carrier collection area to be greater than the width of the inner carrier collection area of ​​the same polarity, and adjusting the position of the metal electrode of the edge carrier collection area, which is beneficial to improving the photoelectric conversion efficiency of the battery.

Description

Technical Field

[0001] At least one embodiment of the present application relates to a solar cell, and more particularly to a back-contact solar cell and a photovoltaic module. Background Art

[0002] In the manufacturing process of back contact (BC) solar cells, the layout structure design on the back of the cell plays a vital role in achieving high photoelectric conversion efficiency, including parameters such as pitch width (usually considered to be the sum of the widths of one multi-carrier region, one minority-carrier region and two isolation regions, or the distance from the center of the width of a multi-carrier region to the center of the width of another multi-carrier region adjacent to a minority-carrier region, or the distance from the center of the width of a minority-carrier region to the center of the width of another minority-carrier region adjacent to a multi-carrier region), minority-carrier region width, multi-carrier region width, and isolation region (i.e., gap region) width. In the manufacturing process of the cell, there are often certain defects in the edge area of ​​the silicon wafer, such as those that are not conducive to edge carrier collection, and these defects will have an adverse effect on cell performance. Summary of the invention

[0003] In order to reduce this effect, the edge area of ​​the silicon wafer is usually designed as an isolation area. However, due to the limitations of different types of silicon wafer sizes and pitch widths, the width of the edge area of ​​the silicon wafer may not be enough to accommodate a complete emitter or back surface field (BSF) structure, or may exceed the width of a complete emitter or back surface field (BSF). In these cases, if the entire edge area of ​​the silicon wafer is designed as an isolation area, this design strategy may encounter some limitations in the pursuit of high-efficiency photoelectric conversion.

[0004] For carrier collection, if no emitter or back surface field is formed at the edge of the silicon wafer, the edge doping concentration is low, resulting in higher resistivity, poor carrier collection ability, poor long-wave absorption ability, and a decrease in fill factor. Therefore, increasing the area ratio of the carrier collection area at the edge of the silicon wafer can increase the fill factor and thus improve the photoelectric conversion efficiency. In addition, for minority carriers, their lifetime is shorter than that of majority carriers, and their diffusion length is shorter than that of majority carriers. Since the defect density at the edge of the silicon wafer is higher than that in other areas of the silicon wafer, the probability of recombination is higher, resulting in poor effect of edge minority carrier collection, which limits the improvement of photoelectric conversion efficiency.

[0005] In view of this, the present application provides a back-contact solar cell and a photovoltaic module to improve the collection efficiency of carriers in the edge region of the silicon wafer and enhance the photoelectric conversion efficiency of the solar cell.

[0006] According to an embodiment of one aspect of the present application, there is provided a back-contact solar cell, comprising:

[0007] A silicon wafer, wherein an electrode collecting region is formed on the back side of the silicon wafer, the electrode collecting region comprising a plurality of first polarity carrier collecting regions and a plurality of second polarity carrier collecting regions of opposite polarities alternately distributed along a first direction, and an isolation region is provided between adjacent first polarity carrier collecting regions and second polarity carrier collecting regions; wherein a width of at least one of the two edge carrier collecting regions adjacent to the edge of the silicon wafer along the first direction is greater than a width of any inner carrier collecting region of the same polarity away from the edge of the silicon wafer.

[0008] Preferably, the width of each of the two edge carrier collection regions adjacent to the edge of the silicon wafer along the first direction is greater than the width of any inner carrier collection region of the same polarity away from the edge of the silicon wafer.

[0009] The back-contact solar cell further includes a non-electrode collecting region, which is located outside the electrode collecting region and at the edge of the silicon wafer.

[0010] According to a preferred embodiment of the present application, the width range of the non-electrode collection area is 30μm~500μm. In theory, the smaller the non-electrode collection area, the better, but the requirements for the process will be greatly increased. For example, the passivation quality of the passivation film layer at the edge of the silicon wafer, the thickness of the doping film layer at the edge of the silicon wafer, and the doping concentration distribution at the edge of the silicon wafer will have extremely high requirements, which will lead to a great increase in process costs, while the efficiency improvement is limited, resulting in a great increase in costs. The width range of the non-electrode collection area is controlled at 30μm~500μm. On the one hand, the area of ​​the silicon wafer can be used as much as possible to improve the overall conversion efficiency of the battery, and on the other hand, it will not increase the process cost too much.

[0011] Preferably, each non-electrode collecting region is adjacent to a first polarity carrier collecting region, and the width of at least one first polarity carrier collecting region adjacent to the non-electrode collecting region is greater than the width of any first polarity carrier collecting region away from the non-electrode collecting region, and any first polarity carrier collecting region is a first polarity carrier collecting region located inside.

[0012] Preferably, the first polarity carrier collection region is a minority carrier region, the second polarity carrier collection region is a majority carrier region, and each non-electrode collection region is adjacent to a minority carrier region, which can shorten the transmission path of minority carriers at the edge of the silicon wafer and reduce recombination. The non-electrode collection regions are adjacent to an edge minority carrier region that is larger than the inner minority carrier region, which will further shorten the transmission path of minority carriers at the edge of the silicon wafer and increase the collection rate of minority carriers. At the same time, due to the longer lifetime of majority carriers and the longer diffusion length, the majority carrier loss generated is smaller, thereby further improving the photoelectric conversion efficiency of the battery.

[0013] Preferably, the width of the first polarity carrier collection area adjacent to the non-electrode collection area at the two edges of the silicon wafer is greater than the width of any first polarity carrier collection area away from the non-electrode collection area. Such a setting can better collect the carriers at the two edges of the silicon wafer and further improve the overall conversion efficiency of the battery.

[0014] According to a preferred embodiment of the present application, the width of the first polarity carrier collection region located at the edge is less than twice the width of the first polarity carrier collection region located on the inside, and the width of the first polarity carrier collection region located at the edge cannot be too wide, otherwise more carriers will be recombined and cannot be collected by the electrode, resulting in a decrease in open circuit voltage, and at the same time will lead to an increase in series resistance, resulting in a decrease in conversion efficiency, and there will also be adverse effects such as an increase in local photodegradation effect and local hot spot effect caused by doping.

[0015] According to a preferred embodiment of the present application, when the sum of half the width of the first polarity carrier collection region located at the edge and the width of the non-electrode collection region is greater than 300 μm, the first polarity carrier collection region located at the edge includes two first fine grids distributed along the first direction, and the two first fine grids divide the first polarity carrier collection region located at the edge into three regions of equal area. The width and distribution of the first fine grids determine the coverage range of the carriers that can be collected, especially for minority carriers, this collection ability is particularly prominent. When the width of the first polarity carrier collection region located at the edge is large, the first fine grid of a specific width range has a decreased carrier collection ability for the wider first polarity carrier collection region. On the one hand, the number of first fine grids on the first polarity carrier collection region located at the edge can be increased, or the width of the first fine grid on the first polarity carrier collection region located at the edge can be increased. For example, by adding a first fine grid, two first fine grids divide the first polarity carrier collection area at the edge into three areas of equal area, which can fully collect the carriers in the first polarity carrier collection area at the edge, and reduce the current imbalance caused by excessive current of a single fine grid with the same width, and the width of the first fine grid is less than or equal to 80μm. For another example, the ratio of the width of the first fine grid on the first polarity carrier collection area at the edge along the first direction to the width of the first polarity carrier collection area at the edge is controlled to be 5% to 80%, which can reduce the transmission path of carrier collection and reduce the large current transmitted on the narrower gate line, causing the current imbalance.

[0016] According to a preferred embodiment of the present application, the first fine gate extends along a second direction perpendicular to the first direction in the plane of the silicon wafer; the distance between the first fine gate and the edge of the silicon wafer along the first direction and the center line of the second polarity carrier collection region adjacent to the first polarity carrier collection region located at the edge along the second direction differs by no more than ±20%. The carrier collection on both sides of the fine gate on the carrier collection region at the edge is balanced to minimize the difference in carrier collection on both sides.

[0017] According to a preferred embodiment of the present application, the ratio of the length of the first polarity carrier collection region located at the edge along the second direction to the length of the first polarity carrier collection region located at the inner side along the second direction is 0.95~1.00. The above arrangement can adapt to the situation that along the second direction, the edge area of ​​the silicon wafer is shorter than the first polarity carrier collection region located at the inner side due to the chamfering of the silicon wafer; or the first polarity carrier collection region located at the edge has a larger area due to its larger width, thereby avoiding the problem of battery current mismatch caused by excessive current in the first polarity carrier collection region located at the edge.

[0018] According to a preferred embodiment of the present application, the ratio of the distance between the edge of the first fine grid extending along the second direction on the first polarity carrier collection region located at the edge and the nearest silicon wafer edge to the distance between the edge of the second fine grid extending along the second direction on the first polarity carrier collection region located inside and the nearest silicon wafer edge is 0.8-1.2. On the basis of avoiding the battery current mismatch caused by the excessive current in the first polarity carrier collection region located at the edge, the collection of carriers at the chamfer of the silicon wafer edge is optimized.

[0019] The first polarity carrier collection region can also be a majority carrier collection region, and the corresponding second polarity carrier collection region is a minority carrier collection region. The first polarity carrier collection region located at the edge is a majority carrier collection region, which has a higher doping concentration than the silicon wafer substrate, reduces the contact resistance, and can better collect the photogenerated carriers generated by the long-wavelength light absorbed by the front and back of the silicon wafer.

[0020] According to the back-contact solar cell provided in the above-mentioned embodiment of the present application, by controlling the width of the edge carrier collection area to be larger than the width of the inner carrier collection area of ​​the same polarity on the inner side of the silicon wafer, and adjusting the position, number and width of the metal electrodes in the edge carrier collection area, the transmission path length of the carriers generated at the edge of the silicon wafer can be reduced, and the recombination of carriers can be reduced, so as to effectively improve the carrier collection efficiency in the edge area of ​​the silicon wafer, thereby improving the photoelectric conversion efficiency of the battery.

[0021] According to an embodiment of another aspect of the present application, a photovoltaic module is provided, comprising the above-mentioned back-contact solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0023] Figure 1 A schematic top view of the back side of a back-contact solar cell provided in an embodiment of the present application;

[0024] Figure 2 A schematic top view of a local area of ​​the back side of a back contact solar cell provided in an embodiment of the present application;

[0025] Figure 3 A diagram showing the test results of the light beam induced current (LBIC) at the edge region of the silicon wafer of an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the design of a first fine gate of a first polarity carrier collection region located at an edge provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the edge area of ​​a silicon wafer provided in an embodiment of the present application;

[0028] Figure 6 A schematic cross-sectional view of a back-contact solar cell provided in an embodiment of the present application; and

[0029] Figure 7 A partial top view schematic diagram of a back-contact solar cell provided by another embodiment of the present application;

[0030] Description of reference numerals:

[0031] 1- Silicon wafer;

[0032] 10-electrode collection area;

[0033] 11- a first polarity carrier collection region;

[0034] 12- a second polarity carrier collection region;

[0035] 13-Isolation area;

[0036] 2A-first fine grid;

[0037] 2B-second fine grid;

[0038] 20- non-electrode collection area;

[0039] W1-width of non-electrode collection area;

[0040] W2-the width of the first polarity carrier collection region located at the edge;

[0041] W3 - width of the isolation zone;

[0042] W4-the width of the first polarity carrier collection region located inside;

[0043] d1-the distance between the edge of the first fine gate extending along the second direction and the closest edge of the silicon wafer;

[0044] d2-the distance between the edge of the second fine gate extending along the second direction on the inner first polarity carrier collection region and the nearest edge of the silicon wafer;

[0045] L1-the distance between the first fine gate and the center line of the second polarity carrier collecting region adjacent to the first polarity carrier collecting region located at the edge along the second direction;

[0046] L2-the distance between the first fine gate and the edge of the silicon wafer along the first direction;

[0047] 14-a first doped semiconductor portion;

[0048] 15-a second doped semiconductor portion;

[0049] 16- a first electrode;

[0050] 17- Second electrode. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the application thorough and complete, and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout.

[0052] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "include", "comprising", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0053] In the related art, during the manufacturing process of back-contact solar cells, defects in the edge area of ​​the silicon wafer and the problem of adapting the width of the emitter or back surface field (BSF) lead to insufficient utilization of the edge area of ​​the silicon wafer, making the battery design lack of flexibility and unable to fully collect the carriers generated in the edge area of ​​the silicon wafer, or failing to maximize the effective area of ​​the battery. Specifically, if the edge isolation area (edge ​​gap area) is too wide, it will affect the collection of carriers in the edge area, and will also reduce the area of ​​the truly effective electrode collection area, resulting in limited photoelectric conversion efficiency and area utilization efficiency, increased manufacturing costs, and the stability of battery performance may be affected due to the presence of edge defects.

[0054] In view of this, in order to optimize the geometric structure of the back-contact solar cell, improve the carrier collection efficiency in the edge area, and enhance the overall performance of the back-contact solar cell, the present application provides a back-contact solar cell and a photovoltaic module.

[0055] According to an exemplary embodiment of the present application, the present application provides a back contact solar cell, referring to Figure 1 , Figure 2 As shown, including:

[0056] A silicon wafer 1, wherein two non-electrode collecting regions 20 and an electrode collecting region 10 located between the two non-electrode collecting regions 20 are formed on the back side of the silicon wafer 1, wherein the electrode collecting region 10 includes a plurality of first polarity carrier collecting regions 11 and a plurality of second polarity carrier collecting regions 12 alternately distributed along a first direction, and an isolation region 13 is provided between adjacent first polarity carrier collecting regions 11 and second polarity carrier collecting regions 12; wherein a width of at least one of the two edge carrier collecting regions adjacent to the edge of the silicon wafer along the first direction is greater than a width of any inner carrier collecting region of the same polarity away from the edge of the silicon wafer.

[0057] According to an embodiment of the present application, each non-electrode collecting region 20 is adjacent to a first polarity carrier collecting region 11, and the width of at least one first polarity carrier collecting region 11 adjacent to the non-electrode collecting region 20 is greater than the width of any first polarity carrier collecting region 11 away from the non-electrode collecting region 20, one of the first polarity carrier collecting regions 11 is a first polarity carrier collecting region located at the edge, and any first polarity carrier collecting region 11 is a first polarity carrier collecting region located on the inside.

[0058] According to another embodiment of the present application, the widths of the first polarity carrier collecting regions 11 adjacent to the non-electrode collecting regions 20 at two edges of the silicon wafer are greater than the widths of any first polarity carrier collecting regions 11 away from the non-electrode collecting regions 20, one of the first polarity carrier collecting regions 11 is a first polarity carrier collecting region located at the edge, and any first polarity carrier collecting region 11 is a first polarity carrier collecting region located on the inner side.

[0059] According to another embodiment of the present application, a non-electrode collecting region 20 is adjacent to a first polarity carrier collecting region 11, and another non-electrode collecting region 20 is adjacent to a second polarity carrier collecting region 12; and the width of a first polarity carrier collecting region 11 adjacent to the non-electrode collecting region 20 is greater than the width of any first polarity carrier collecting region 11 away from the non-electrode collecting region 20, and any first polarity carrier collecting region 11 is a first polarity carrier collecting region located on the inner side; and / or, the width of a second polarity carrier collecting region 12 adjacent to the non-electrode collecting region 20 is greater than the width of any second polarity carrier collecting region 12 away from the non-electrode collecting region 20, and any second polarity carrier collecting region 12 is a second polarity carrier collecting region located on the inner side of the silicon wafer.

[0060] According to an embodiment of the present application, the silicon wafer 1 has a front side and a back side opposite to the front side, the front side of the silicon wafer 1 corresponds to the light-facing side of the back-contact solar cell, and the back side of the silicon wafer 1 corresponds to the back-light side of the back-contact solar cell. The front side of the silicon wafer 1 may be a velvet surface to improve the light trapping effect of the front side.

[0061] According to an embodiment of the present application, the shape of the silicon wafer 1 is a rectangle, and the side length of the rectangle ranges from 156mm to 260mm. The side length of the rectangle can be, for example, 156mm, 182mm, 191mm, 210mm, 220mm, 260mm, but is not limited to the listed values.

[0062] According to an embodiment of the present application, by controlling the width W2 of the first polarity carrier collection region located at the edge to be larger than the width W4 of the first polarity carrier collection region located on the inside, the transmission path of the carriers generated at the edge of the silicon wafer can be reduced, and the recombination of the carriers generated at the edge of the silicon wafer can be reduced, so as to effectively improve the carrier collection efficiency in the edge area of ​​the silicon wafer, thereby improving the photoelectric conversion efficiency of the battery.

[0063] According to an embodiment of the present application, the first polarity carrier collection region 11 is a minority carrier region, and the edge minority carrier region, that is, the width W2 of the first polarity carrier collection region located at the edge can be, for example, 640 μm, and the inner minority carrier region, that is, the width W4 of the first polarity carrier collection region located at the inner side can be, for example, 540 μm.

[0064] According to the embodiment of the present application, the width of the minority carrier region at the edge is greater than the width of the minority carrier region at the inner side, so that the distance for the minority carriers at the edge of the silicon wafer to be transmitted to the emitter becomes shorter, so as to improve the collection efficiency of the minority carriers at the edge of the silicon wafer; however, if the width of the minority carrier region at the edge is too large, the minority carriers generated in the minority carrier region at the edge may not be effectively collected by the first fine gate on the minority carrier region, which is not conducive to improving the efficiency of the battery. Therefore, the width of the minority carrier region at the edge is set to be less than 2 times the width of the inner minority carrier region.

[0065] Figure 3 This is a diagram showing the light beam induced current (LBIC) test results of the edge region of a silicon wafer according to an embodiment of the present application.

[0066] refer to Figure 3 As shown in the figure, after the LBIC test of the back-contact solar cell, it was found that the current intensity at the edge of the back-contact solar cell was generally lower than that at the inner side of the cell. This phenomenon of low current at the edge of the cell, especially in the area with a width of about 360μm from the very edge of the cell to the edge of the cell, shows a gradually increasing trend of current intensity. This may be due to various factors in the cell manufacturing process; for example, the edge area may have an incomplete edge passivation film layer, uneven doping concentration, and lint at the edge due to slight differences in deposition equipment, as well as subsequent laser and wet process treatments. These defects may increase the recombination of carriers, so that the carriers generated at the edge cannot be transmitted and collected through the adjacent electrodes, thereby reducing the open circuit voltage, short-circuit current density, and pseudo fill factor (Pseudo FillFactor, pFF) of the cell.

[0067] According to an embodiment of the present application, the width of the non-electrode collection area 20 ranges from 30 μm to 500 μm, for example, 30 μm, 50 μm, 100 μm, 150 μm, 200 μm, 300 μm, 360 μm, 400 μm, 500 μm, but not limited to the values ​​cited. By using the area at the edge of the silicon wafer with more defects and severe carrier recombination as the non-electrode collection area 20, the carrier collection at the edge of the silicon wafer is increased to improve the pseudo fill factor (pFF) and short-circuit current density of the battery, which is beneficial to improve the photoelectric conversion efficiency of the battery.

[0068] According to an embodiment of the present application, the width W1 of the non-electrode collecting region is greater than the width W3 of the isolation region.

[0069] According to an embodiment of the present application, the width W3 of the isolation region is less than or equal to 200 μm, and the width W3 of the isolation region is not 0. For example, the width W3 of the isolation region is 50 μm, 100 μm, 150 μm, 180 μm, or 200 μm, but is not limited to the listed values.

[0070] According to an embodiment of the present application, in order to effectively collect the carriers generated by the first polarity carrier collection region 11 located at the edge, two first fine grids may be provided on the first polarity carrier collection region 11 located at the edge. Specifically, when the sum of half of the width W2 of the first polarity carrier collection region located at the edge and the width W1 of the non-electrode collection region is greater than 300 μm, the first polarity carrier collection region 11 located at the edge includes two first fine grids distributed along the first direction, and the two first fine grids divide the first polarity carrier collection region 11 located at the edge into three regions of equal area. By setting two first fine gates on the first polarity carrier collection area 11 located at the edge, the transmission path of the carriers in the first polarity carrier collection area 11 located at the edge can be reduced, so as to improve the carrier collection efficiency of the first polarity carrier collection area 11 located at the edge, thereby improving the photoelectric conversion efficiency of the battery, and avoiding the problem of excessive current in the first polarity carrier collection area 11 located at the edge, which causes current mismatch in the battery when only one first fine gate is set on the first polarity carrier collection area 11 located at the edge.

[0071] According to an embodiment of the present application, the width of the two first fine gates on the first polarity carrier collection region 11 located at the edge is less than or equal to 80μm, for example, it can be 20μm, 30μm, 40μm, 50μm, 60μm, 65μm, 70μm, 80μm, but is not limited to the listed values.

[0072] According to an embodiment of the present application, the width of the first polarity carrier collecting region 11 located at the edge is greater than the width of the first polarity carrier collecting region 11 located on the inside. In order to effectively collect the carriers of the first polarity carrier collecting region 11 located at the edge without increasing the number of first fine gates, the width of the first fine gate on the first polarity carrier collecting region 11 located at the edge can be increased.

[0073] According to the embodiment of the present application, if the ratio of the width of the first fine grid to the width of the first polarity carrier collection region 11 located at the edge is less than 10%, it is not conducive to the collection of carriers. By widening the gate line to reduce the carrier transmission path, the carrier collection can be increased; if the ratio of the width of the first fine grid to the width of the first polarity carrier collection region 11 located at the edge is too large, the material required for manufacturing the first fine grid is increased, which is not conducive to controlling the cost. In the case where a first fine grid is arranged on the first polarity carrier collection region 11 located at the edge, the ratio of the width of the first fine grid along the first direction on the first polarity carrier collection region 11 located at the edge to the width of the first polarity carrier collection region 11 located at the edge is set to 10%~80%, so as to effectively collect the carriers of the first polarity carrier collection region 11 located at the edge. For example, the ratio can be 10%, 20%, 50%, 70%, 80%, but is not limited to the values ​​cited.

[0074] According to the embodiments of the present application, reference Figure 2 As shown, the non-electrode collecting region 20 , the first polarity carrier collecting region 11 , the second polarity carrier collecting region 12 , and the isolation region 13 all extend along a second direction perpendicular to the first direction within the plane of the silicon wafer 1 .

[0075] According to an embodiment of the present application, the length of the first polarity carrier collecting region 11 located at the edge along the second direction is equal to the length of the first polarity carrier collecting region 11 located on the inner side along the second direction, that is, the ratio of the length of the first polarity carrier collecting region 11 located at the edge along the second direction to the length of the first polarity carrier collecting region 11 located on the inner side along the second direction is 1.00.

[0076] According to an embodiment of the present application, the silicon wafer 1 also includes a chamfer connecting two adjacent sides. The length of the first polarity carrier collecting region 11 located at the edge along the second direction is less than the length of the first polarity carrier collecting region 11 located at the inner side along the second direction, and the ratio of the length of the first polarity carrier collecting region 11 located at the edge along the second direction to the length of the first polarity carrier collecting region 11 located at the inner side along the second direction is 0.95~1.00, for example, 0.95, 0.96, 0.97, 0.98, 0.99, but not limited to the values ​​cited.

[0077] According to the embodiments of the present application, since the width W2 of the first polarity carrier collecting region located at the edge is greater than the width W4 of the first polarity carrier collecting region located on the inner side, the length of the first polarity carrier collecting region 11 located at the edge is set to be slightly less than or equal to the length of the first polarity carrier collecting region 11 located on the inner side, that is, the ratio of the lengths of the two is 0.95~1.00, so as to reduce the influence of the chamfer on the area of ​​the first polarity carrier collecting region 11 located at the edge, thereby avoiding the problem of battery current mismatch caused by excessive current in the first polarity carrier collecting region at the edge.

[0078] Figure 4 A schematic diagram of the design of a first fine gate of a first polarity carrier collection region located at an edge provided in an embodiment of the present application.

[0079] According to the embodiments of the present application, reference Figure 4As shown, the distance between the first fine gate (as shown by the dotted line in the figure) and the edge of the silicon wafer along the first direction is marked as L2; ​​the distance between the first fine gate and the center line of the second polarity carrier collection area 12 adjacent to the first polarity carrier collection area 11 located at the edge along the second direction is marked as L1, and the difference between L2 and L1 does not exceed ±20%, and preferably L2 and L1 are equal, so that the first polarity carrier collection area 11 at the edge can effectively collect the carriers generated by the adjacent second polarity carrier collection area 12 and the non-electrode collection area 20. In other words, the first fine gate on the first polarity carrier collection area 11 located at the edge is not set on the center line of the first polarity carrier collection area 11 extending along the second direction, and the carriers generated by the edge of the silicon wafer and the adjacent second polarity carrier collection area 12 are effectively collected by moving the position of the first fine gate.

[0080] Figure 5 A schematic diagram of the edge area of ​​a silicon wafer provided in an embodiment of the present application.

[0081] According to the embodiments of the present application, reference Figure 5 As shown, the width of the first polarity carrier collection region 11 located at the edge is greater than the width of the first polarity carrier collection region 11 located at the inner side, the first polarity carrier collection region 11 located at the edge is provided with a first fine gate 2A, and the first polarity carrier collection region 11 located at the inner side is provided with a second fine gate 2B. The ratio of the distance d1 between the edge of the first polarity carrier collection region 11 located at the edge and the closest silicon wafer edge extending along the second direction and the distance d2 between the edge of the second fine gate 2B located at the inner side and the closest silicon wafer edge extending along the second direction is 0.8-1.2, so that the carriers generated at the silicon wafer edge of the first polarity carrier collection region 11 located at the edge can be collected by the first fine gate 2A thereon, so as to increase the carrier collection at the chamfer of the silicon wafer, for example, the ratio can be 0.8, 0.9, 1.0, 1.1, 1.2, but is not limited to the values ​​cited.

[0082] According to the embodiments of the present application, the back contact solar cell includes but is not limited to any one of a hybrid BC (combined passivated BC), a low-temperature interdigitated back contact heterojunction solar cell (heterojunction back contact, HBC), an interdigitated back contact solar cell (Interdigitated Back Contact, IBC), a tunneling oxide passivated contact back contact solar cell (tunneling oxide passivated contact back contact, TBC), and a polycrystalline silicon on oxide interdigitated back contact solar cell (polycrystalline silicon on oxide interdigitated back contact, POLO-IBC).

[0083] Figure 6 A schematic cross-sectional view of a back-contact solar cell provided in an embodiment of the present application.

[0084] According to the embodiments of the present application, reference Figure 6 As shown, the back-contact solar cell also includes: a first doped semiconductor portion 14 for collecting and conducting first polarity carriers, the first doped semiconductor portion 14 being arranged in the first polarity carrier collection region 11; a second doped semiconductor portion 15 for collecting and conducting second polarity carriers, the second doped semiconductor portion 15 being arranged in the second polarity carrier collection region 12, wherein the conductivity types of the first doped semiconductor portion 14 and the second doped semiconductor portion 15 are opposite, one of the first doped semiconductor portion 14 and the second doped semiconductor portion 15 is N-type, and the other of the first doped semiconductor portion 14 and the second doped semiconductor portion 15 is P-type.

[0085] According to an embodiment of the present application, the material of the first doped semiconductor portion 14 and / or the second doped semiconductor portion 15 may include any semiconductor material such as silicon, silicon germanium, germanium or gallium arsenide. In terms of the arrangement of the material, the crystal phase of the first doped semiconductor portion 14 and / or the second doped semiconductor portion 15 may be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. Among them, the materials of the first doped semiconductor portion 14 and the second doped semiconductor portion 15 may be the same or different. For example: the materials of the first doped semiconductor portion 14 and the second doped semiconductor portion 15 may both be doped polycrystalline silicon. For another example: the materials of the first doped semiconductor portion 14 and the second doped semiconductor portion 15 may both include at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon. For another example: the material of the first doped semiconductor portion 14 may be doped polycrystalline silicon, and the material of the second doped semiconductor portion 15 may include at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon.

[0086] According to an embodiment of the present application, the back-contact solar cell also includes a first interface passivation layer, which is arranged between the silicon wafer 1 and the first doped semiconductor portion 14; and / or, the back-contact solar cell also includes a second interface passivation layer, which is arranged between the silicon wafer 1 and the second doped semiconductor portion 15.

[0087] According to an embodiment of the present application, when the back-contact solar cell further includes a first interface passivation layer and a second interface passivation layer, the first interface passivation layer and the first doped semiconductor portion 14 constitute a first passivation contact structure, and the second interface passivation layer and the second doped semiconductor portion 15 constitute a second passivation contact structure; wherein the passivation contact types of the first passivation contact structure and the second passivation contact structure may be the same. For example: the first passivation contact structure and the second passivation contact structure are both tunneling passivation contact structures or heterogeneous contact structures. Alternatively, the passivation contact types of the first passivation contact structure and the second passivation contact structure may also be different. For example: one of the first passivation contact structure and the second passivation contact structure is a tunneling passivation contact structure, and the other is a heterogeneous contact structure.

[0088] According to an embodiment of the present application, the above-mentioned back-contact solar cell further includes a first electrode 16 and a second electrode 17, wherein the first electrode 16 is located on a surface of the first doped semiconductor portion 14 away from the silicon wafer 1, and the second electrode 17 is located on a surface of the second doped semiconductor portion 15 away from the silicon wafer 1.

[0089] According to another embodiment of the present application, along the first direction, the electrode collecting region 10 covers the edge of the silicon wafer, that is, no non-electrode collecting region is provided along the first direction or only one non-electrode collecting region is provided. Figure 7 This embodiment is shown, and this arrangement can reduce certain process steps and lower the manufacturing cost.

[0090] According to an exemplary embodiment of the present application, the present application provides a photovoltaic module, including the above-mentioned back-contact solar cell.

[0091] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0092] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A back contact solar cell, characterized in that: include: A silicon wafer, wherein an electrode collection region (10) is formed on the back side of the silicon wafer, the electrode collection region (10) comprising a plurality of first polarity carrier collection regions (11) and a plurality of second polarity carrier collection regions (12) with opposite polarities alternately distributed along a first direction, and an isolation region (13) is provided between adjacent first polarity carrier collection regions (11) and second polarity carrier collection regions (12); The width of at least one of the two edge carrier collection regions adjacent to the edge of the silicon wafer along the first direction is greater than the width of any inner carrier collection region with the same polarity away from the edge of the silicon wafer.

2. The back contact solar cell according to claim 1, characterized in that: It also comprises a non-electrode collecting area (20), wherein the non-electrode collecting area (20) is located outside the electrode collecting area (10) and at the edge of the silicon wafer.

3. The back contact solar cell according to claim 2, characterized in that: The width of the non-electrode collecting area (20) along the first direction ranges from 30 μm to 500 μm.

4. The back contact solar cell according to claim 2, characterized in that: The non-electrode collection region (20) is adjacent to one of the first polarity carrier collection regions (11), The width of the first polarity carrier collection region (11) located at the edge is less than twice the width of the first polarity carrier collection region (11) located at the inside.

5. The back contact solar cell according to claim 2, characterized in that: When the sum of half the width of the first polarity carrier collection region (11) located at the edge and the width of the non-electrode collection region (20) is greater than 300 μm, the first polarity carrier collection region (11) located at the edge comprises two first fine grids distributed along the first direction, and the two first fine grids divide the first polarity carrier collection region (11) located at the edge into three regions of equal area.

6. The back contact solar cell according to claim 5, characterized in that: The width of the first fine gate along the first direction is less than 80 μm.

7. The back contact solar cell according to claim 4, characterized in that: The ratio of the width of the first fine grid on the first polarity carrier collection region (11) located at the edge along the first direction to the width of the first polarity carrier collection region (11) located at the edge is in the range of 5% to 80%.

8. The back contact solar cell according to claim 4, characterized in that: A first fine gate on a first polarity carrier collection region (11) located at an edge extends along a second direction perpendicular to the first direction in a silicon wafer plane; The distance between a first fine gate on a first polarity carrier collection region (11) located at the edge and the edge of the silicon wafer along a first direction and the distance between a center line of a second polarity carrier collection region (12) adjacent to the first polarity carrier collection region (11) located at the edge along a second direction differ by no more than ±20%.

9. The back contact solar cell according to claim 8, characterized in that: The ratio of the length of the first polarity carrier collection region (11) located at the edge along the second direction to the length of the first polarity carrier collection region (11) located at the inside along the second direction is 0.95-1.

00.

10. The back contact solar cell according to claim 9, characterized in that: The ratio of the distance between the edge of the first fine gate extending along the second direction and the closest edge of the silicon wafer to the distance between the edge of the second fine gate extending along the second direction on the inner first polarity carrier collection region (11) and the closest edge of the silicon wafer is 0.8-1.

2.

11. A photovoltaic module, characterized in that: A back-contact solar cell comprising the following:

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