A flexible and stackable cluster computing system

Abstract

The present invention provides a flexible and stackable cluster computing system, which belongs to the field of data processing equipment. The system includes 4 types of modules: power module, processing module, computer main control module, and IO module; the number of processing modules can be flexibly increased or decreased according to demand; the four corners of the left and right sides of the module have through-hole structures for fixed connection of string rods between modules; the systems are networked and used through optical fiber interfaces; the system adopts line clock recovery technology to achieve clock synchronization between modules and systems. From the perspective of the module level, the core computing power module of this computing system has a certain degree of versatility, and a variety of core processing chips can be used according to actual applications. Through device-level hardware design, the degree of integration between software algorithms and hardware systems is minimized, and the system is universal. This invention can not only achieve computing power expansion between modules, but also can be used in flexible cascades of multiple units to expand the overall computing power.

Description

Technical Field

[0001] The present invention belongs to the field of data processing equipment, and in particular relates to a flexible and stackable cluster computing system. Background Art

[0002] In recent years, in order to solve the shortcomings of cluster cloud computing in terms of security, network dependence and environmental adaptability, fog computing and edge computing have been proposed. The purpose is to migrate computing power, storage and interface resources in cloud computing to the middle and long segments or near ends of the network. However, the new methods have brought about the heterogeneity of computing devices in the cloud, fog and edge, resulting in a series of problems such as poor interoperability, low resource utilization, lack of flexible scalability and high cost. Summary of the invention

[0003] To solve the above problems, the present invention proposes a high-speed cluster computing system with universality, high reliability and elastic scalability. The system can adapt to various types of mainstream applications and artificial intelligence algorithms, and has a wide range of applications. It can formulate high-performance computing solutions for modules, systems and clusters according to different environments, different applications and different occasions.

[0004] To solve the above technical problems, a specific technical solution of a flexible stackable cluster computing system of the present invention is as follows:

[0005] The cluster computing system is designed with a heterogeneous and scalable architecture. The system can flexibly build the modules and resources required by the application according to the resources required by the application algorithm. In the design process, the proportion of domestic products is maximized, and in principle, the design is based on national production.

[0006] A flexible and stackable cluster computing system includes four types of modules: a power module, N processing modules, a computer main control module, and an IO module. The number of processing modules can be flexibly increased or decreased according to demand, and the modules are stacked in parallel, which are the power module, N processing modules, the computer main control module, and the IO module in order.

[0007] The module shell is a rectangular structure, with the external interface surface of the module at the front, and the modules are stacked side by side on the left and right sides; the four corners of the left and right sides of the module have through-hole structures for connecting the modules with string rods; integrated heat dissipation teeth are set on the upper and rear sides of the module to dissipate heat using external air ducts;

[0008] The power supply module provides power to the cluster computing system;

[0009] The processing module can be configured with a CPU, an embedded GPU, an FPGA or a dedicated ASIC chip, and can also be configured with an ARM coprocessor and a high-speed, large-capacity memory;

[0010] The computer main control module is a configuration and resource integration scheduling module of the cluster computing system, providing large-scale programming logic resources and PowerPC processors, high-speed and large-capacity memory;

[0011] The IO module is the load unit module of the cluster computing system, which provides data input for the system and is designed as different load inputs according to requirements.

[0012] The external information interface of the cluster computing system enters the system through the connector, and the internal data is transmitted to each other through the GTH high-speed serial port, GTH optical fiber interface and network interface for use by various modules within the system; data is transmitted from the I / O module to the downstream in the form of streams, and the downstream modules use time slicing to obtain the data they need in time-sharing. The configuration of time slices and data bandwidth is completed by the computer main control module; systems are networked through optical fiber interfaces;

[0013] User signals are input and output through the IO module or computer main control module, and after being processed by the module's internal FPGA, they are distributed to each module of the system for use;

[0014] Each module inside the system has a unique physical address and ID number for identification of data transmission. During the data transmission process, data flows from the IO module to the computer main control module. After receiving the data, the computer main control module uses the rate matching queue mechanism. If the data frame contains data that matches the physical address and ID number of its own module, it will be used. Data forwarding rules are designed inside the module to enable users to flexibly configure the data frame, forward the data frame according to the intra-frame forwarding rules, and send the data to the downstream processing module. The data transmission process is similar. The data upload process is the opposite of the download process, which realizes the data flow within the system.

[0015] Furthermore, the system adopts line clock recovery technology, utilizes the transmitting end clock information carried by the flip frequency and phase of the line data, recovers the line clock, and then inputs the clock into a dedicated clock synthesizer, combines it with the local high-stability clock, and adopts clock de-jittering to de-jitter and distribute the recovered clock as the local system working clock, so as to realize the clock synchronization between modules and systems;

[0016] Furthermore, the clock de-jitter adopts a dual phase-locked loop cascade architecture, the first-stage phase-locked loop is a voltage-controlled crystal oscillator VCXO with a low loop bandwidth to achieve de-jitter, and the second-stage phase-locked loop is a voltage-controlled oscillator VCO with a high loop bandwidth to achieve distribution.

[0017] Furthermore, the timing within the system and between systems is divided into two levels. The first level is that the time code board on the computer main control module receives the external B-code timing source, solves and outputs the time, and performs timing for the computer main control module; the second level is that the computer main control module transmits the timing information to the processing module and other cascaded systems through the data communication channel of the synchronous time division protocol bus.

[0018] Furthermore, the computer main control module uses a high-precision temperature-compensated crystal oscillator as the board operating clock. When an external clock source is detected, the local clock count is first used to detect the interval of the input second pulse and the time code information. After locking for 3 consecutive seconds, the external time source is started to be used. In the subsequent process, the second pulse interval and time code information are continuously detected, and the erroneous time code information is shielded during the process. The other times follow the external time source.

[0019] Furthermore, in the case of multi-level cascading between systems, the computer main control module as the master end uses the IEEE-1588 protocol to synchronize the time of the computer main control modules of other cascaded systems as the slave ends; at the same time, a dedicated time slot is opened in the synchronous time division protocol frame for transmitting the PTP protocol frame, isolation from other business data is achieved on the channel, and pure hardware is used to implement the processing of the PTP protocol.

[0020] Furthermore, the power module, N processing modules, computer main control module, and IO module also have through holes in the middle of the left and right sides for electrical connection between modules.

[0021] Furthermore, the heating devices on the internal PCB boards of the power module, N processing modules, computer main control module, and IO module are packaged in a surface mount form, using copper for heat conduction, and copper foil is laid under the heating devices for heat dissipation. The heat dissipation copper tube is connected to the heating device with thermal conductive silicone, and vias are set on the copper foil to conduct heat to the outer shell board.

[0022] Furthermore, the power module, N processing modules, computer main control module, and IO module have internal integrated filtering, EMC and other components to ensure the normal use of the system in complex environments.

[0023] Furthermore, the large-scale programming logic resource is FPGA.

[0024] Furthermore, the specific parameters of the GTH high-speed serial port are width X8 and line rate 6.25 Gbps; the specific parameters of the GTH optical fiber interface are width X1 and line rate 6.25 Gbps, and the interconnection mechanism between systems is star, ring, tree or other topology.

[0025] The beneficial effects of the present invention are as follows:

[0026] From the perspective of module level, the computing system provided by the present invention has a certain versatility in the core computing power module, and can adopt chips based on CPU, embedded GPU, FPGA or dedicated ASIC as the core processing chip according to the actual application. Through device-level hardware design, the degree of integration between the software algorithm and the hardware system is minimized, thereby achieving the universalization of the system. While considering low cost and localization, the invention can not only achieve the expansion of computing power between modules, but also can be used in elastic cascade to expand the overall computing power. This design method enables the device to be deployed at fixed points in the cloud, fog end and edge end, and can also be used as a mobile edge computing system in vehicle-mounted, airborne end, etc., to achieve high interoperability and resource utilization, while taking into account elastic scalability and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram of the modules of a single cluster computing system.

[0028] Figure 2 This is a schematic diagram of the structure of a single cluster computing system.

[0029] Figure 3 This is the internal data interconnection flow diagram of a single cluster computing system.

[0030] Figure 4 This is a schematic diagram of the topology of multiple cluster computing system modules.

[0031] Figure 5 Schematic diagram of line clock recovery technology.

[0032] Figure 6 Schematic diagram of the line clock recovery process in a multi-stage cascade situation.

[0033] Figure 7 This is a schematic diagram of the 1588 time synchronization process. DETAILED DESCRIPTION

[0034] In order to better understand the purpose, structure and function of the present invention, a flexible and stackable cluster computing system of the present invention is further described in detail below with reference to the accompanying drawings.

[0035] like Figure 1 As shown in FIG. 1 , a flexible and stackable cluster computing system includes four types of modules: power module, N processing modules, computer main control module, and IO module. The number of modules can be flexibly increased or decreased according to application requirements. The modules are arranged in parallel, namely, power module, N processing modules, computer main control module, and IO module. Figure 2As shown, each module shell is a rectangular structure, with the left and right sides stacked side by side, and an interface designed on the front side for inter-module and external connections. Through-hole structures are set at the four corners of the left and right sides of each module for custom string rods between modules, and the left and right sides of the module fit each other. Furthermore, the power module, N processing modules, computer main control module, and IO module also have through holes in the middle of the left and right sides for electrical connections between modules.

[0036] Each module has integrated heat dissipation teeth on the upper and rear sides, and uses external air ducts for heat dissipation. Due to the need to process various complex algorithms, the device power consumption is large and the heat generated is high. The heat of the module main device is transferred to the module shell through the capillary thermal copper tube, and the outside of the shell adopts fan heat dissipation. The heating device on the PCB board inside each module adopts the surface mount packaging form, using copper with good thermal conductivity for heat conduction, and a large area of ​​copper foil is laid under the heating device for heat dissipation. The heat dissipation copper tube and the heating device are connected with thermal conductive silicone to increase the heat conduction area. Then, multiple vias are set on the copper foil to transfer the heat to the aluminum shell plate for heat dissipation.

[0037] The length and width of each module shell are tentatively set at 130*110mm, and the thickness depends on the processing chip selection, connector requirements and thermal simulation. The external connector of the cluster computing system can be adapted to military connectors such as aviation plugs. The cluster computing system is made of 6061-T6 material, and the internal module frame is made of magnesium-aluminum alloy profiles, and the rubber coating is a high-strength silicone rubber part. Each module integrates filtering, EMC (electromagnetic compatibility) and other components to ensure the normal use of the equipment in complex environments.

[0038] The following is a detailed introduction to each module.

[0039] Power module: Provides power for the cluster computing system, converts DC18V~DC36V DC power into the power required by the processing module, computer main control module, and IO module, and is designed to have a +12V output. The power module input is +18V~+36V, and the maximum load capacity is 350W. One power module is set for one cluster computing system.

[0040] Processing module: The processing module is the core module of the cluster computing system. Its internal configuration is based on chips such as CPU, embedded GPU, FPGA or dedicated ASIC, and is also equipped with an ARM coprocessor. It provides DDR3 and high-speed large-capacity memory for users to use. It has external interfaces such as GTH electrical interface, GTH optical interface and network port for users to use. Each cluster computing system can set the number of processing modules according to demand.

[0041] Computer main control module: The computer main control module is the configuration and resource integration scheduling module of the cluster computing system, providing large-scale programming logic resources and PowerPC processors; specifically, a single computer main control module has 1 FPGA and 1 PowerPC coprocessor onboard, provides DDR3 and high-speed large-capacity memory for users, and has GTH electrical interface, GTH optical interface, network port and other interfaces for users.

[0042] IO module: The IO module is the load unit module of the cluster computing system, which provides data input for the system. The IO module can be designed with different load inputs according to application requirements.

[0043] In order to reduce data transmission delay, improve the consistency and stability of cluster computing systems, and achieve high consistency of system clocks between nodes, line clock recovery technology is used to recover the line clock using the sending end clock information carried by the flip frequency and phase of line data. However, the clock jitter obtained in this way is large, and the clock needs to be input into a dedicated clock synthesizer, combined with a local high-stability clock, and a highly stable clock signal with frequency and phase correlation with the sending end clock is generated through phase locking as the local system working clock to achieve clock synchronization between modules and systems.

[0044] Specifically, Figure 5 The figure shows a schematic diagram of line clock recovery technology. In the upper left corner of the figure, the receiving channel PLL (phase-locked loop) is set to CDR (clock and data recovery) mode. The CDR initially locks to the local reference clock and works near the received data rate. After the lock is completed, the CDR switches to lock to the data and adjusts the clock phase and frequency according to the input data. In this way, the local transmit clock of the other end is recovered to complete the transmission of clock information. Locking to the data depends on the alternation of 0 and 1 in the data stream, and the PCS (physical layer) encoding cannot guarantee absolute continuous flipping, forming the input phase noise of the PLL. First, it is difficult to make the loop filter bandwidth of the PLL low enough to form sufficient attenuation for the input jitter; second, the VCO (voltage-controlled oscillator) of the PLL itself also generates phase noise. Therefore, the recovered clock has a certain jitter, which deteriorates the clock quality during the transmission process.

[0045] Therefore, as shown in the lower left of the figure, the system uses clock de-jitter to de-jitter and distribute the clock recovered by the CDR, so that the clock maintains its performance after passing through the optical fiber and backplane. Usually, clock de-jitter adopts a dual PLL cascade architecture. The first-stage PLL is a high-performance VCXO (voltage-controlled crystal oscillator) with a low loop bandwidth to achieve de-jitter, and the second-stage PLL is a VCO (voltage-controlled oscillator) with a high loop bandwidth to achieve distribution.

[0046] like Figure 6 As shown, it is a schematic diagram of the line clock recovery process in a multi-stage cascade case; the figure includes 4 systems, the clock of the master system passes through the clock synthesizer and the high-speed transceiver, and is directly transmitted to the slave system 1 and the slave system 3 through the line data, and is transmitted to the slave system 2 via the slave system 1.

[0047] In order to ensure high speed and timing consistency within and between systems, the system timing is divided into two levels. The first level is that the time code board on the computer main control module receives the external B-code timing source, solves and outputs the time, and performs timing for the computer main control module. The second level is that the computer main control module transmits the timing information to the processing module and other cascaded system systems through the DCC (data communication) channel of the synchronous time division protocol bus, thereby completing the timing function for other nodes in the network.

[0048] The computer main control module uses a high-precision temperature-compensated crystal oscillator as the board running clock. When an external clock source is detected, the local clock count is first used to detect the interval of the input second pulse and the time code information. After locking for 3 consecutive seconds, it starts to use the external time source. In the subsequent process, the second pulse interval and time code information are continuously detected, and the erroneous time code information is shielded during the process. The rest of the time follows the external time source.

[0049] The computer main control module as the master end uses the IEEE-1588 protocol to synchronize the time of the computer main control modules of other cascade systems as the slave end. The IEEE-1588 synchronization process uses the time difference between the master end and the slave end to send and receive data packets, and calculates the data transmission delay and the time deviation between the master end and the slave end through mathematical operations. The basic assumption for establishing the mathematical equation is that the two-way transmission time of the data packet between the master end and the slave end is the same. The 1588 time synchronization process is shown in the figure below. Figure 7 As shown in the figure, dynamic path delay = [(t2–t1) + (t4–t3)] / 2; master-slave time difference = [(t2–t1) - (t4–t3)] / 2; t1 is the time when the master clock sends the message, t2 is the time when the slave clock receives the message because of the offset and delay; t3 is the time when the slave clock feeds back the delay information to the master clock, and t4 is the time when the master clock receives the message because of the delay in the feedback process. The entire synchronization process is to calculate and offset the time difference.

[0050] Therefore, the factors that affect the timing accuracy of IEEE-1588 are: 1. The clock consistency between the master and slave ends; 2. The transmission delay jitter of the timing frame and the round-trip consistency of the timing channel; 3. The processing time of the PTP protocol frame. In view of these three factors, we improve the timing accuracy performance in the following ways: Clock consistency between the master and slave ends: guaranteed by the above-mentioned line clock recovery technology. Transmission delay jitter of the timing frame and the round-trip consistency of the timing channel: a dedicated time slot is opened in the synchronous time division protocol frame for transmitting the PTP protocol frame, and isolation from other business data is achieved on the channel to avoid conflicts, thereby ensuring the jitter index of the transmission delay and the consistency of the round-trip time. PTP protocol frame processing time: pure hardware is used to implement the processing of the PTP protocol, ensuring that the protocol processing time is fixed each time, further improving the timing performance. After actual measurement, the IEEE1588 timing accuracy achieved by the above-mentioned methods is better than ±15ns.

[0051] The external information interface of the cluster computing system can enter the system through connectors such as aviation plugs, and the internal data is transmitted to each other through the GTH high-speed serial port, GTH optical fiber interface and network interface for use by various modules within the system.

[0052] The modules communicate with each other through high-speed serial ports, where the upstream and downstream data interfaces are X8 high-speed serial ports with a line rate of 6.25Gbps. Data is transmitted from the I / O module to the downstream in a stream form. The downstream modules use a similar time-slicing method to obtain the required data in a time-sharing manner to ensure data real-time and low transmission delay. The configuration of time slices and data bandwidth is completed by the computer main control module. The cluster computing system has various interfaces to the outside, including user interfaces and debugging interfaces. At the same time, its optical fiber interface X1 6.25Gbps can be used for networking between systems.

[0053] The hardware diagram of the interconnection between modules is as follows: Figure 3 As shown, in a single-system multi-processing module application, each module communicates and interconnects data through a high-speed serial port. The interconnection structure is a cascade structure. Data is transmitted between modules through a data transparent transmission and forwarding mechanism. Any module inside the device is guaranteed to transmit data to each other. This is implemented using the FPGA's GTH interface and is compatible with a variety of data transmission protocols.

[0054] In multi-system applications, data communication can be performed between systems through the optical fiber interface configured on the module, realizing cascading between systems for computing power expansion and multi-system networking operations. User signals are input and output through IO modules or computer modules, and after being processed by the FPGA inside the module, they are distributed to the modules of the computing system for use.

[0055] Data needs to be transmitted between various modules of the cluster computing system to realize business data flow. Quantity interconnection needs to consider low latency and convenient and flexible networking. The transmission of data flow between modules adopts GTH raw data flow mode for data transmission. The upstream and downstream data interfaces of the module are GTH high-speed serial ports, with a design width of X8 mode and a line rate of 6.25Gbps. Each module in the system has a unique physical address and ID number for identification of data transmission. The physical interface for data transmission is GTH high-speed serial port. The basic protocol for data transmission is raw data stream Aurora mode (lightweight point-to-point serial link layer scalable mode). Transmission is carried out in data stream mode (stream mode), which can maximize data transmission bandwidth and minimize data transmission delay. During data transmission, a data transmission frame mechanism is established based on the data stream. Data flows from the IO module to the computer main control module. After the computer main control module receives it, it uses the rate matching queue mechanism (FIFO, first in first out) to obtain data that matches the physical address and ID number of its own module in the data frame. The module is designed with data forwarding rules to enable users to flexibly configure and forward data frames according to the frame forwarding rules, and send data to the post-processing module. The data downlink process is similar. The data uploading process is the opposite of the downlink process, which can realize the data flow within the system.

[0056] The data distribution mechanism within the system adopts module access and data forwarding mechanism. The data sending main control module sends the same number of data frames at the same time (for example, 8000 frames per second, configurable). Each frame contains the payload data required by the subsequent module. The data bandwidth and sending interval required by each functional module can be configured through the computer main control module to reasonably allocate the data stream bandwidth, thereby realizing the data exchange mechanism within the system.

[0057] The external interface of the IO module includes the data load interface required by the matching application. The external interfaces of the computer main control module and the processing module include the network interface, the optical fiber interface (for data interconnection between systems), the debugging interface, etc. The network interface is used to realize the parameter configuration and management of the system. The optical fiber interface is used to realize the expansion between systems for system cascading and networking. The debugging interface is mainly used for debugging system applications and querying system status.

[0058] After the power module starts working, it will send the power supply status to the computer main control module in real time through the status interface so as to summarize the power consumption of the system.

[0059] Cluster computing systems can be used alone or in cascade. When the processing power of a single system cannot meet the application computing requirements or multiple types of applications need to be processed in parallel, multiple systems can be cascaded to expand computing power. The data interconnection mechanism between systems is mainly used to solve the problem of insufficient computing power of a single system, expand the computing power of a single system, and realize the collaborative work of multiple systems through the connection of optical fiber channels.

[0060] The cascade interface of the cluster computing system is realized by using the optical fiber path on the computer main control module and the processing module. The optical fiber interface is designed as X1, and the line rate is designed as 6.25Gbps. By configuring the optical fiber interface on the module, the data stream can be transmitted through the optical fiber path to achieve the purpose of data communication between systems.

[0061] In the application, it is necessary to configure the resources required by the application in advance, set up a reasonable data flow and transceiver processing mechanism, configure the computer main control module and processing module, design the data sharing and system data routing mechanism that meet the application, and complete the multi-system collaboration function. Since the computer main control module and processing module in a single system are designed with X1, 6.25Gbps optical fiber channels, the interconnection mechanism between systems can be flexibly changed to flexibly create topological structures such as star, ring, and tree. Figure 4 shown.

[0062] The cluster computing system has two working modes: preparation mode and real-time working mode;

[0063] Preparation mode: The preparation mode completes system topology discovery, system configuration, configuration file generation, configuration file loading, configuration content check, FPGA firmware upgrade and other tasks, and can also query and compare system configuration files. Among them, system configuration completes the creation, modification, setting and saving of the project; configuration file generation includes the generation of configuration files for the entire system and the generation of format files for external data output; configuration content check includes the detection of the correctness of configuration file loading, and parameter check is the readback verification of parameter output.

[0064] Real-time working mode: In real-time working mode, after the MCU is powered on, it reads the parameter configuration file saved in FLASH, performs protocol conversion, and configures the parameters of the FPGA through the FLEXBUS bus. At the same time, the FPGA completes the initialization of peripheral devices. After the entire device completes power-on initialization, it enters the workflow of data acquisition, transmission, and processing.

[0065] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A flexible and stackable cluster computing system. It is characterized in that It includes 4 types of modules: power module, N processing modules, computer main control module, and IO module. The number of processing modules can be flexibly increased or decreased according to demand, and the modules are stacked in parallel, namely power module, N processing modules, computer main control module, and IO module. The module shell is a rectangular structure, with the external interface surface of the module at the front, and the modules are stacked side by side on the left and right sides; the four corners of the left and right sides of the module have through-hole structures for connecting the modules with string rods; integrated heat dissipation teeth are set on the upper and rear sides of the module to dissipate heat using external air ducts; The power supply module provides power to the cluster computing system; The processing module is internally configured with a CPU, an embedded GPU, an FPGA or a dedicated ASIC chip, and is also configured with an ARM coprocessor and a high-speed, large-capacity memory; The computer main control module is a configuration and resource integration scheduling module of the cluster computing system, providing large-scale programming logic resources and PowerPC processors, high-speed and large-capacity memory; The IO module is the load unit module of the cluster computing system, which provides data input for the system and is designed as different load inputs according to requirements; The external information interface of the cluster computing system enters the system through the connector, and the internal data is transmitted to each other through the GTH high-speed serial port, GTH optical fiber interface and network interface for use by various modules within the system; data is transmitted from the I / O module to the downstream in the form of streams, and the downstream modules use time slicing to obtain the data they need in time-sharing. The configuration of time slices and data bandwidth is completed by the computer main control module; systems are networked through optical fiber interfaces; User signals are input and output through the IO module or computer main control module, and after being processed by the module's internal FPGA, they are distributed to each module of the system for use; Each module in the system has a unique physical address and ID number for data transmission identification. During data transmission, data flows from the IO module to the computer main control module. After receiving the data, the computer main control module uses the rate matching queue mechanism. If the data frame contains data that matches the physical address and ID number of its own module, it will be used. The module is designed with data forwarding rules to enable users to flexibly configure the data frame, forward the data frame according to the frame forwarding rules, and send the data to the downstream processing module. The data transmission process is similar. The data upload process is the opposite of the download process, that is, the data flow within the system is realized. The system adopts line clock recovery technology, uses the sending end clock information carried by the flip frequency and phase of the line data to recover the line clock, and then inputs the clock into a dedicated clock synthesizer, combines it with the local high-stability clock, and uses clock de-jitter to de-jitter and distribute the recovered clock as the local system working clock, so as to realize the clock synchronization between modules and systems; The clock de-jitter adopts a dual phase-locked loop cascade architecture, the first-stage phase-locked loop is a voltage-controlled crystal oscillator VCXO with a low loop bandwidth to achieve de-jitter, and the second-stage phase-locked loop is a voltage-controlled oscillator VCO with a high loop bandwidth to achieve distribution; In the case of multi-level cascading between systems, the computer main control module as the master end uses the IEEE-1588 protocol to synchronize the time with the computer main control modules of other cascaded systems as the slave end. At the same time, a dedicated time slot is opened in the synchronous time division protocol frame to transmit the PTP protocol frame, so as to achieve isolation from other business data on the channel, and the PTP protocol processing is implemented by pure hardware.

2. The elastically stackable cluster computing system according to claim 1, It is characterized in that The timing within the system and between systems is divided into two levels. The first level is that the time code board on the computer main control module receives the external B code timing source, solves and outputs the time, and performs timing on the computer main control module; the second level is that the computer main control module transmits the timing information to the processing module and other cascaded systems through the data communication channel of the synchronous time division protocol bus; The computer main control module uses a high-precision temperature-compensated crystal oscillator as the board running clock. When an external clock source is detected, the local clock count is first used to detect the interval of the input second pulse and the time code information. After locking for 3 consecutive seconds, it starts to use the external time source. In the subsequent process, the second pulse interval and time code information are continuously detected, and the erroneous time code information is shielded during the process. The rest of the time follows the external time source.

3. The elastically stackable cluster computing system according to claim 2, It is characterized in that The power module, N processing modules, computer main control module, and IO module are also provided with through holes in the middle of the left and right sides for electrical connection between the modules.

4. The elastically stackable cluster computing system according to claim 2, It is characterized in that The heating devices on the internal PCB boards of the power module, N processing modules, computer main control module, and IO module are packaged in a surface mount manner, using copper for heat conduction, and copper foil is laid under the heating devices for heat dissipation. The heat dissipation copper tube is connected to the heating device with thermal conductive silicone, and vias are set on the copper foil to conduct heat to the outer shell board.

5. The elastically stackable cluster computing system according to claim 2, It is characterized in that The power supply module, N processing modules, computer main control module, internal integrated filtering, EMC and other components of the IO module ensure the normal use of the system in complex environments.

6. The elastically stackable cluster computing system according to claim 2, It is characterized in that The large-scale programming logic resource is FPGA.

7. The elastically stackable cluster computing system according to claim 2, It is characterized in that The specific parameters of the GTH high-speed serial port are width X8 and line rate 6.25 Gbps; the specific parameters of the GTH optical fiber interface are width X1 and line rate 6.25 Gbps. The interconnection mechanism between systems is star, ring, tree or other topology.

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