Amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and preparation method thereof

Abstract

The present invention discloses an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and a preparation method thereof. The thin film transistor device comprises: a substrate layer, a bottom gate electrode layer, a top gate electrode layer, a bottom gate insulating layer, a top gate insulating layer, an InAlSnO active layer, an InGaZnO active layer, a source electrode layer, a drain electrode layer and a passivation layer. The present invention effectively suppresses the carrier capture effect and enhances the electrical reliability of the TFT device by forming a composite channel structure with a larger InAlSnO / InGaZnO heterojunction energy band step.

Description

Technical Field

[0001] The present invention belongs to the technical field of thin film transistor devices and process manufacturing thereof, and more specifically, relates to an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and a preparation method thereof. Background Art

[0002] The new transparent amorphous InGaZnO-based thin film transistor (a-IGZO TFT) has high field-effect electron mobility (>10 cm 2 / V•s), high optical transmittance (E g >3.0 eV), low power consumption and low cost, it has significant application prospects in active matrix organic light-emitting diode display (AM-OLED), active matrix liquid crystal display (AM-LCD) and System-on-panel (SoP) technology; at the same time, because the a-IGZO TFT prepared under room temperature conditions still has good electrical properties, the TFT device is compatible with flexible substrates, and it also has great application potential in flexible transparent display technology. Although a-IGZOTFT shows excellent device performance, due to the inherent amorphous properties of a-IGZO materials, there are high-density band tail states and subband state-related defects distributed in the material band gap, which seriously affects the field effect electron mobility and electrical reliability of TFT devices. According to the design requirements of the next generation of advanced display technology, the driving TFT device needs to have a higher electron mobility to reduce the size of the TFT device, reduce the pixel area, and increase the number of pixels, thereby realizing high resolution, high brightness, large size, and high refresh rate new display technology applications (such as AR / VR display, 3D display and flexible logic circuits). In order to overcome the material property limitations of a-IGZO TFT devices, oxide heterojunction composite channel band engineering has been proposed to increase the electron mobility and electrical reliability of TFT devices. In the oxide heterojunction composite channel band structure, a large band step will be formed at the heterojunction interface of the TFT device ( ): that is, a potential well is formed on one side of the narrowband (n) oxide semiconductor thin film material, and a potential barrier is formed on the side of the broadband (N) oxide semiconductor thin film material; at the same time, a carrier accumulation similar to a two-dimensional electron gas is formed in the potential well, which helps to improve the electron mobility of the TFT device; in addition, the potential barrier at the heterojunction interface of the TFT device will suppress the channel carrier capture effect, thereby improving the electrical reliability of the TFT device.

[0003] At present, the reported TFT devices based on a-IGZO oxide heterojunction composite channel, such as InZnO / InGaZnO, InO / InGaZnO, InSnO / InGaZnO, etc., have improved the field effect mobility and electrical reliability of their TFT devices. The improvement of the electrical performance of TFT devices is attributed to the formation of heterojunctions of oxide composite channel semiconductor materials ( ). Studies have shown that having a larger energy band gap is the key to improving the field effect electron mobility and electrical reliability of oxide heterojunction composite channel TFT devices. However, the energy band gap modulation range of the reported semiconductor heterojunction composite channel materials is relatively small (E g (a-IGZO) is about 3.0 eV~3.5 eV, E g (ITO) is about 3.8 eV~4.2 eV), and the heterojunction barrier of the TFT device formed is relatively low, which affects the further improvement of the field effect electron mobility and electrical reliability of the TFT device. Since Al2O3 material has a wide bandgap (~8.7 eV), doping an appropriate amount of Al into InSnO material will significantly increase the bandgap width of InAlSnO thin film material (~5.0 eV).

[0004] Therefore, there is an urgent need for a new amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and a preparation method thereof. Summary of the invention

[0005] The present invention forms an InAlSnO / InGaZnO heterojunction composite channel structure with a larger heterojunction energy band step. A wide bandgap high-conductivity InAlSnO film is used to contact InGaZnO to form a homogeneous heterojunction, forming a larger heterojunction energy band step, thereby accumulating a higher concentration of carriers in the heterojunction potential well, thereby improving the electron mobility of the TFT device; a higher heterojunction potential barrier will effectively suppress the carrier capture effect, thereby improving the electrical reliability of the TFT device. At the same time, in order to further improve the performance of the TFT device, the present invention proposes to use a dual-gate structure to regulate the dual-channel heterojunction composite channel, so as to optimize the longitudinal electric field distribution in the TFT device, reduce the carrier scattering effect at the device interface, and improve the carrier mobility of the TFT device.

[0006] Based on the wide band gap, high electron mobility and good conductivity of InAlSnO thin film materials, it is combined with a-IGZO thin film materials to form an nN heterostructure. According to the semiconductor heterojunction energy band theory, a large band gap will be formed at the a-IGZO / IATO heterojunction interface ( ): that is, a potential well is formed on one side of the a-IGZO thin film material, and a potential barrier is formed on the side of the InAlSnO thin film material; at the same time, a carrier accumulation similar to a two-dimensional electron gas is formed in the potential well, which helps to improve the electron mobility of the TFT device; in addition, the potential barrier at the a-IGZO / IATO heterojunction interface will suppress the channel carrier capture effect, thereby improving the electrical reliability of the TFT device.

[0007] In order to solve at least one of the above technical problems, according to one aspect of the present invention, an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device is provided, comprising: a substrate layer 1, a bottom gate electrode layer 2, a top gate electrode layer 8, a bottom gate insulating layer 3, a top gate insulating layer 7, an InAlSnO active layer 4, an InGaZnO active layer 5, a source electrode layer 6, a drain electrode layer 10 and a passivation layer 9; the bottom gate electrode layer 2 covers the center position of the upper surface of the substrate layer 1; the bottom gate insulating layer 3 is located on the upper side of the bottom gate electrode layer 2 and completely covers the upper surfaces of the substrate layer 1 and the bottom gate electrode layer 2; the InAlSnO active layer 4 is located in the middle position of the upper side of the bottom gate insulating layer 3 and is patterned; the InGaZnO active layer 5 is located in the middle position of the upper side of the bottom gate insulating layer 3 and is patterned; The upper surface of the patterned InAlSnO active layer 4; a source electrode layer 6 and a drain electrode layer 10 are respectively formed on the left and right sides of the upper surface of the InGaZnO active layer 5, and patterned; the top gate insulating layer 7 is located in the InGaZnO active layer 5 and the bottom gate insulating layer 3 area except the alignment with the source electrode layer 6 and the drain electrode layer 10; the top gate electrode layer 8 is located in the central part area aligned with the top gate insulating layer 7 and patterned; the passivation layer is respectively located on the upper surfaces of the top gate insulating layer 7, the source electrode layer 6, the drain electrode layer 10 and the top gate electrode layer 8, and the passivation layer does not completely cover the source electrode layer 6 and the drain electrode layer 10; and the InAlSnO active layer 4 and the InGaZnO active layer 5 area other than the alignment with the top gate electrode layer 8 are subjected to conductor processing.

[0008] Furthermore, the substrate layer 1 is made of glass or flexible material with high transparency.

[0009] Furthermore, the bottom gate electrode layer 2 is made of materials such as ITO, titanium, aluminum, nickel, molybdenum, copper, and gold, and the thickness of the bottom gate electrode layer 2 is 50nm-500nm.

[0010] Furthermore, the bottom gate insulating layer 3 is made of dielectric materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc., and the thickness of the bottom gate insulating layer 3 is 50nm-500nm.

[0011] Furthermore, the active layer material is an InAlSnO active layer 4 thin film and an InGaZnO active layer 5 thin film, and the thickness of the active layer material is 2nm-15nm and 10nm-60nm respectively. The InAlSnO active layer 4 thin film material has the characteristics of wide band gap, high electron mobility and good conductivity, and is combined with the amorphous InGaZnO active layer 5 thin film material to form an nN isotype heterostructure.

[0012] Furthermore, the source electrode layer 6 and the drain electrode layer 10 are made of materials such as ITO, titanium, aluminum, nickel, molybdenum, copper, and gold, and the thickness of the source electrode layer 6 and the drain electrode layer 10 is 100nm-500nm.

[0013] Furthermore, the top gate insulating layer 7 is made of dielectric materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc., and the thickness of the top gate insulating layer 7 is 50nm-500nm.

[0014] Furthermore, the top gate electrode layer 8 is made of materials such as ITO, titanium, aluminum, nickel, molybdenum, copper, and gold, and the thickness of the top gate electrode layer 8 is 50nm-500nm.

[0015] Furthermore, the passivation layer 9 is made of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc., and has a thickness of 100nm-1000nm. Its purpose is to protect the device surface from corrosion by external gas, moisture, and impurities, and improve the reliability of the TFT device.

[0016] According to another aspect of the present invention, a method for preparing an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device is provided, comprising the following steps:

[0017] Step 1: Obtain and clean the substrate;

[0018] Step 2: Using a magnetron sputtering system or an electron beam evaporation system to deposit a thin film of ITO, titanium, aluminum, nickel, molybdenum, copper, gold, etc. as the bottom gate electrode layer 2;

[0019] Step 3: using a plasma enhanced chemical vapor deposition (PECVD) process or an atomic layer deposition (ALD) process to deposit a thin film of silicon oxide, silicon nitride, hafnium dioxide, aluminum oxide, etc. as a bottom gate insulating layer 3;

[0020] Step 4: sequentially depositing an InAlSnO active layer 4 and an InGaZnO active layer 5 on the bottom gate insulating layer 3 using a magnetron sputtering system;

[0021] Step 5: using a photolithography process and a wet or dry etching process to achieve device isolation on the InAlSnO active layer 4 and the InGaZnO active layer 5;

[0022] Step 6: Using a magnetron sputtering system or an electron beam evaporation system, ITO, titanium, aluminum, nickel, molybdenum, copper, gold or other thin films are deposited on the left and right sides of the upper surface of the InGaZnO active layer 5 to prepare a source electrode layer 6 and a drain electrode layer 10;

[0023] Step 7: using a PECVD process or an ALD process to deposit a layer of silicon oxide, silicon nitride, or aluminum oxide thin film as a top gate insulating layer 7 on the upper surface of the InGaZnO active layer 5 and the bottom gate insulating layer 3;

[0024] Step 8: Using a magnetron sputtering system or an electron beam evaporation system, a thin film of ITO, titanium, aluminum, nickel, molybdenum, copper, gold, etc. is deposited on the central portion of the upper surface of the top gate insulating layer 7 as the top gate electrode layer 8;

[0025] Step 9: using a PECVD process or an ALD process to prepare a thin film of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. as a passivation layer 9;

[0026] Step 10: etching the passivation layer by photolithography and wet or dry etching to expose the source electrode layer 6 and the drain electrode layer 10;

[0027] Step 11: annealing the thin film transistor at a high temperature of 250° C. to 350° C. for 2 hours in air or oxygen atmosphere.

[0028] According to another aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and the preparation method thereof of the present invention.

[0029] According to another aspect of the present invention, there is provided a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the amorphous InGaZnO / InAlSnO heterojunction composite channel dual-gate thin film transistor device and the preparation method thereof of the present invention are implemented.

[0030] Compared with the prior art, the above method of the present invention has the following beneficial effects:

[0031] 1. Band engineering and carrier control: By precisely controlling the composition of each element in the InAlSnO material, the band gap of the material is increased. After forming a heterojunction with InGaZnO, a larger heterojunction band step is formed, and a higher concentration of carriers is accumulated in the heterojunction potential well, thereby improving the field effect electron mobility of the TFT device;

[0032] 2. Enhanced stress stability: By forming a composite channel structure with a larger InAlSnO / InGaZnO heterojunction band step, the carrier capture effect is effectively suppressed and the electrical reliability of the TFT device is enhanced;

[0033] 3. Threshold voltage optimization: Through the optimization design of heterojunction composite channel dual-gate TFT device structure, the threshold voltage of TFT device can be effectively controlled to obtain a low threshold voltage of TFT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0035] Figure 1 It is a schematic diagram of the device structure of the double-gate double-channel thin film transistor in Example 1 of the present invention;

[0036] Figure 2 This is a flow chart of a method for preparing a dual-gate dual-channel thin film transistor according to Example 1 of the present invention;

[0037] Figure 3 This is a structural flow chart of the manufacturing process of the dual-gate dual-channel thin film transistor according to Example 1 of the present invention.

[0038] In the figure: 1-substrate layer, 2-bottom gate electrode layer, 3-bottom gate insulating layer, 4-InAlSnO active layer, 5-InGaZnO active layer, 6-source electrode layer, 7-top gate insulating layer, 8-top gate electrode layer, 9-passivation layer, 10-drain electrode layer. DETAILED DESCRIPTION

[0039] To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them.

[0040] Unless otherwise defined, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0041] Example 1: Figure 1 As shown, the present invention proposes an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device and a preparation method thereof.

[0042] The present invention provides a thin film transistor device including a substrate layer 1, a bottom gate electrode layer 2, a top gate electrode layer 8, a bottom gate insulating layer 3, a top gate insulating layer 7, an InAlSnO active layer 4, an InGaZnO active layer 5, a source electrode layer 6, a drain electrode layer 10 and a passivation layer 9.

[0043] A novel method for preparing a novel amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device, such as Figure 2 As shown, the following steps are included:

[0044] Step S1 (corresponding to Figure 3 (1)): obtaining and cleaning the substrate;

[0045] The substrate layer 1 can be glass or flexible material with high transparency. In this embodiment, Corning EagleXG glass is selected as the substrate. It is cleaned with ultrasonic wave, and then isopropyl alcohol and plasma water are used to clean the substrate until it is cleaned; and it is set aside.

[0046] Step S2 (corresponding to Figure 3 Middle (2)): forming a bottom gate electrode layer 2 on the substrate layer;

[0047] The bottom gate electrode layer 2 can be a thin film of ITO, titanium, aluminum, nickel, molybdenum, copper, gold, etc. In this embodiment, a patterned photoresist mask layer is formed on the substrate by a photolithography process, and then the bottom gate electrode layer 2 is deposited on the substrate layer 1 and the photoresist mask layer by a magnetron sputtering system or an electron beam evaporation system; and then the bottom gate electrode layer 2 is obtained by removing the photoresist through a stripping process.

[0048] Step S3 (corresponding to Figure 3 (2)): forming a bottom gate insulating layer 3 on the substrate layer 1 and the bottom gate electrode layer 2;

[0049] The bottom gate insulating layer 3 may be a dielectric material such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. In this embodiment, the bottom gate insulating layer 3 is formed on the bottom gate electrode layer 2 and the substrate layer 1 by a plasma enhanced chemical vapor deposition (PECVD) process or an atomic layer deposition (ALD) process, and the thickness of the bottom gate insulating layer 3 is about 50nm-500nm.

[0050] Step S4 (corresponding to Figure 3 (3)): an InAlSnO active layer 4 and an InGaZnO active layer 5 are sequentially prepared on the bottom gate insulating layer 3;

[0051] In this embodiment, a single InAlSnO target sintered from In2O3, Al2O3, and SnO2 is selected. An InAlSnO film is prepared on the bottom gate insulating layer as the front channel layer by a magnetron sputtering process, and a 600-second pre-sputtering coating is used before each deposition. A single InGaZnO target sintered from In2O3, Ga2O3, and ZnO is selected. An InGaZnO film is prepared on the upper surface of the InAlSnO active layer 4 by a magnetron sputtering process as the back channel layer, and a 600-second pre-sputtering coating is used before each deposition;

[0052] A photoresist barrier layer is formed on the upper surface of the InGaZnO active layer 5 by using a photolithography process, and a target pattern of the InAlSnO or InGaZnO thin film is formed by using a dry or wet etching process; furthermore, the InAlSnO or InGaZnO thin film region other than the top gate electrode layer 8 is subjected to conductor processing.

[0053] Step S5 (corresponding to Figure 3 (4)): forming a source electrode layer 6 and a drain electrode layer 10 on the InGaZnO active layer 5;

[0054] The source electrode layer 6 and the drain electrode layer 10 may be thin films of ITO, titanium, aluminum, nickel, molybdenum, copper, gold, etc. In this embodiment, a patterned photoresist mask layer is formed on the upper surface of the InGaZnO active layer 5 by using a photolithography process, and then the source electrode layer 6 and the drain electrode layer 10 are sputtered on the InGaZnO active layer 5 and the photoresist mask layer by using a magnetron sputtering system or an electron beam evaporation system; and then the source electrode layer 6 and the drain electrode layer 10 are obtained by removing the photoresist through a stripping process.

[0055] Step S6 (corresponding to Figure 3 (4)): forming a top gate insulating layer 7 on the InGaZnO active layer 5 and the bottom gate insulating layer 3;

[0056] The top gate insulating layer 7 can be made of dielectric materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. In this embodiment, the top gate insulating layer 7 is formed on the InGaZnO active layer 5 and the bottom gate insulating layer 3 by PECVD process or ALD process, and the thickness of the top gate insulating layer 7 is 50nm-500nm.

[0057] Step S7 (corresponding to Figure 3 (5)): forming a top gate electrode layer 8 on the top gate insulating layer 7;

[0058] The top gate electrode layer 8 can be made of materials such as ITO, titanium, aluminum, nickel, molybdenum, copper, gold, etc. In this embodiment, a patterned photoresist mask layer is formed on the substrate by a photolithography process, and then a top gate thin film layer 7 is sputtered on the substrate layer 1 and the photoresist mask layer by a magnetron sputtering system or an electron beam evaporation system; and then the top gate electrode layer 8 is obtained by removing the photoresist through a stripping process.

[0059] Step S8 (corresponding to Figure 3 (6)): forming a passivation layer 9 on the top gate insulating layer 7, the source electrode layer 6, the drain electrode layer 10 and the top gate electrode layer 8;

[0060] The passivation layer 9 may be a dielectric material such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, etc. In this embodiment, the passivation layer 9 is formed on the top gate insulating layer 7, the source electrode layer 6, the drain electrode layer 10, and the top gate electrode layer 8 by using a PECVD process or an ALD process. Finally, the entire device is annealed in air or oxygen atmosphere for 2 hours, and the annealing temperature is about 250°C to 350°C.

[0061] Embodiment 2: The computer-readable storage medium of this embodiment stores a computer program, which, when executed by a processor, implements the steps in the method for preparing an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin-film transistor device of Embodiment 1.

[0062] The computer-readable storage medium of this embodiment may be an internal storage unit of the terminal, such as a hard disk or memory of the terminal; the computer-readable storage medium of this embodiment may also be an external storage device of the terminal, such as a plug-in hard disk, a smart memory card, a secure digital card, a flash memory card, etc. equipped on the terminal; further, the computer-readable storage medium may also include both an internal storage unit of the terminal and an external storage device.

[0063] The computer-readable storage medium of this embodiment is used to store computer programs and other programs and data required by the terminal. The computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0064] Embodiment 3: The computer device of this embodiment includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the method for preparing an amorphous InGaZnO / InAlSnO heterojunction composite channel dual-gate thin-film transistor device of Embodiment 1 are implemented.

[0065] In this embodiment, the processor may be a central processing unit, or other general-purpose processors, digital signal processors, application-specific integrated circuits, readily available programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0066] Those skilled in the art will appreciate that the contents disclosed in the embodiments may be provided as methods, systems, or computer program products. Therefore, the present solution may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware. Moreover, the present solution may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program codes.

[0067] The present solution is described with reference to the flowchart and / or block diagram of the method and computer program product according to the embodiment of the present solution. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions; these computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0068] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0070] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0071] The examples described in the present invention are merely descriptions of the preferred implementation modes of the present invention, and are not intended to limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various modifications and improvements made to the technical solutions of the present invention by engineers and technicians in this field should all fall within the protection scope of the present invention.

Claims

1. An amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device, characterized in that: include: Substrate layer, bottom gate electrode layer, top gate electrode layer, bottom gate insulating layer, top gate insulating layer, InAlSnO active layer, InGaZnO active layer, source electrode layer, drain electrode layer and passivation layer; The bottom gate electrode layer covers the center position of the upper surface of the substrate layer; The bottom gate insulating layer is located on the upper side of the bottom gate electrode layer and completely covers the upper surfaces of the substrate layer and the bottom gate electrode layer; The InAlSnO active layer is located in the middle of the upper side of the bottom gate insulating layer and is patterned; The InGaZnO active layer is located on the upper surface of the patterned InAlSnO active layer; the InAlSnO thin film material is combined with the amorphous InGaZnO thin film material to form an nN isotype heterostructure; the source electrode layer and the drain electrode layer are respectively formed on the upper surface of the InGaZnO active layer and patterned; The top gate insulating layer is arranged on the upper surface area of ​​the InGaZnO active layer and the bottom gate insulating layer; The top gate electrode layer is located in a central portion area aligned with the top gate insulating layer and is patterned; The passivation layer is respectively located on the upper surfaces of the top gate insulating layer, the source electrode layer, the drain electrode layer and the top gate electrode layer, and the passivation layer does not completely cover the source electrode layer and the drain electrode layer; and the top gate electrode layer is aligned with the InAlSnO and InGaZnO active layer regions outside for conductor processing.

2. The amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device according to claim 1, characterized in that: The substrate layer is made of glass or flexible material.

3. The amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device according to claim 1, characterized in that: The bottom gate electrode layer and the top gate electrode layer are one or more of ITO, titanium, aluminum, nickel, molybdenum, copper and gold; the thickness of the bottom gate electrode layer and the top gate electrode layer is 50nm-500nm.

4. The amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device according to claim 1, characterized in that: The bottom gate insulating layer and the top gate insulating layer are one of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide; the thickness of the bottom gate insulating layer and the top gate insulating layer is 50nm-500nm.

5. The amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device according to claim 1, characterized in that: The thickness of the InAlSnO active layer is 2nm-15nm, and the thickness of the InGaZnO active layer is 10nm-60nm.

6. The amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device according to claim 1, characterized in that: The source electrode layer and the drain electrode layer are one or more of ITO, titanium, aluminum, nickel, molybdenum, copper and gold; the thickness of the source electrode layer and the drain electrode layer is 100nm-500nm.

7. The amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device according to claim 1, characterized in that: The passivation layer material is one of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide; the passivation layer thickness is 100nm-1000nm.

8. A method for preparing an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device, characterized in that: The steps include: Step 1: Obtain and clean the substrate; Step 2: using a magnetron sputtering system or an electron beam evaporation system to deposit one or more thin films of ITO, titanium, aluminum, nickel, molybdenum, copper and gold as a bottom gate electrode layer; Step 3: using a plasma enhanced chemical vapor deposition process or an atomic layer deposition process to deposit a thin film of silicon oxide, silicon nitride, hafnium dioxide and aluminum oxide as a bottom gate insulating layer; Step 4: depositing an InAlSnO active layer and an InGaZnO active layer in sequence on the bottom gate insulating layer using a magnetron sputtering system; Step 5: Using a photolithography process and a wet or dry etching process to achieve device isolation on the InAlSnO active layer and the InGaZnO active layer; Step 6: Using a magnetron sputtering system or an electron beam evaporation system, a highly conductive thin film is deposited on the upper surface of the InGaZnO active layer to prepare a source electrode layer and a drain electrode layer; Step 7: Depositing a thin film of one of silicon oxide, silicon nitride and aluminum oxide as a top gate insulating layer on the upper surface of the InGaZnO active layer and the bottom gate insulating layer by a plasma enhanced chemical vapor deposition process or an atomic layer deposition process; Step 8: using a magnetron sputtering system or an electron beam evaporation system to deposit one or more thin films of ITO, titanium, aluminum, nickel, molybdenum, copper and gold as a top gate electrode layer on the central portion of the upper surface of the top gate insulating layer; Step 9: using a plasma enhanced chemical vapor deposition process or an atomic layer deposition process to prepare a thin film of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide as a passivation layer; Step 10: etching the passivation layer to expose the source electrode layer and the drain electrode layer by using a photolithography process and a wet or dry etching process; Step 11: annealing the thin film transistor at a high temperature of 250° C. to 350° C. for 2 hours in air or oxygen atmosphere.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the method for preparing an amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device as claimed in claim 8 are implemented.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the method for preparing the amorphous InGaZnO / InAlSnO heterojunction composite channel double-gate thin film transistor device as claimed in claim 8 are implemented.

Images