Motor simulation device and simulation method thereof

Abstract

The embodiment of the invention relates to the field of real-time simulation of power electronics, and provides a motor simulation device and a simulation method thereof, and the device comprises a motor simulator which comprises a core control unit provided with a first FPGA chip; the interface expansion box is provided with a second FPGA chip and is located outside the motor simulator; the interface expansion communication unit is configured to realize optical fiber communication between the core control unit and the interface expansion box; a to-be-tested motor and a sensing signal transmission unit, wherein the sensing signal transmission unit is configured to realize interaction of sensing signals between the interface expansion box and the to-be-tested motor; the first FPGA chip is configured to realize a sensing signal simulation algorithm, an optical fiber user layer protocol and a physical layer protocol; and the second FPGA chip is configured to realize sensing signal interface logic, an optical fiber user layer protocol and a physical layer protocol. The embodiment of the invention is at least beneficial to improving the universality of the motor simulation device and reducing the interference of other signals in the motor simulation device on the sensing signal.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of real-time simulation of power electronics, and in particular to a motor simulation device and a simulation method thereof. Background Art

[0002] As a typical electromechanical energy conversion device, motors are widely used in many traditional industries such as industrial control, transportation, water conservancy projects, medical care, consumer electronics, etc. According to authoritative statistics at home and abroad, the electric energy used by motor systems accounts for more than 60% of the total power generation. The energy saving of motor systems has a huge impact on my country's national policy of implementing energy conservation and emission reduction strategies. With the rapid development of emerging motor application fields and technologies such as new energy vehicles, wind power generation, locomotive traction, and ship electric propulsion, more and more new challenges are being raised to the performance testing technology of various motors and their drive controllers.

[0003] The motor simulator is based on the constructed dynamic mathematical model of the motor to achieve accurate simulation of the motor's driving and generating states. It combines the advantages of semi-physical simulation testing and bench testing, filling the gap between signal-level hardware-in-the-loop simulation (HiL) testing and power-level motor bench testing. It simulates various load conditions of the motor based on the motor drive controller and implements power hardware-in-the-loop testing (MCU Power-HiL) of the motor drive controller.

[0004] However, when the motor simulator and the drive controller of the motor to be tested communicate with each other, the signal transmitted between the two is easily interfered by the power devices in the motor simulator. Summary of the invention

[0005] The embodiments of the present disclosure provide a motor simulation device and a simulation method thereof, which are at least beneficial to improving the versatility of the motor simulation device and reducing the interference of other signals in the motor simulation device on the sensor signal.

[0006] According to some embodiments of the present disclosure, on the one hand, the embodiments of the present disclosure provide a motor simulation device, including: a motor simulator, the motor simulator including a core control unit, the core control unit including a first FPGA chip; an interface expansion box, located outside the motor simulator, the interface expansion box including a second FPGA chip; an interface expansion communication unit, configured to implement optical fiber communication between the core control unit and the interface expansion box; a motor to be tested and a sensor signal transmission unit, the sensor signal transmission unit being configured to implement interaction of sensor signals between the interface expansion box and the motor to be tested; wherein the first FPGA chip is configured to implement a sensor signal simulation algorithm, and an optical fiber user layer protocol and a physical layer protocol on the core control unit side; and the second FPGA chip is configured to implement a sensor signal interface logic, and an optical fiber user layer protocol and a physical layer protocol on the interface expansion box side.

[0007] In some embodiments, the core control unit is provided with a first high-speed serial interface, the interface expansion box is provided with a second high-speed serial interface, and the first high-speed serial interface and the second high-speed serial interface are configured to receive the same reference clock; the interface extension communication unit includes a first high-speed optical module, a transceiver optical fiber and a second high-speed optical module, wherein the first high-speed optical module is connected to the first high-speed serial interface, the second high-speed optical module is connected to the second high-speed serial interface, and the transceiver optical fiber connects the first high-speed optical module and the second high-speed optical module.

[0008] In some embodiments, the first FPGA chip includes a sensing signal simulation algorithm module, a first user layer protocol sending module, a first user layer protocol receiving module and a first physical layer communication module; wherein the first physical layer communication module is configured to receive a first signal transmitted by the interface expansion box based on the interface expansion communication unit; the first user layer protocol receiving module is configured to receive the first signal from the first physical layer communication module and transmit the first signal to the sensing signal simulation algorithm module; the sensing signal simulation algorithm module is configured to perform sensing signal simulation based on the first signal and output a second signal to the first user layer protocol sending module; the first user layer protocol sending module is configured to receive the second signal from the sensing signal simulation algorithm module and transmit it to the first physical layer communication module; the first physical layer communication module is also configured to transmit the second signal to the interface expansion box based on the interface expansion communication unit.

[0009] In some embodiments, the sensor signal simulation algorithm module is further configured to receive a control signal and perform sensor signal simulation based on the control signal and the first signal.

[0010] In some embodiments, the second FPGA chip includes a sensing signal hardware interface design module, a second user layer protocol sending module, a second user layer protocol receiving module and a second physical layer communication module; wherein the second physical layer communication module is configured to receive a second signal transmitted by the core control unit based on the interface extension communication unit; the second user layer protocol receiving module is configured to receive the second signal from the second physical layer communication module and transmit the second signal to the sensing signal hardware interface design module; the sensing signal hardware interface design module is configured to receive the second signal from the second user layer protocol receiving module and receive the first signal transmitted by the motor to be tested; the second user layer protocol sending module is configured to receive the first signal from the sensing signal hardware interface design module and transmit it to the second physical layer communication module; the second physical layer communication module is also configured to transmit the first signal to the core control unit based on the interface extension communication unit.

[0011] In some embodiments, the sensor signal hardware interface design module is further configured to design different sensor signal interfaces for interacting with the motor under test based on different types of the sensor signals, receive the first signal transmitted by the motor under test from some of the sensor signal interfaces, and transmit the received second signal to the remaining sensor signal interfaces.

[0012] In some embodiments, the sensing signal hardware interface design module includes an interface timing logic design unit and a signal conditioning unit; the interface timing logic design unit is configured to design different interface timing logics based on different types of the sensing signal; the signal conditioning unit is configured to condition the first signal and the second signal.

[0013] In some embodiments, the interface sequential logic design unit includes a first sequential logic design sub-unit and a second sequential logic design sub-unit; the signal conditioning unit includes a first conditioning sub-unit and a second conditioning sub-unit; wherein the first signal is transmitted sequentially from part of the sensor signal interface, the first conditioning sub-unit and the first sequential logic design sub-unit to the second user layer protocol sending module; the second signal is transmitted sequentially from the second user layer protocol receiving module, the second sequential logic design sub-unit and the second conditioning sub-unit to the remaining sensor signal interface.

[0014] In some embodiments, the sensing signal includes a position sensing signal or a temperature sensing signal.

[0015] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a motor simulation method, which is applied to the motor simulation device described in any of the above items, and the motor simulation method includes: realizing the interaction of sensor signals between the interface expansion box and the motor to be tested with the help of the sensor signal transmission unit; realizing optical fiber communication between the core control unit and the interface expansion box with the help of the interface expansion communication unit; and realizing the simulation of the motor to be tested through information interaction between the motor simulator and the motor to be tested.

[0016] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0017] On the one hand, the interface that needs to establish communication with the motor to be tested is designed on the interface extension box instead of the core control unit, so as to realize the physical extension of the sensor signal interface and reduce the type and number of interfaces required to be designed on the core control unit, thereby helping to reduce the interface design pressure on the core control unit. On the other hand, the interface extension communication unit is designed to realize the optical fiber communication between the core control unit and the interface extension box. Among them, since the transmission distance of the sensor signal between the designed interface extension box and the core control unit is relatively long, based on the high speed, low delay, and small delay jitter characteristics of optical fiber communication, the physical extension of the sensor signal interface realized by the interface extension box can be ignored for the performance impact on the motor simulation device, so as to ensure the low delay and low jitter of the sensor signal at a long distance, ensure the synchronization of the sensor signal, and effectively reduce the interference of the connection of other devices in the motor simulator except the core control unit to the sensor signal transmitted in the interface extension communication unit, further improving the accuracy of the sensor signal transmitted between the core control unit and the interface extension box. On the other hand, the first FPGA chip in the core control unit is used to implement the sensor signal simulation algorithm, and the second FPGA chip in the interface expansion box is used to implement the sensor signal interface logic, that is, the module that implements the sensor signal simulation algorithm function and the module that implements the sensor signal interface logic are dispersed on two FPGA chips, further reducing the design pressure on the core control unit. On the other hand, the second FPGA chip is designed to implement the sensor signal interface logic. In the case of a large number of sensor signal types, the second FPGA chip can also be used to design interfaces that match multiple types of motors to be tested, thereby helping to improve the versatility of the motor simulation device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of a motor simulation device provided by an embodiment of the present disclosure;

[0020] Figure 2 A partial structural schematic diagram of a motor simulation device provided by an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of the structure of a first FPGA chip in a motor simulation device provided in an embodiment of the present disclosure;

[0022] Figure 4 Another partial structural schematic diagram of a motor simulation device provided by an embodiment of the present disclosure;

[0023] Figure 5 Another structural schematic diagram of a motor simulation device provided by an embodiment of the present disclosure;

[0024] Figure 6 A schematic diagram of the structure of a second FPGA chip in a motor simulation device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] As can be seen from the background art, it is necessary to reduce interference with signals transmitted between a motor simulator and a drive controller of a motor to be tested.

[0026] After analysis, it was found that the motor simulator is mainly composed of a host computer, a core control unit, a bidirectional DC source, a power conversion unit, and a filter unit, among which the core control unit is connected to the motor to be tested. The motor model is constructed in the host computer, and parameters are sent to the core control unit and related status is displayed; the core control unit implements host computer parameter analysis and related status reporting, bidirectional DC source control, motor model algorithm, three-phase current tracking and power conversion control. The core control unit needs to collect the bidirectional DC source voltage output, three-phase line voltage and three-phase line current as the signal input of the motor model and three-phase current tracking.

[0027] It can be seen that the core control unit is not only connected to the power conversion unit, the two-phase DC source and the host computer, but also needs to collect the voltage output of the two-way DC source, the three-phase line voltage and the three-phase line current. On this basis, it is also necessary to communicate with the motor to be tested to implement the sensor signal simulation algorithm related to the motor to be tested in the core control unit. Therefore, many communication interfaces need to be designed on the core control unit to meet its communication connection with the above-mentioned many devices and the collection of current and voltage, which makes the interface design pressure on the core control unit relatively large. In addition, the core control unit and the motor controller to be tested generally perform the input and output connection of the sensor signal by means of physical connection. Since the core control unit is an internal component of the motor simulator, the physical connection between the core control unit and the motor controller to be tested is relatively long, and the physical connection and the connection between the core control unit and other devices in the motor simulator are all arranged in the motor simulator. The distance of many connections is relatively close, which causes the communication between the core control unit and the motor controller to be tested to be easily interfered by other devices inside the motor simulator, thereby affecting the sensor signal collection of the motor controller to be tested.

[0028] The present disclosure implements a motor simulation device and a simulation method thereof. In the motor simulation device, on the one hand, the interface that needs to establish communication with the motor to be tested is designed on the interface extension box instead of the core control unit, so as to realize the physical extension of the sensor signal interface, reduce the type and number of interfaces required to be designed on the core control unit, and thus help reduce the interface design pressure on the core control unit. On the other hand, the interface extension communication unit is designed to realize the optical fiber communication between the core control unit and the interface extension box. Among them, since the transmission distance of the sensor signal between the designed interface extension box and the core control unit is relatively far, based on the high speed, low delay, and small delay jitter characteristics of optical fiber communication, the physical extension of the sensor signal interface realized by the interface extension box can be ignored on the performance of the motor simulation device, so as to ensure the low delay and low jitter of the sensor signal at a long distance, ensure the synchronization of the sensor signal, and effectively reduce the interference of the connection of other devices in the motor simulator except the core control unit to the sensor signal transmitted in the interface extension communication unit, further improve the accuracy of the sensor signal transmitted between the core control unit and the interface extension box. On the other hand, the first FPGA chip in the core control unit is used to implement the sensor signal simulation algorithm, and the second FPGA chip in the interface expansion box is used to implement the sensor signal interface logic, that is, the module that implements the sensor signal simulation algorithm function and the module that implements the sensor signal interface logic are dispersed on two FPGA chips, further reducing the design pressure on the core control unit. On the other hand, the second FPGA chip is designed to implement the sensor signal interface logic. In the case of a large number of sensor signal types, the second FPGA chip can also be used to design interfaces that match multiple types of motors to be tested, thereby helping to improve the versatility of the motor simulation device.

[0029] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0030] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] In the description of the embodiments of the present application, when a certain component “includes” another component, unless otherwise stated, other components are not excluded and other components may be further included.

[0032] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0033] An embodiment of the present disclosure provides a motor simulation device, which will be described in detail below with reference to the accompanying drawings.

[0034] refer to Figure 1 , Figure 1A schematic diagram of a module structure of a motor simulation device provided for an embodiment of the present disclosure, the motor simulation device comprises: a motor simulator 100, the motor simulator 100 comprises a core control unit 101, the core control unit 101 comprises a first FPGA chip 111; an interface extension box 102, located outside the motor simulator 100, the interface extension box 102 comprises a second FPGA chip 112; an interface extension communication unit 103, configured to implement optical fiber communication between the core control unit 101 and the interface extension box 102; a motor to be tested 104 and a sensor signal transmission unit 105, the sensor signal transmission unit 105 is configured to implement the interaction of sensor signals between the interface extension box 102 and the motor to be tested 104; wherein the first FPGA chip 111 is configured to implement a sensor signal simulation algorithm, and an optical fiber user layer protocol and a physical layer protocol on the core control unit 101 side; and the second FPGA chip 112 is configured to implement a sensor signal interface logic, and an optical fiber user layer protocol and a physical layer protocol on the interface extension box 102 side.

[0035] It is worth noting that an interface expansion box 102 is designed outside the motor simulator 100, an interface expansion communication unit 103 is designed to realize optical fiber communication between the core control unit 101 and the interface expansion box 102, and a sensor signal transmission unit 105 is designed to realize the interaction of sensor signals between the interface expansion box 102 and the motor to be tested 104. With the help of the sensor signal transmission unit 105, the interface expansion box 102 and the interface expansion communication unit 103, the real-time interaction of sensor signals between the core control unit 101 and the motor to be tested 104 is realized.

[0036] On the one hand, the interface required to establish communication with the motor 104 to be tested is designed on the interface expansion box 102 rather than on the core control unit 101, thereby realizing the physical extension of the sensor signal interface and reducing the types and number of interfaces required to be designed on the core control unit 101, thereby helping to reduce the interface design pressure on the core control unit 101.

[0037] On the other hand, based on the design of the interface extension box 102, the interface extension communication unit 103 is designed to realize the optical fiber communication between the core control unit 101 and the interface extension box 102. Among them, since the transmission distance of the sensor signal between the designed interface extension box 102 and the core control unit 101 is relatively far, it is beneficial to realize the real-time interaction of the sensor signal between the core control unit 101 and the interface extension box 102 by taking advantage of the high speed, low delay, and small delay jitter of the optical fiber communication of the interface extension communication unit 103. In other words, based on the high speed, low delay, and small delay jitter of the optical fiber communication, the physical extension of the sensor signal interface realized by the interface extension box 102 can be ignored in terms of the performance impact on the motor simulation device, so as to ensure the low delay and low jitter of the sensor signal at a long distance and ensure the synchronization of the sensor signal.

[0038] Moreover, since the core control unit 101 and the interface expansion box 102 interact with each other through high-speed, low-latency, and low-jitter optical fibers rather than transmitting signals through physical connections, the interference of connections of other devices in the motor simulator 100 other than the core control unit 101 on the sensor signals transmitted in the interface expansion communication unit 103 is effectively reduced, further improving the accuracy of the sensor signals transmitted between the core control unit 101 and the interface expansion box 102.

[0039] On the other hand, the interface that cooperates with the motor to be tested is transferred from the core control unit 101 to the interface expansion box 102, and the first FPGA chip 111 in the core control unit 101 is used to implement the sensor signal simulation algorithm, and the second FPGA chip 112 in the interface expansion box 102 is used to implement the sensor signal interface logic. That is, the module that implements the sensor signal simulation algorithm function and the module that implements the sensor signal interface logic are dispersed on two FPGA chips, further reducing the design pressure on the core control unit 101.

[0040] On the other hand, the second FPGA chip 112 is designed to implement the sensor signal interface logic. When there are many types of sensor signals, the second FPGA chip 112 can be used to design interfaces that match various types of motors 104 to be tested. This not only effectively reduces the peripheral interface design pressure of the core control unit 101, but also helps to match the motor simulation device with various types of motors 104 to be tested, thereby improving the versatility of the motor simulation device.

[0041] In some cases, the interface extension box 102 is located outside the motor simulator 100. Compared with the core control unit 101, the interface extension box 102 can be designed to be closer to the motor to be tested 104, reducing the distance between the interface extension box 102 and the motor to be tested 104, so as to reduce the wiring length of the sensor signal transmission unit 105, thereby reducing the delay caused by the transmission of the sensor signal in the sensor signal transmission unit 105, and further ensuring the real-time interaction of the sensor signal between the core control unit 101 and the interface extension box 102. In one example, the sensor signal transmission unit 105 can be a physical connection.

[0042] In some cases, the core control unit 101 is connected to other devices in the motor simulator 100 via a power line. Based on this, an interface extension communication unit 103 is designed to realize optical fiber communication between the core control unit 101 and the interface extension box 102, which is beneficial to avoid the existence of a signal line located inside the motor simulator 100 between the core control unit 101 and the motor to be tested 104, thereby helping to avoid the signal line that transmits the sensor signal being close to the power line in the motor simulator 100, thereby avoiding the power line from causing greater interference to the signal line.

[0043] In some cases, based on the different types of motors 104 to be tested, the types and quantities of sensor signals that need to interact between the core control unit 101 and the motor 104 to be tested are different, and the multiple sensor signals can be transmitted with the help of the interface expansion communication unit 103. There is no need to design multiple signal lines for transmitting sensor signals between the core control unit 101 and the interface expansion box 102.

[0044] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0045] In some embodiments, reference Figure 2 , Figure 2 A partial structural diagram of a motor simulation device provided in an embodiment of the present disclosure, wherein a core control unit 101 is provided with a first high-speed serial interface, and an interface extension box 102 is provided with a second high-speed serial interface, and the first high-speed serial interface and the second high-speed serial interface are configured to receive the same reference clock clk; an interface extension communication unit 103 includes a first high-speed optical module 113, a transceiver optical fiber 123, and a second high-speed optical module 133, wherein the first high-speed optical module 113 is connected to the first high-speed serial interface, the second high-speed optical module 133 is connected to the second high-speed serial interface, and the transceiver optical fiber 123 is connected to the first high-speed optical module 113 and the second high-speed optical module 133.

[0046] In some examples, the first high-speed serial interface and the second high-speed serial interface are respectively connected to the same parameter clock crystal oscillator, so that the core control unit 101 and the interface extension communication unit 103 receive the same reference clock clk.

[0047] In some examples, the first high-speed optical module 113 and the second high-speed optical module 133 are of the same model, so as to further ensure the real-time interaction of the sensor signals between the core control unit 101 and the motor to be tested 104 .

[0048] In some embodiments, the sensing signal includes a position sensing signal or a temperature sensing signal.

[0049] It is worth noting that the types of sensor signals required to be transmitted between the core control unit 101 and the motor 104 to be tested may also be different based on the types of motors to be tested 104. Based on the various types of motors to be tested 104, the sensor signals include two categories: position sensor signals or temperature sensor signals. Among them, the position sensor signals include but are not limited to resolver signals, incremental encoding signals or Hall encoding signals, etc.; the temperature sensor signals are mainly signals simulated by thermistors.

[0050] Based on this, the interface connected to the motor 104 to be tested is externalized outside the motor simulator 100, and a second FPGA chip 112 is designed to implement the sensor signal interface logic. Even if there are many types of sensor signals, the second FPGA chip 112 can be used to design interfaces that match various types of motors 104 to be tested. This not only effectively reduces the peripheral interface design pressure of the core control unit 101, but also helps to make the motor simulation device match various types of motors 104 to be tested, thereby improving the versatility of the motor simulation device.

[0051] In some embodiments, reference Figure 3 , Figure 3 A structural schematic diagram of the first FPGA chip in the motor simulation device provided in one embodiment of the present disclosure, the first FPGA chip 111 may include a sensor signal simulation algorithm module 211, a first user layer protocol sending module 311, a first user layer protocol receiving module 411 and a first physical layer communication module 511.

[0052] Combined with reference Figure 1 and Figure 3The first physical layer communication module 511 is configured to receive the first signal singal1 transmitted by the interface extension box 102 based on the interface extension communication unit 103. The first user layer protocol receiving module 411 is configured to receive the first signal singal1 from the first physical layer communication module 511, and transmit the first signal singal1 to the sensing signal simulation algorithm module 211. The sensing signal simulation algorithm module 211 is configured to perform sensing signal simulation based on the first signal singal1, and output the second signal singal2 to the first user layer protocol sending module 311. The first user layer protocol sending module 311 is configured to receive the second signal singal2 from the sensing signal simulation algorithm module 211, and transmit it to the first physical layer communication module 511. The first physical layer communication module 511 is also configured to transmit the second signal singal2 to the interface extension box 102 based on the interface extension communication unit 103.

[0053] The following is a detailed description of the sensor signal transmitted between the motor to be tested 104 and the core control unit 101 as a resolver signal. Figure 3 and Figure 4 , Figure 4 This is another partial structural diagram of a motor simulation device provided in an embodiment of the present disclosure. The first signal singal1 may include an excitation acquisition signal singal11 , and the second signal singal2 may include an in-phase signal singal21 and an orthogonal signal singal22 .

[0054] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The sensing signal simulation algorithm module 211 may also be configured to receive a control signal control, and perform sensing signal simulation based on the control signal control and the first signal singal1.

[0055] In some cases, reference Figure 5 , Figure 5Another structural schematic diagram of a motor simulation device provided by an embodiment of the present disclosure, the motor simulator 100 may also include a host computer 106, a bidirectional DC source 107, a power conversion unit 108 and a filter unit 109. Among them, the host computer 106 and the core control unit 101 are connected in communication, the host computer 106 constructs a motor model, and sends parameters and displays related states to the core control unit 101; the core control unit 101 and the bidirectional DC source 107 are connected in communication, the core control unit 101 is also connected in communication with the power conversion unit 108, the core control unit 101 performs power control on the power conversion unit 108, and the core control unit 101 also collects the bidirectional DC source voltage output Udc, the three-phase line voltages Uab and Ubc, and the three-phase line currents Ia, Ib, and Ic.

[0056] In addition, the control signal control received by the sensor signal simulation algorithm module 211 is sent by the host computer 106 . The host computer 106 can send different types of control signals control to the sensor signal simulation algorithm module 211 based on the different types of the motor 104 to be tested.

[0057] In some cases, reference Figure 5 , the bidirectional DC source 107 is electrically connected to the power grid 119 .

[0058] The following is a detailed description by taking the example that the type of the sensor signal transmitted between the motor to be tested 104 and the core control unit 101 is a resolver signal.

[0059] Combined with reference Figure 3 and Figure 4 , the control signal control can be resolver pole pair number control1, resolver amplitude control control2 and motor mechanical speed control3. The sensor signal simulation algorithm module 211 performs sensor signal simulation based on the received excitation acquisition signal singal11, resolver pole pair number control1, resolver amplitude control control2 and motor mechanical speed control3, and outputs the in-phase signal singal21 and the orthogonal signal singal22 to the first user layer protocol sending module 311.

[0060] Combined with reference Figure 4 and Figure 5It is worth noting that the transmission line used for collecting the bidirectional DC source voltage output Udc, the three-phase line voltage Uab, Ubc, and the three-phase line current Ia, Ib, Ic in the core control unit 101 is the power line. The power signal transmitted in the power line is likely to cause greater interference to the signal line that transmits the sensor signal. Based on this, the interface extension communication unit 103 is designed to realize the optical fiber communication between the core control unit 101 and the interface extension box 102, which is conducive to avoiding the presence of a signal line located inside the motor simulator 100 between the core control unit 101 and the motor to be tested 104, thereby helping to avoid the signal line that transmits the sensor signal being close to the various power lines in the motor simulator 100, and avoiding the power line from causing greater interference to the signal line.

[0061] In some embodiments, reference Figure 6 , Figure 6 A structural schematic diagram of the second FPGA chip in the motor simulation device provided in one embodiment of the present disclosure, the second FPGA chip 112 may include a sensor signal hardware interface design module 212, a second user layer protocol sending module 312, a second user layer protocol receiving module 412 and a second physical layer communication module 512.

[0062] Combined with reference Figure 1 and Figure 3 The second physical layer communication module 512 is configured to receive the second signal singal2 transmitted by the core control unit 101 based on the interface extension communication unit 103. The second user layer protocol receiving module 412 is configured to receive the second signal singal2 from the second physical layer communication module 512, and transmit the second signal singal2 to the sensing signal hardware interface design module 212. The sensing signal hardware interface design module 212 is configured to receive the second signal singal2 from the second user layer protocol receiving module 412, and receive the first signal singal1 transmitted by the motor to be tested 104. The second user layer protocol sending module 312 is configured to receive the first signal singal1 from the sensing signal hardware interface design module 212, and transmit it to the second physical layer communication module 512. The second physical layer communication module 512 is also configured to transmit the first signal singal1 to the core control unit 101 based on the interface extension communication unit 103.

[0063] In some embodiments, in conjunction with reference Figure 5 and Figure 6The sensor signal hardware interface design module 212 can also be configured to design different sensor signal interfaces for interacting with the motor under test 104 for sensor signals based on different types of sensor signals, receive the first signal singal1 transmitted by the motor under test 104 from some sensor signal interfaces, and transmit the received second signal singal2 to the remaining sensor signal interfaces.

[0064] It is worth noting that for different types of motors 104 to be tested, the types of sensor signals may be different. Based on this, the sensor signal hardware interface design module 212 can change the type of interface for interacting with the motor 104 to be tested, so that the interface extension communication unit 103 can be adapted to multiple types of motors 104 to be tested, so that the motor simulator 100 can simulate multiple types of motors 104 to be tested, thereby helping to improve the versatility of the motor simulator 100.

[0065] The following is a detailed description by taking the example that the type of the sensor signal transmitted between the motor to be tested 104 and the core control unit 101 is a resolver signal.

[0066] In some cases, in conjunction with reference Figure 4 and Figure 5 Based on the fact that the sensing signal is a rotary signal, the sensing signal hardware interface design module 212 designs different sensing signal interfaces for interacting with the motor 104 under test for sensing signals, including an excitation signal interface 212a, an in-phase signal interface 212b, and an orthogonal signal interface 212c. Among them, the excitation signal interface 212a serves as an input interface to receive the excitation acquisition signal singal11 transmitted from the motor 104 under test; the in-phase signal interface 212b and the orthogonal signal interface 212c serve as output interfaces, the in-phase signal interface 212b provides the in-phase signal singal21 to the motor 104 under test, and the orthogonal signal interface 212c provides the orthogonal signal singal22 to the motor 104 under test.

[0067] In some embodiments, in conjunction with reference Figure 4 and Figure 6 The sensing signal hardware interface design module 212 includes an interface timing logic design unit 222 and a signal conditioning unit 232; the interface timing logic design unit 222 is configured to design different interface timing logics based on different types of sensing signals; the signal conditioning unit 232 is configured to condition the first signal singal1 and the second signal singal2.

[0068] It is worth noting that based on the possible different types of sensing signals, different interface timing logics are designed with the help of the interface timing logic design unit 222, so that the interface extension communication unit 103 has an interface adapted to the motor to be tested, thereby achieving the purpose of the interface extension communication unit 103 being adapted to multiple types of motors 104 to be tested.

[0069] In some cases, in conjunction with reference Figure 4 and Figure 5 The interface timing logic design unit 222 and the signal conditioning unit 232 correspond one to one, and the signal conditioning unit 232 and the sensor signal interface on the interface extension communication unit 103 for interacting with the motor 104 under test for sensor signals correspond one to one.

[0070] In some embodiments, in conjunction with reference Figure 4 and Figure 6 The interface sequential logic design unit 222 includes a first sequential logic design sub-unit 222a and a second sequential logic design sub-unit 222b; the signal conditioning unit 232 includes a first conditioning sub-unit 232a and a second conditioning sub-unit 232b; wherein the first signal singal1 is transmitted from part of the sensing signal interface, the first conditioning sub-unit 232a and the first sequential logic design sub-unit 222a to the second user layer protocol sending module 312 in sequence; the second signal singal2 is transmitted from the second user layer protocol receiving module 412, the second sequential logic design sub-unit 222b and the second conditioning sub-unit 232b to the remaining sensing signal interface in sequence.

[0071] The following is a detailed description by taking the example that the type of the sensor signal transmitted between the motor to be tested 104 and the core control unit 101 is a resolver signal.

[0072] In some cases, reference Figure 4 The excitation acquisition signal singal11 is transmitted to the first conditioning subunit 232a and the first sequential logic design subunit 222a via the excitation signal interface 212a and is transmitted to the second user layer protocol sending module 312. The first conditioning subunit 232a can be regarded as an input signal conditioning unit, and the first sequential logic design subunit 222a is used to implement the ADC interface sequential logic and convert the collected analog signal into a digital signal.

[0073] The second signal singal2 includes an in-phase signal singal21 and an orthogonal signal singal22. The second sequential logic design subunit 222b includes an in-phase sequential logic design subunit 322b corresponding to the in-phase signal singal21 and an orthogonal sequential logic design subunit 422b corresponding to the orthogonal signal singal22. The second conditioning subunit 232b includes an in-phase conditioning subunit 332b corresponding to the in-phase signal singal21 and an orthogonal conditioning subunit 432b corresponding to the orthogonal signal singal22. The second conditioning subunit 232b can be regarded as an output signal conditioning unit. The second sequential logic design subunit 222b is used to implement the DAC interface sequential logic and convert the digital signal into an analog signal.

[0074] Among them, the in-phase signal singal21 is transmitted from the second user layer protocol receiving module 412, the in-phase sequential logic design subunit 322b and the in-phase conditioning subunit 332b to the in-phase signal interface 212b in sequence; the orthogonal signal singal22 is transmitted from the second user layer protocol receiving module 412, the orthogonal sequential logic design subunit 422b and the orthogonal conditioning subunit 432b to the orthogonal signal interface 212c in sequence.

[0075] In summary, on the one hand, the interface design that needs to establish communication with the motor 104 to be tested is placed on the interface extension box 102 instead of the core control unit 101, so as to realize the physical extension of the sensor signal interface, which is conducive to reducing the interface design pressure on the core control unit 101. On the other hand, the interface extension communication unit 103 is designed to realize the optical fiber communication between the core control unit 101 and the interface extension box 102, which is conducive to realizing the real-time interaction of the sensor signal between the core control unit 101 and the interface extension box 102 by taking advantage of the high speed, low latency, and small delay jitter of the optical fiber communication of the interface extension communication unit 103, and effectively reducing the interference of the connection of other devices other than the core control unit 101 in the motor simulator 100 on the sensor signal transmitted in the interface extension communication unit 103, further improving the accuracy of the sensor signal transmitted between the core control unit 101 and the interface extension box 102. On the other hand, the module that realizes the sensor signal simulation algorithm function and the module that realizes the sensor signal interface logic are dispersed on two FPGA chips, which further reduces the design pressure on the core control unit 101. On the other hand, the second FPGA chip 112 is designed to implement the sensor signal interface logic. When there are many types of sensor signals, the second FPGA chip 112 can also be used to design interfaces that match various types of motors 104 to be tested, which is beneficial to improving the versatility of the motor simulation device.

[0076] Another embodiment of the present disclosure further provides a motor simulation method, which can be implemented by the above-mentioned motor simulation device. The motor simulation method provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the same or corresponding parts of the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments and will not be repeated below.

[0077] refer to Figure 1 The motor simulation method is applied to the motor simulation device provided in the aforementioned embodiment, and the motor simulation method includes: using the sensor signal transmission unit 105 to realize the interaction of sensor signals between the interface extension box 102 and the motor to be tested 104; using the interface extension communication unit 103 to realize the optical fiber communication between the core control unit 101 and the interface extension box 102; and realizing the simulation of the motor to be tested 104 through the information interaction between the motor simulator and the motor to be tested 104.

[0078] By taking advantage of the high speed, low delay, and small delay jitter characteristics of the optical fiber communication of the interface extension communication unit 103, the low delay and low jitter of the sensing signal at a long distance is ensured, and the synchronization of the sensing signal is ensured, so as to help improve the simulation accuracy of the motor 104 to be tested by the motor simulation method. In addition, the interface extension box 102 is arranged outside the motor simulator 100, which effectively reduces the interference of the connection of other devices in the motor simulator 100 except the core control unit 101 on the sensing signal transmitted in the interface extension communication unit 103, further improves the accuracy of the sensing signal transmitted between the core control unit 101 and the interface extension box 102, so as to further improve the simulation accuracy of the motor 104 to be tested by the motor simulation method.

[0079] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A motor simulation device, characterized in that: include: A motor simulator, wherein the motor simulator comprises a core control unit, and the core control unit comprises a first FPGA chip; An interface expansion box, located outside the motor simulator, wherein the interface expansion box includes a second FPGA chip; An interface extension communication unit, configured to implement optical fiber communication between the core control unit and the interface extension box; A motor to be tested and a sensor signal transmission unit, wherein the sensor signal transmission unit is configured to realize the interaction of sensor signals between the interface extension box and the motor to be tested; Among them, the first FPGA chip is configured to implement the sensor signal simulation algorithm, and the fiber optic user layer protocol and physical layer protocol on the core control unit side; the second FPGA chip is configured to implement the sensor signal interface logic, and the fiber optic user layer protocol and physical layer protocol on the interface expansion box side.

2. The motor simulation device according to claim 1, characterized in that: The core control unit is provided with a first high-speed serial interface, the interface extension box is provided with a second high-speed serial interface, and the first high-speed serial interface and the second high-speed serial interface are configured to receive the same reference clock; The interface extension communication unit includes a first high-speed optical module, a transceiver optical fiber, and a second high-speed optical module, wherein the first high-speed optical module is connected to the first high-speed serial interface, the second high-speed optical module is connected to the second high-speed serial interface, and the transceiver optical fiber connects the first high-speed optical module and the second high-speed optical module.

3. The motor simulation device according to claim 1 or 2, characterized in that: The first FPGA chip includes a sensing signal simulation algorithm module, a first user layer protocol sending module, a first user layer protocol receiving module and a first physical layer communication module; Wherein, the first physical layer communication module is configured to receive a first signal transmitted by the interface extension box based on the interface extension communication unit; The first user layer protocol receiving module is configured to receive the first signal from the first physical layer communication module and transmit the first signal to the sensing signal simulation algorithm module; The sensing signal simulation algorithm module is configured to perform sensing signal simulation based on the first signal and output a second signal to the first user layer protocol sending module; The first user layer protocol sending module is configured to receive the second signal from the sensing signal simulation algorithm module and transmit it to the first physical layer communication module; The first physical layer communication module is further configured to transmit the second signal to the interface extension box based on the interface extension communication unit.

4. The motor simulation device according to claim 3, characterized in that: The sensor signal simulation algorithm module is further configured to receive a control signal and perform sensor signal simulation based on the control signal and the first signal.

5. The motor simulation device according to claim 1 or 2, characterized in that: The second FPGA chip includes a sensing signal hardware interface design module, a second user layer protocol sending module, a second user layer protocol receiving module and a second physical layer communication module; Wherein, the second physical layer communication module is configured to receive a second signal transmitted by the core control unit based on the interface extension communication unit; The second user layer protocol receiving module is configured to receive the second signal from the second physical layer communication module and transmit the second signal to the sensing signal hardware interface design module; The sensing signal hardware interface design module is configured to receive the second signal from the second user layer protocol receiving module and receive the first signal transmitted by the motor to be tested; The second user layer protocol sending module is configured to receive the first signal from the sensing signal hardware interface design module and transmit it to the second physical layer communication module; The second physical layer communication module is further configured to transmit the first signal to the core control unit based on the interface extension communication unit.

6. The motor simulation device according to claim 5, characterized in that: The sensor signal hardware interface design module is also configured to design different sensor signal interfaces for interacting with the motor under test based on different types of the sensor signals, receive the first signal transmitted by the motor under test from some of the sensor signal interfaces, and transmit the received second signal to the remaining sensor signal interfaces.

7. The motor simulation device according to claim 6, characterized in that: The sensor signal hardware interface design module includes an interface timing logic design unit and a signal conditioning unit; The interface timing logic design unit is configured to design different interface timing logics based on different types of the sensing signal; The signal conditioning unit is configured to condition the first signal and the second signal.

8. The motor simulation device according to claim 7, characterized in that: The interface sequential logic design unit includes a first sequential logic design subunit and a second sequential logic design subunit; the signal conditioning unit includes a first conditioning subunit and a second conditioning subunit; Among them, the first signal is transmitted from part of the sensor signal interface, the first conditioning subunit and the first sequential logic design subunit to the second user layer protocol sending module in sequence; the second signal is transmitted from the second user layer protocol receiving module, the second sequential logic design subunit and the second conditioning subunit to the remaining sensor signal interface in sequence.

9. The motor simulation device according to claim 1, characterized in that: The sensing signal includes a position sensing signal or a temperature sensing signal.

10. A motor simulation method, characterized in that: The motor simulation device according to any one of claims 1 to 9, wherein the motor simulation method comprises: The sensor signal transmission unit is used to realize the interaction of sensor signals between the interface expansion box and the motor to be tested; Implementing optical fiber communication between the core control unit and the interface expansion box by means of the interface expansion communication unit; The simulation of the motor to be tested is achieved through information interaction between the motor simulator and the motor to be tested.

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