Method for determining instruction performance of a kernel program of a GPU, computing device, computer-readable storage medium, and computer program product

Abstract

The present disclosure provides a method, computing device, computer-readable storage medium and computer program product for determining the instruction performance of a kernel program of a GPU. The method includes: setting multiple performance counters in each EU of a GPU and corresponding the number of the performance counter to a continuous bit segment of the kernel program; during the instruction execution process of the continuous bit segment of the kernel program, if the instruction execution corresponding to the program counter is in a waiting state, the count value of the program counter remains unchanged, the count value of the performance counter increases by one every clock cycle, and if the instruction execution corresponding to the program counter is not in a waiting state, the performance counter increases with the count value of the program counter; and when the instruction execution of the continuous bit segment of the kernel program is completed, determining the count value of the performance counter as the instruction execution time of the continuous bit segment. This improves the efficiency of GPU instruction-level performance debugging and reduces hardware costs.

Description

Technical Field

[0001] The present disclosure generally relates to the field of processors, and more particularly, to a method for determining instruction performance of a kernel program of a GPU, a computing device, a computer-readable storage medium, and a computer program product. Background Art

[0002] Currently, graphics processing units (GPUs) or general-purpose graphics processing units (GPGPUs), collectively referred to as GPUs below, usually implement various computing tasks by running kernel programs. During GPU performance debugging, it is usually necessary to count which instructions or instruction segments (such as memory read and write, synchronization, and other operation instructions) take up the most absolute time or the most time proportion during the running of the kernel program, so as to locate performance bottlenecks and perform targeted software optimization on the kernel program.

[0003] Currently, it is very difficult to perform instruction-level performance debugging on kernel programs. It either requires high hardware costs or the design of specialized complex software. Summary of the invention

[0004] In view of the above problems, the disclosed solution sets a performance counter in the kernel program of the GPU, and counts the clock cycles consumed by each instruction or instruction segment during the running of the kernel program to simply and conveniently determine the instruction performance of a certain instruction or instruction segment of the kernel program. This improves the efficiency of GPU instruction-level performance debugging and significantly reduces hardware costs.

[0005] According to one aspect of the present disclosure, a method for determining the instruction performance of a kernel program of a GPU is provided. The method includes: setting a plurality of performance counters in each EU of the GPU and corresponding the number of the performance counter to a continuous bit segment of the kernel program; during the instruction execution process of the continuous bit segment of the kernel program, if the instruction execution corresponding to the program counter is in a waiting state, the count value of the program counter remains unchanged, the count value of the performance counter increases by one per clock cycle, and if the instruction execution corresponding to the program counter is not in a waiting state, the performance counter increases with the count value of the program counter; and when the instruction execution of the continuous bit segment of the kernel program is completed, determining the count value of the performance counter as the instruction execution time of the continuous bit segment.

[0006] In some implementations, corresponding the number of the performance counter to a continuous bit segment of the kernel program includes: corresponding the number of the performance counter to the highest bit segment of the program counter of the kernel program; and when the execution of the instruction of the continuous bit segment of the kernel program is completed, determining the count value of the performance counter as the instruction execution time of the continuous bit segment includes: for each performance counter number, when the execution of the kernel program is completed, determining the count value of the performance counter as the instruction execution time corresponding to the number of the performance counter.

[0007] In some implementations, the method further includes: traversing the highest bit segment of the program counter in the order of the numbers of the performance counters, and determining the instruction execution time corresponding to the number of each performance counter.

[0008] In some implementations, the method further includes: modifying the number of the performance counter so that it corresponds to the next continuous bit segment of the kernel program; determining whether the next continuous bit segment overflows; and if the next continuous bit segment does not overflow, determining the instruction execution time corresponding to the next continuous bit segment.

[0009] In some implementations, the method further includes, before modifying the number of the performance counter to correspond to the next consecutive bit segment of the kernel program: selecting an instruction segment with the largest count value of the performance counter in the highest bit segment of the program counter.

[0010] In some implementations, the method further includes: outputting each determined instruction execution time to a memory of the GPU, and the host of the GPU determines the instruction performance of each instruction segment of the kernel program based on the instruction execution time.

[0011] According to another aspect of the present invention, a computing device is provided, comprising: at least one processor; and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, wherein the instructions, when executed by the at least one processor, cause the computing device to perform the steps of the method described above.

[0012] According to yet another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program code is stored. When the computer program code is executed, the method described above is executed.

[0013] According to yet another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program performs the method described above when executed by a machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present disclosure will be better understood and other objects, details, features and advantages of the present disclosure will become more apparent through the description of specific embodiments of the present disclosure given with reference to the following drawings.

[0015] Figure 1 A schematic diagram of the structure of an exemplary computing system is shown.

[0016] Figure 2 An exemplary flow chart of a method for determining instruction performance of a kernel program of a GPU according to an embodiment of the present invention is shown.

[0017] Figure 3A An exemplary schematic diagram showing the relationship between a program counter and a performance counter according to an embodiment of the present invention.

[0018] Figure 3B Another exemplary schematic diagram shows the relationship between a program counter and a performance counter according to an embodiment of the present invention.

[0019] Figure 3C Another exemplary schematic diagram shows the relationship between a program counter and a performance counter according to an embodiment of the present invention.

[0020] Figure 4 An exemplary flow chart of a method for determining instruction performance of a kernel program of a GPU according to an embodiment of the present invention is shown.

[0021] Figure 5A Shows Figure 4 A schematic diagram of the results of the execution of the method shown.

[0022] Figure 5B Shows Figure 4 Another schematic diagram of the results of the execution of the method shown.

[0023] Figure 5C Shows Figure 4 Another schematic diagram of the execution result of the method shown. DETAILED DESCRIPTION

[0024] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "one embodiment" and "some embodiments" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0026] Figure 1 FIG. 1 shows a schematic diagram of an exemplary computing system 100. Figure 1 As shown in , the computing system 100 may include one or more GPUs 110 and a host 120. Each GPU 110 includes multiple execution units (EUs) 112. EU 112 is a computing unit in GPU 110 that is scheduled to run a warp. GPU 110 may also have various other computing units of different sizes. For example, multiple EUs 112, such as 4 EUs, may form a computing unit (CU), which is scheduled to run a thread block or thread group, and multiple CUs may form a computing cluster, which is scheduled to run a thread grid.

[0027] In addition, the GPU 110 may further include a storage unit, such as an on-chip memory 114 and an off-chip memory 116. The on-chip memory 114 is closer to the EU 112, has a larger transmission bandwidth, and a faster transmission speed, but generally has a smaller storage capacity, and the off-chip memory 116 generally has a larger storage capacity, but is farther from the EU 112, has a smaller transmission bandwidth, and a slower transmission speed.

[0028] The on-chip memory 114 can usually be implemented using a static random access memory (SRAM). The off-chip memory 116 can be located on a different chip from each EU 112 and the on-chip memory 114, and can be implemented using a dynamic random access memory (DRAM) or a high bandwidth memory (HBM).

[0029] The host 120 implements the computing task to be implemented by the computing system 100 by programming the computing task into a kernel program using the programming model and sending it to the GPU 110 for execution. When the kernel program is executed, all instructions of the kernel program will be executed in each EU 112. Therefore, the instruction performance of the kernel program, that is, the time consumed by the instructions or instruction segments of the kernel program to run in the EU 112 (also referred to as instruction execution time in this article), has a great impact on the performance of the GPU 110.

[0030] Currently, it is very difficult to perform instruction-level performance debugging on kernel programs. It either requires very high hardware costs or requires the design of specialized complex software. Currently, there is no simple and convenient method to determine the instruction performance of kernel programs.

[0031] In response to the above problems, the solution disclosed in the present invention sets a performance counter in the kernel program of the GPU, and counts the clock cycles consumed by each instruction or instruction segment during the running of the kernel program to simply and conveniently determine the instruction performance of a certain instruction or instruction segment of the kernel program. In addition, in a further implementation, the value of the performance counter can be changed (in order to distinguish it from the count value of the performance counter, the value of the performance counter is referred to as the number of the performance counter below, which is usually a continuous fixed value) to traverse the entire kernel program or a specific part thereof to determine the instruction performance of the entire kernel program or the specific part (such as the instruction or instruction segment that causes the performance bottleneck), so as to further locate the performance bottleneck of the GPU, thereby performing targeted software optimization.

[0032] Figure 2 An exemplary flow chart of a method 200 for determining instruction performance of a kernel program of a GPU according to an embodiment of the present invention is shown. Here, the method 200 is implemented by running the kernel program of the GPU 110 in each EU 112.

[0033] like Figure 2 As shown in FIG. 2 , in block 210 , a plurality of performance counters may be set in each EU 112 of the GPU 110 and the numbers of the performance counters may correspond to a continuous bit segment of the kernel program.

[0034] Currently, kernel programs usually count the instructions of kernel programs by setting a counter called a program counter. The count value of the program counter corresponding to an instruction can be used to indicate the order of the instruction in the kernel program. For example, a program containing 2 n instructions (furthermore, more than 2 n-1 and less than or equal to 2 nThe kernel program of the kernel program can use the program counter of n-bit binary number to count each instruction. For example, when n=16, the program counter can indicate each instruction of the kernel program through 16 bits of bit15~bit0.

[0035] In this article, the number of performance counters may be preset. In this case, the size of the continuous bit segment corresponding to each number of the performance counter may be different depending on the number of instructions included in the kernel program. Specifically, for a given number of performance counters, when the number of instructions included in the kernel program is large, the instruction segment corresponding to each number of the performance counter is also large, and when the number of instructions included in the kernel program is small, the instruction segment corresponding to each number of the performance counter is also small.

[0036] In addition, when the number of instructions contained in a given kernel program is different, if the number of performance counters is different, the size of the continuous bit segment corresponding to each number of the performance counter is also different.

[0037] FIG. 3A to FIG. 3C Three exemplary schematic diagrams showing the relationship between the program counter and the performance counter according to an embodiment of the present invention are shown. Figure 3A and Figure 3B shows the relationship between the program counter and the performance counter when the number of performance counters is the same (i.e., the number of bits of the performance counters is the same) and the number of instructions contained in the kernel program is different (i.e., the number of bits of the program counter is different); Figure 3B and Figure 3C The relationship between the program counter and the performance counter is shown when the number of instructions contained in the kernel program is the same (ie, the number of bits of the program counter is the same) and the number of performance counters is different (ie, the number of bits of the performance counter is different).

[0038] like Figure 3A As shown in , assuming that the number of performance counters is set to 16 (ie, 4 bits), the performance counters are numbered from 0000 to 1111 and assuming n=8, that is, the number of bits of the program counter is 8. In this case, each performance counter can correspond to a 4-bit continuous bit segment of the kernel program. Assuming that a performance counter corresponds to a continuous bit segment of the highest 4 bits (bit 7 to 4) of the kernel program, the performance counter can be used to evaluate a size of 2 4 For example, if the performance counter corresponds to the continuous bit segment of bits 6 to 3 of the kernel program, then the performance counter can be used to evaluate the performance of the instruction segment of size 2. 3The performance of the instruction segment of the instruction, that is, the instruction segment with the count value of the program counter *XXX X000 ~ *XXX X111. Among them, XXXX is the number of the performance counter, and * indicates the highest bit of the program counter (that is, bit7), which can be 0 or 1.

[0039] like Figure 3B As shown in , assuming that the number of performance counters is set to 8 (i.e., 3 bits), the performance counters are numbered from 000 to 111 and assuming n=16, i.e., the number of bits of the program counter is 16. In this case, each performance counter can correspond to a continuous bit segment of 3 bits of the kernel program. Assuming that a performance counter corresponds to a continuous bit segment of the highest 3 bits (bits 15 to 13) of the kernel program, the performance counter can be used to evaluate a size of 2 13 For example, if the performance counter corresponds to the continuous bit segment from bit 12 to bit 10 of the kernel program, then the performance counter can be used to evaluate the performance of the instruction segment of size 2. 10 The performance of the instruction segment of the 30000000 instruction is the instruction segment whose count value of the program counter is ***X XX00 0000 0000~***XXX11 1111 1111. Among them, XXX is the number of the performance counter, and *** indicates the highest 3 bits of the program counter, which can be any value from 000 to 111.

[0040] like Figure 3C As shown in the figure, assuming that the number of performance counters is set to 16 (ie, 4 bits), the performance counters are numbered from 0000 to 1111 and assuming n = 16, that is, the number of bits of the program counter is 16. In this case, each performance counter can correspond to a 4-bit continuous bit segment of the kernel program. Assuming that a performance counter corresponds to a continuous bit segment of the highest 4 bits (bits 15 to 12) of the kernel program, the performance counter can be used to evaluate a size of 2 12 For example, if the performance counter corresponds to the continuous bit segment of bits 11 to 8 of the kernel program, then the performance counter can be used to evaluate the performance of the instruction segment of size 2. 8The performance of the instruction segment of the 10000000 instruction, that is, the instruction segment whose program counter count value is **** XXXX 0000 0000~****XXXX 1111 1111. Among them, XXXX is the number of the performance counter, **** indicates the highest 4 bits of the program counter, which can be any value from 0000 to 1111.

[0041] Note that here, when only a certain instruction segment in the kernel program is to be evaluated for instruction performance, the host 120 may set the kernel program to set the performance counter to a certain specific number. When the instruction performance of the entire kernel program is to be evaluated, the kernel program may be run by increasing the number of the performance counter from small to large to traverse all instruction segments of the kernel program.

[0042] In addition, the continuous bit segment of the kernel program corresponding to the performance counter can also be arbitrarily set by the kernel program. For example, when the number of performance counters is set to 16 (i.e., 4 bits), the number of a performance counter can be used to evaluate the instruction performance of the instruction segment corresponding to the continuous bit segment of any 4 bits (such as bits 14 to 11, bits 13 to 10, etc.) of the program counter.

[0043] Here, when the performance counter is used to determine the instruction performance of the entire kernel program, the instruction performance of each instruction segment of a certain continuous bit segment can be determined by sequentially increasing the number of the performance counter, and then the continuous bit segment corresponding to the performance counter is shifted downward and the instruction performance of the next continuous bit segment is determined, until all instructions and instruction segments are traversed, as shown in the following combination Figure 4 and Figures 5A to 5C Described in detail.

[0044] In block 220, during the execution of the instruction of the continuous bit segment corresponding to the number of the performance counter in block 210, if the instruction execution corresponding to the program counter is in a waiting state, the count value of the program counter remains unchanged, and the count value of the performance counter increases by 1 every clock cycle. If the instruction execution corresponding to the program counter is not in a waiting state, the performance counter increases with the count value of the program counter.

[0045] That is, for each instruction in the instruction segment corresponding to the performance counter, if the execution of the instruction is in a waiting state, although the count value of the program counter remains unchanged (that is, the instruction remains unchanged), the count value of the performance counter increases with the number of waiting clock cycles; if the execution of the instruction is not in a waiting state, the performance counter increases by one for each instruction. Here, the instruction that may be in a waiting state may be, for example, a synchronization instruction, which is usually designed by the kernel program to wait for several clock cycles to achieve synchronization operations between various EUs 112.

[0046] In this way, when the execution of the continuous bit segment of the kernel program corresponding to the number of a performance counter is completed, the count value of the performance counter can indicate the total instruction execution time of the instruction / instruction segment of the continuous bit segment. Therefore, in block 230, the count value of the performance counter at this time can be used as the instruction execution time corresponding to the continuous bit segment.

[0047] In this way, for any specified performance counter number and its corresponding continuous bit segment of the kernel program, the instruction execution time corresponding to the continuous bit segment can be determined as an indication of the instruction performance of the instruction / instruction segment corresponding to the continuous bit segment.

[0048] In many cases, it is necessary to collect statistics on the instruction performance of all instructions of the entire kernel program to determine the direction of further optimization, or it is necessary to find abnormal performance areas of the kernel program (such as instructions or instruction segments whose instruction execution time is obviously too long). In this case, the above method 200 can be executed multiple times to traverse the entire kernel program.

[0049] Figure 4 An exemplary flow chart of a method 400 for determining instruction performance of a kernel program of a GPU according to an embodiment of the present invention is shown. Figures 5A to 5C Shows Figure 4 The method 400 is a schematic diagram of the execution result of the method 400 shown in FIG. Figure 2 A specific application of method 200, which utilizes Figure 2 The multiple performance counters set in the illustrated method 200 traverse the entire kernel program in the manner illustrated in the method 200 to determine the instruction performance or performance abnormality areas of all instructions / instruction segments of the kernel program.

[0050] like Figure 4 As shown in FIG. 4 , in block 410 , as a specific implementation of block 210 , the number of the performance counter may correspond to the highest bit segment of the program counter of the kernel program.

[0051] by Figure 3C For example, the number of performance counters is 16, numbered 0000 to 1111. In this case, in block 410, the performance counter may correspond to the instruction segment of the highest 4 bits (bits 15 to 12) of the kernel program, that is, the highest 4 bits of the program counter.

[0052] At block 420, the highest bit segment of the program counter may be traversed in the order of the program counter numbers (eg, from small to large or from large to small), and the highest bit segment of the program counter may be traversed in the order of the program counter numbers (eg, from small to large or from large to small). Figure 2 The instruction execution time corresponding to the number of each performance counter is determined in the manner described in blocks 220 and 230 .

[0053] like Figure 5A As shown in , the left column 510 shows a list of performance counter numbers, wherein each cell 512 indicates the number of a performance counter, which are arranged in ascending order from 0000 to 1111. The right column 520 shows a list of instruction execution times of the instruction segments corresponding to the remaining 12 bits of the program counter (i.e., the instruction segments of the program counter numbered XXXX 0000 0000 0000~XXXX 1111 1111 1111, where XXXX is the number of the performance counter) when the performance counter corresponds to the highest 4 bits of the program counter, wherein each cell 522 indicates the instruction execution time of the instruction segment corresponding to the performance counter given the number of the performance counter. In Figure 5A In the example shown, the number of the performance counter is the same as the highest 4 bits of the program counter, but the present invention is not limited to this, and the number of the performance counter can also be represented by other methods.

[0054] It can be seen that Figure 5A Each cell 522 of the chart shows a size of 2 12 The instruction execution time of the instruction segment of an instruction can indicate the instruction performance of the instruction segment. Figure 5A In the example, when the performance counter is numbered 4 (i.e., the highest bit segment of the program counter is 0100), the instruction execution time of the corresponding instruction segment is the longest or the proportion is the highest.

[0055] Next, in box 430, the number of the performance counter can be modified to correspond to the next continuous bit segment of the kernel program, and when it is determined that the next continuous bit segment has not overflowed (box 440 determines no), the operation of the above box 420 is repeated to determine the instruction execution time of the next continuous bit segment.

[0056] Here, the next continuous bit segment does not overflow means that the modified next continuous bit segment is still within the counting range of the program counter of the kernel program. For example, in the above example of n=16, assuming that the program counter indicates each instruction of the kernel program through 16 bits from bit15 to bit0, then the next continuous bit segment does not overflow means that the program counter of the modified continuous bit segment is still within the range of bit15 to bit0.

[0057] In one embodiment, method 400 is used to determine the performance abnormality area of ​​the kernel program. In this case, this loop can only determine the corresponding instruction performance for the instruction segment of interest. For example, assuming Figure 5A In the instruction segment where the highest bit of the program counter is 0100, the performance counter has the largest count value. Figure 5BIn the example, the performance evaluation can be performed only on the instruction segment of the next continuous bit segment of the program counter whose highest bit segment is 0100. In this case, the performance counter corresponds to the instruction segment of the next continuous bit segment bit 11~09 of the kernel program, that is, the next 4 bits of the highest 4 bits of the program counter.

[0058] In this case, when the next continuous bit segment is determined not to have overflowed at block 440, method 400 proceeds to block 420 and continues to perform the following steps: Figure 2 The instruction execution time of the corresponding instruction segment 0100 XXXX 0000 0000~0100XXXX 1111 1111 is determined in the manner described in blocks 220 and 230, where XXXX is the number of the performance counter.

[0059] like Figure 5B As shown in , the left column 530 shows the highest 4 bits of the program counter 0100, and the middle column 540 shows a list of performance counter numbers, where each cell 542 indicates the number of a performance counter, which are arranged in ascending order from 0000 to 1111. The right column 550 shows a list of instruction execution times for the remaining 8-bit instruction segments of the program counter (i.e., the instruction segments of the program counter numbered 0100 XXXX0000 0000~0100 XXXX 1111 1111, where XXXX is the number of the performance counter) when the performance counter corresponds to the next consecutive bit segment bits 11~09 of the program counter, where each cell 552 indicates the instruction execution time of the instruction segment corresponding to the performance counter given the number of the performance counter. In Figure 5B In the example shown, the number of the performance counter is the same as the next 4 bits of the highest 4 bits of the program counter, but the present invention is not limited to this, and the number of the performance counter can also be expressed in other ways.

[0060] On the other hand, if it is determined at block 440 that the next consecutive bit segment overflows, the method 400 ends. Figure 5C The result of the last execution of block 420 is shown, namely, the number of the performance counter corresponds to the lowest 4 bits of the program counter of the kernel program.

[0061] like Figure 5CAs shown in , the left column 560 shows the upper 12 bits of the program counter (for example, 0100 1000 1100), the middle column 570 shows a list of performance counter numbers, where each cell 572 indicates the number of a performance counter, which is arranged in ascending order from 0000 to 1111, and the right column 580 shows a list of instruction execution times of individual instructions when the performance counter corresponds to the continuous bit segment of the lowest 4 bits of the program counter, bit 03 to 00, where each cell 582 indicates the instruction execution time of the instruction corresponding to the performance counter given the number of the performance counter. Figure 5C In the example shown, the number of the performance counter is the same as the lowest 4 bits of the program counter, but the present invention is not limited to this, and the number of the performance counter can also be represented by other methods.

[0062] In other embodiments, the method 400 is used to determine the instruction performance of all instructions of the entire kernel program. In this case, the corresponding instruction performance can be determined for all instruction segments. For example, in the above block 420, not only for the next consecutive bit segment with the highest bit segment being 0100, but also for all the next consecutive bit segments with the highest bit segment being 0000 to 1111, the following are determined respectively: Figure 5B The instruction execution time is shown.

[0063] Furthermore, each time the kernel program is executed, the determined execution time of each instruction can be output to the memory of GPU 110, such as on-chip memory 114 or off-chip memory 116. In this way, Figure 1 The host 120 shown can read these instruction execution times and determine the instruction execution time of each instruction segment of interest of the kernel program, thereby determining the instruction performance of the corresponding instruction segment.

[0064] By using the solution disclosed in the present invention, a performance counter is set in the kernel program of the GPU, and the clock cycles consumed by each instruction or instruction segment are counted during the running of the kernel program to simply and conveniently determine the instruction performance of a certain instruction or instruction segment of the kernel program. In addition, in a further implementation, the instruction performance of the entire kernel program or a specific part thereof can be determined by traversing the entire kernel program or the specific part by changing the number of the performance counter, so as to further locate the performance bottleneck of the GPU, thereby performing targeted software optimization.

[0065] The solution of the present invention only needs to set up a performance counter in each EU, and the hardware cost is very small. When determining the instruction performance, it is only necessary to shift the continuous bit segments corresponding to the performance counter and execute simple bit comparison logic, and the software implementation is simple.

[0066] The method for determining the instruction performance of the kernel program of the GPU according to the present disclosure is described above in conjunction with the accompanying drawings. The method can be used in Figure 1 However, those skilled in the art will appreciate that the method described herein may also include more steps not shown in the figure.

[0067] The present invention may be implemented as a method, a computing device, a computer-readable storage medium, and / or a computer program product. A computer-readable storage medium stores a computer program code, which is used to perform the method of the present disclosure when it is executed. The computer program product includes a computer program, which performs the method of the present disclosure when it is executed. The computing device may include at least one processor and at least one memory coupled to the at least one processor, and the memory may store instructions for execution by the at least one processor. When the instructions are executed by the at least one processor, the computing device may execute the above method.

[0068] In one or more exemplary designs, the functions described in the present disclosure may be implemented using hardware, software, firmware, or any combination thereof. For example, if implemented using software, the functions may be stored as one or more instructions or codes on a computer-readable medium, or transmitted as one or more instructions or codes on a computer-readable medium.

[0069] Those skilled in the art should also understand that the various illustrative logical blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments of the present disclosure may be implemented as electronic hardware, computer software, or a combination of the two.

[0070] The above description of the present disclosure is intended to enable any person of ordinary skill in the art to implement or use the present disclosure. Various modifications of the present disclosure are obvious to those of ordinary skill in the art, and the general principles defined herein may also be applied to other variations without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is consistent with the broadest scope of the principles and novel features disclosed herein.

Claims

1. A method for determining instruction performance of a kernel program of a GPU, comprising: Setting a plurality of performance counters in each EU of the GPU and corresponding the numbers of the performance counters to a continuous bit segment of the kernel program; During the execution of the instruction of the continuous bit segment of the kernel program, if the instruction execution corresponding to the program counter is in a waiting state, the count value of the program counter remains unchanged, and the count value of the performance counter increases by one every clock cycle; if the instruction execution corresponding to the program counter is not in a waiting state, the performance counter increases along with the count value of the program counter; as well as When the execution of the instructions of the continuous bit segment of the kernel program is completed, the count value of the performance counter is determined as the instruction execution time of the continuous bit segment to indicate the instruction performance of the continuous bit segment.

2. The method of claim 1, wherein corresponding the number of the performance counter to a continuous bit segment of the kernel program comprises: Corresponding the number of the performance counter to the highest bit segment of the program counter of the kernel program; And when the execution of the instruction of the continuous bit segment of the kernel program is completed, determining the count value of the performance counter as the instruction execution time of the continuous bit segment includes: For each performance counter number, when the kernel program is executed, the count value of the performance counter is determined as the instruction execution time corresponding to the performance counter number.

3. The method of claim 2, further comprising: The highest bit segment of the program counter is traversed in the order of the numbers of the performance counters, and the instruction execution time corresponding to the number of each performance counter is determined.

4. The method of claim 3, further comprising: Modifying the number of the performance counter to make it correspond to the next consecutive bit segment of the kernel program; determining whether the next continuous bit segment overflows; as well as If the next continuous bit segment does not overflow, the instruction execution time corresponding to the next continuous bit segment is determined.

5. The method of claim 4 further comprising, before modifying the number of the performance counter to correspond to the next consecutive bit segment of the kernel program: Select the instruction segment with the largest count value of the performance counter in the highest bit segment of the program counter.

6. The method of claim 3, further comprising: Outputting the determined execution time of each instruction to the memory of the GPU, and The host of the GPU determines instruction performance of each instruction segment of the kernel program based on the instruction execution time.

7. A computing device comprising: at least one processor; as well as At least one memory, the at least one memory being coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, causing the computing device to perform the steps of the method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program code stored thereon, wherein the computer program code executes the method according to any one of claims 1 to 6 when executed.

9. A computer program product, comprising a computer program, which, when executed by a machine, performs the method according to any one of claims 1 to 6.

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