Multi-layer stacked chip packaging method

Abstract

The embodiment of the invention provides a multi-layer stacked chip packaging method, which comprises the following steps of: forming a plurality of chips, and forming conductive bumps on the first surfaces of the chips; forming a first plastic package body wrapping the chip and forming a first interconnection layer on the exposed conductive bumps to form a first chip module; forming a redistribution layer, forming a first convex column on the redistribution layer, and forming a dielectric column on the first convex column; fixing a chip on the rewiring layer and forming a second plastic package body on the rewiring layer; removing the dielectric columns to form blind holes, and forming second convex columns on the first convex columns to form plastic package body conductive columns; forming a second interconnection layer on the surface, deviating from the rewiring layer, of the second plastic package body to form a second chip module; and sequentially stacking the plurality of second chip modules on the substrate, and stacking the first chip module to the second chip module on the uppermost layer. According to the method, the structure storage capacity is improved, and the alignment precision requirement is reduced; the surface uniformity of the first convex column is improved when the second convex column is formed, and the stability and the reliability of the conductive column of the plastic package body are improved.

Description

Technical Field

[0001] The disclosed embodiments belong to the field of semiconductor packaging technology, and specifically relate to a multi-layer stacked chip packaging method. Background Art

[0002] like Figure 1 As shown, currently multiple memory chips 30 are stacked on a substrate 22 through a silicon interposer 24, and vertical interconnection is achieved using through silicon vias 32, wherein the top memory chip 36 has no through silicon via 32 structure; the more chips are stacked, the greater the storage capacity. As the number of chip stacking layers increases, the difficulty of alignment between each layer and the previous layer increases significantly, which brings severe challenges to the manufacturing process, thereby limiting the increase in the number of stacking layers and affecting the increase in storage capacity.

[0003] In view of the above problems, it is necessary to propose a multi-layer stacked chip packaging method that is reasonably designed and effectively solves the above problems. Summary of the invention

[0004] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a multi-layer stacked chip packaging method.

[0005] The present disclosure provides a multi-layer stacked chip packaging method, the method comprising:

[0006] Forming a plurality of chips, wherein a conductive bump is formed on a first surface of each of the chips;

[0007] forming a first plastic package body encapsulating the plurality of chips, and forming a first interconnection layer on the conductive bumps exposed by the first plastic package body to form a first chip module;

[0008] forming a redistribution layer, forming a first convex column on the redistribution layer, and forming a dielectric column on the first convex column;

[0009] Fixing a plurality of the chips to the redistribution layer, and forming a second plastic package on the redistribution layer to respectively encapsulate the chips, the first convex pillars and the dielectric pillars;

[0010] The dielectric column is removed to form a blind hole, and a second convex column is formed in the blind hole, wherein the second convex column is connected to the first convex column to form the conductive column of the plastic package;

[0011] Forming a second interconnection layer electrically connected to the conductive pillars of the plastic package on a surface of the second plastic package away from the redistribution layer to form a second chip module;

[0012] Multiple second chip modules are stacked in sequence on the substrate through the second interconnection layer, and the first chip modules are stacked to the uppermost second chip module through the first interconnection layer, wherein the plastic package conductive pillars realize vertical interconnection between the chip modules.

[0013] Optionally, a plurality of the second chip modules are sequentially stacked on the substrate through the second interconnect layer, and the first chip modules are stacked to the uppermost second chip module through the first interconnect layer, comprising:

[0014] The second interconnection layer of the second chip module at the bottom is electrically connected to the substrate;

[0015] The second interconnect layer of the second chip module at the upper layer is electrically connected to the redistribution layer of the second chip module at the lower layer;

[0016] The first interconnect layer of the first chip module is electrically connected to the redistribution layer of the uppermost second chip module.

[0017] Optionally, forming a first convex column on the redistribution layer includes:

[0018] forming a first photoresist layer on the redistribution layer;

[0019] sequentially exposing and developing the first photoresist layer to form a first opening on the first photoresist layer;

[0020] The first protrusion is formed in the first opening by an electroplating process.

[0021] Optionally, forming a dielectric column on the first convex column includes:

[0022] forming a second photoresist layer on the redistribution layer to wrap the first convex pillar;

[0023] The second photoresist layer is sequentially exposed and developed to form the dielectric pillar on the first convex pillar; wherein,

[0024] The size of the dielectric pillar is the same as that of the first convex pillar.

[0025] Optionally, removing the dielectric pillar to form a blind hole, and forming a second convex pillar in the blind hole includes:

[0026] Removing the dielectric column to form the blind hole on the second plastic package body to expose the first convex column;

[0027] The second convex column is formed on the first convex column exposed in the blind hole by using an electroplating process; wherein,

[0028] The size of the first protrusion is the same as the size of the second protrusion.

[0029] Optionally, fixing the plurality of chips to the redistribution layer includes:

[0030] Fixing the second surfaces of the plurality of chips to the redistribution layer;

[0031] The forming of the second plastic package body comprises:

[0032] forming the second plastic package body on the redistribution layer;

[0033] The side of the second plastic package body facing away from the redistribution layer is thinned to expose the conductive bumps and the dielectric pillars on the first surface of the chip.

[0034] Optionally, forming a second interconnect layer electrically connected to the conductive pillars of the plastic package on a surface of the second plastic package away from the redistribution layer includes:

[0035] forming a third photoresist layer on a surface of the second plastic package body away from the redistribution layer;

[0036] Patterning the third photoresist layer to form corresponding second openings on the corresponding exposed conductive bumps and conductive columns of the plastic package body;

[0037] A second soldering point is formed in the second opening, and the second soldering point is electrically connected to the corresponding conductive bump and the conductive column of the plastic package body respectively.

[0038] Optionally, the step of fixing the plurality of chips to the redistribution layer further comprises:

[0039] Fixing the first surfaces of the plurality of chips to the redistribution layer, wherein the conductive bumps are electrically connected to the redistribution layer;

[0040] The forming of the second plastic package body further includes:

[0041] forming the second plastic package body on the redistribution layer;

[0042] The side of the second plastic package body facing away from the redistribution layer is thinned to expose the dielectric column.

[0043] Optionally, the second interconnect layer electrically connected to the conductive pillars of the plastic package body is formed on a surface of the second plastic package body away from the redistribution layer, and further includes:

[0044] Forming a wiring layer on a surface of the second plastic package body away from the redistribution layer, wherein the wiring layer is electrically connected to the conductive pillars of the plastic package body;

[0045] A plurality of solder balls electrically connected to the wiring layer are formed on the wiring layer, and the wiring layer and the solder balls together constitute the second interconnection layer.

[0046] Optionally, after stacking a plurality of the second chip modules in sequence on the substrate through the second interconnect layer, and stacking the first chip modules to the uppermost second chip module through the first interconnect layer, the method further comprises:

[0047] An underfill layer is formed between the first chip module and the uppermost second chip module, between two adjacent second chip modules, and between the lowermost second chip module and the substrate.

[0048] In the multi-layer stacked chip packaging method of the disclosed embodiment, multiple chips can be arranged in each first chip module and the second chip module, which significantly improves the storage capacity of the chip packaging structure, reduces the number of stacking layers, and improves the stability of the entire chip packaging structure; the chip modules are vertically interconnected by plastic-encapsulated conductive columns with larger diameters, and the plastic-encapsulated conductive columns can be better aligned with the redistribution layer and the pads of the substrate, significantly reducing the alignment accuracy requirements and improving the stability of the chip packaging structure. By pre-forming the first convex column, the depth-to-width ratio of the blind hole is optimized when the plastic-encapsulated conductive column is formed, so that when the second convex column is formed in the blind hole, the uniformity of the second convex column surface is improved, thereby improving the reliability of the entire plastic-encapsulated conductive column, thereby improving the reliability of the entire chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of a multi-layer stacked chip packaging structure in the prior art;

[0050] Figure 2 A schematic diagram of a multi-layer stacked chip packaging method according to an embodiment of the present disclosure;

[0051] Figure 3 is a top view of a wafer according to an embodiment of the present disclosure;

[0052] Figure 4 A schematic diagram of a process for forming a plurality of chips in the first embodiment and the second embodiment of the present disclosure;

[0053] Figure 5 It is a schematic diagram of a process for forming a first plastic package body in the first embodiment and the second embodiment of the present disclosure;

[0054] Figure 6 It is a schematic diagram of a process for thinning the first plastic package body in the first embodiment and the second embodiment of the present disclosure;

[0055] Figure 7It is a schematic diagram of a process of forming a first interconnection layer to form a first chip module in the first embodiment and the second embodiment of the present disclosure;

[0056] Figure 8 It is a schematic diagram of a process of forming a first protrusion on a redistribution layer and forming a dielectric column on the first protrusion in an embodiment of the present disclosure;

[0057] Fig. 9 This is a schematic diagram of a process of fixing a plurality of chips on a redistribution layer and forming a second plastic package body according to a first embodiment of the present disclosure;

[0058] Fig.10 It is a schematic diagram of a process for forming a conductive column of a plastic package body according to the first embodiment of the present disclosure;

[0059] Fig.11 It is a schematic diagram of a process for forming a second interconnection layer in the first embodiment of the present disclosure;

[0060] Fig.12 A schematic diagram of a process of sequentially stacking a first chip module and a plurality of second chip modules on a substrate and forming a chip packaging structure according to a first embodiment of the present disclosure;

[0061] Fig.13 This is a schematic diagram of a process for fixing multiple chips on a redistribution layer and forming a second plastic package body according to a second embodiment of the present disclosure;

[0062] Fig.14 It is a schematic diagram of a process for forming a conductive column of a plastic package body according to a second embodiment of the present disclosure;

[0063] Fig.15 A schematic diagram of a process of forming a second interconnection layer to form a second chip module according to a second embodiment of the present disclosure;

[0064] Fig.16 It is a structural schematic diagram of a chip packaging structure formed when the chip of the second embodiment of the present disclosure is not exposed from the second plastic packaging body;

[0065] Fig.17 This is a schematic diagram of a process of sequentially stacking a first chip module and a plurality of second chip modules on a substrate to form a chip packaging structure in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0067] like Figure 2As shown, the embodiment of the present disclosure provides a multi-layer stacked chip packaging method S100, the method S100 comprising:

[0068] S110, forming a plurality of chips, wherein a conductive bump is formed on a first surface of each chip.

[0069] like Figure 3 and Figure 4 As shown, first, Figure 4 As shown in FIG. 1 , a wafer 42 is provided, wherein a passivation layer 46 and a pad 44 are sequentially disposed on a first surface of the wafer 42. The first surface of the wafer 42 is the front surface of the wafer 42. That is, a passivation layer 46 and a pad 44 are sequentially disposed on the front surface of the wafer 42.

[0070] Next, a conductive bump 50 is formed on the pad 44 to correspond to and be electrically connected to the pad 44 .

[0071] Specifically, Figure 4 As shown in FIG. 2 b, a photoresist is spin-coated on the front side of the wafer 42 to form a first photoresist layer 48, and the first photoresist layer 48 is exposed and developed to form a first window in the first photoresist layer 48 at a position corresponding to the pad 44. Figure 4 As shown in FIG. 3 , a conductive bump 50 is formed at the opening by electroplating. In this embodiment, the conductive bump 50 is a copper conductive bump and is electrically connected to the pad 44. Figure 4 As shown in FIG. 4 , the remaining first photoresist layer 48 is removed by etching or other processes.

[0072] Then, the wafer 42 is cut into a plurality of chips 52 , wherein a conductive bump 50 electrically connected to the pad 44 of each chip 52 is formed on a first surface of each chip 52 .

[0073] Specifically, Figure 4 As shown in FIG. 4 , according to packaging requirements, the wafer 42 is cut to form a plurality of chips 52 , and a conductive bump 50 corresponding to the chip 52 is formed on the pad 44 on the front side.

[0074] It should be noted that, in this embodiment, the type of chip 52 is not specifically limited. In this embodiment, the first surface of the chip 52 is taken as the front side of the chip 52, and the second surface of the chip 52 is taken as the back side of the chip 52, and the type of chip 52 is taken as a memory chip.

[0075] S120, forming a first plastic package body encapsulating the plurality of chips, and forming a first interconnection layer on the conductive bumps exposed by the first plastic package body to form a first chip module.

[0076] Specifically, Figure 5As shown, the specific process of forming the first plastic package body 62 in step S120 is as follows:

[0077] like Figure 5 As shown in FIG. 1 , a temporary carrier 56 is provided, and a temporary bonding adhesive layer 54 is disposed on the temporary carrier 56. The front surfaces of the plurality of chips 52 are fixed on the temporary bonding adhesive layer 54. Figure 5 As shown in b, a first plastic package 62 encapsulating multiple chips 52 is formed on the temporary bonding adhesive layer 54. Figure 5 As shown in FIG. 3 c, the first plastic package body 62 is thinned on a side facing away from the temporary carrier 56 by grinding to expose the back sides of the multiple chips 52.

[0078] It should be noted that the plurality of chips 52 are horizontally laid out in the first plastic package 62 . The number of the chips 52 is not specifically limited in this embodiment and can be selected according to actual needs.

[0079] Among them, Figure 6 As shown, the specific process of forming the first interconnection layer in step S120 is as follows:

[0080] like Figure 6 As shown in FIG. 1 , a first temporary bonding adhesive layer 54 ′ and a first temporary carrier 56 ′ are sequentially arranged on the surface of the first plastic package 62 away from the temporary carrier 56 and the back of the chip 52. Figure 6 As shown in FIG. 2 b, the first plastic package body 62 is turned over to make the first temporary carrier 56 ′ serve as a supporting carrier, and the temporary carrier 56 and the temporary bonding adhesive layer 54 are removed.

[0081] refer to Figure 7 As shown in FIG. 7a, a photoresist is spin-coated on the surface of the first plastic package 62 away from the first temporary carrier 56' to form a second photoresist layer 68, and the second photoresist layer 68 is exposed and developed to form a second window at a position corresponding to the conductive bump 50 to expose the conductive bump 50. Figure 7 As shown in b, solder 70 is electroplated at the second window. Figure 7 As shown in Fig. c, the remaining second photoresist layer 68 is removed by etching or other processes. Figure 7 d, the solder 70 is reflowed to form a first solder joint 72 on the conductive bump 50, and the first solder joint 72 is electrically connected to the conductive bump 50. In other words, the first interconnect layer is a plurality of first solder joints 72 electrically connected to the conductive bump 50. In this embodiment, the first solder joint 72 can be a solder ball.

[0082] like Figure 7As shown in Fig. 5 , after forming a plurality of first solder joints 72, the first temporary bonding adhesive layer 54' is separated from the first plastic package 6 to form a first chip module A. That is, the first chip module A includes a first plastic package 62, a plurality of chips 52 wrapped in the first plastic package 62, and a first interconnection wiring layer arranged on the conductive bumps 50 of the chip 52. Among them, a conductive bump 50 electrically connected to the pad 44 is arranged on the pad 44 on the front of the chip 52, and the surface of the conductive bump 50 is flush with the surface of the first plastic package 62. The first chip module A realizes vertical interconnection with other chip modules through the first interconnection layer.

[0083] In this embodiment, a plurality of chips are arranged flatly in the first chip module, which significantly improves the storage capacity of the chip packaging structure, reduces the number of stacking layers, and improves the stability of the entire chip packaging structure.

[0084] S130, forming a redistribution layer, forming a first convex column on the redistribution layer, and forming a dielectric column on the first convex column.

[0085] The specific process of forming the redistribution layer 58 in step S130 is as follows:

[0086] like Figure 8 As shown in FIG. 1 , a dielectric layer is formed on the temporary bonding adhesive layer 54 of the temporary carrier 56, the dielectric layer is patterned by a photolithography process, and an interconnection metal layer is formed on the patterned dielectric layer by a process such as electroplating or sputtering, thereby forming a redistribution layer 58. It should be noted that the number of layers of the redistribution layer 58 is not specifically limited in this embodiment and can be selected according to actual needs.

[0087] Among them, Figure 8 As shown, the specific process of forming the first protrusion 80 on the redistribution layer 58 in step S130 may be as follows:

[0088] First, a first photoresist layer is formed on the redistribution layer.

[0089] Specifically, a first photoresist layer is formed on the redistribution layer 58 by spin coating, spray coating, physical vapor deposition (PVD), chemical vapor deposition (CVD) and other processes. The first photoresist layer may be a positive photoresist or a negative photoresist. For example, the first photoresist layer may be a polymer such as polyimide (PI), polybenzoxazole (PBO), or benzocyclobutene (BCB). In this embodiment, the first photoresist layer is described as a positive photoresist.

[0090] Secondly, the first photoresist layer is exposed and developed in sequence to form a first opening on the first photoresist layer.

[0091] Specifically, a first mask is provided, on which a preset shape matching the first convex column is arranged. The first mask is placed above the first photoresist layer, and the first photoresist layer is exposed and developed using the first mask as a mask.

[0092] In this embodiment, the first photoresist layer adopts positive photoresist, so the first photoresist layer covered by the first mask is insoluble in the developer, and the first photoresist layer not covered by the first mask is dissolved in the developer to form a first opening on the first photoresist layer. In this way, the preset pattern of the first convex column on the first mask is transferred to the first photoresist layer.

[0093] Finally, the first protrusion is formed in the first opening by an electroplating process.

[0094] Specifically, a copper metal solution is electroplated in the first opening by an electroplating process to form a copper layer in the first opening. Figure 8 a shows the first protrusion 80. That is, the first protrusion 80 is a copper column.

[0095] The specific process of forming the dielectric pillar 82 on the first convex pillar 80 in step S130 may be as follows:

[0096] First, a second photoresist layer is formed on the redistribution layer to wrap the first convex pillar.

[0097] Specifically, a second photoresist layer is formed on the redistribution layer 58 by spin coating, spray coating, physical vapor deposition (PVD), chemical vapor deposition (CVD) and other processes, wherein the second photoresist layer can be a positive photoresist or a negative photoresist, for example, the second photoresist layer can be a polymer such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), etc. In this embodiment, the second photoresist layer is described as a negative photoresist.

[0098] It should be noted that, in this embodiment, the thickness of the second photoresist layer is twice the length of the first protrusion 80 .

[0099] Next, the second photoresist layer is exposed and developed in sequence to form the dielectric pillar 82 on the first convex pillar 80 . The size of the dielectric pillar 82 is the same as that of the first convex pillar 80 .

[0100] Specifically, a second mask is provided, on which a preset shape matching the dielectric pillar is arranged. The second mask is placed above the second photoresist layer, wherein the position of the preset shape on the second mask corresponds to the position of the first convex pillar. The second photoresist layer is exposed and developed using the second mask as a mask.

[0101] In this embodiment, the second photoresist layer adopts negative photoresist, so the second photoresist layer covered by the second mask is soluble in the developer, and the second photoresist layer not covered by the second mask is insoluble in the developer, so that a layer as shown in FIG. Figure 8 b shows the dielectric pillar 82. That is, in this embodiment, the dielectric pillar 82 is a photoresist pillar. In this embodiment, the size of the dielectric pillar 82 is the same as the size of the first convex pillar 80. That is, the length, width and height of the dielectric pillar 82 are the same as those of the first convex pillar 80.

[0102] It should be noted that, in addition to the photoresist pillars described in this embodiment, the dielectric pillars 82 may also be pillars made of other materials, as long as the blind holes 67 can be formed on the second plastic packaging layer 62 ′ after the dielectric pillars 82 are removed.

[0103] S140, fixing the plurality of chips on the redistribution layer, and forming a second plastic package on the redistribution layer to respectively encapsulate the chips, the first convex pillars and the dielectric pillars.

[0104] Among them, Fig. 9 As shown, in the first embodiment, the process of fixing the plurality of chips to the redistribution layer in step S140 may be specifically as follows:

[0105] like Fig. 9 As shown in FIG. 1 , the second surfaces of the plurality of chips 52 are fixed to the redistribution layer 58. Specifically, the back surfaces of the plurality of chips 52 are fixed to the flat dielectric layer of the redistribution layer 58 by means of an adhesive layer 60, so as to increase the firmness of the chips 52. That is, the redistribution layer 58 may only be provided with a dielectric layer in the region where the chips 52 are fixed, without providing an interconnection metal layer.

[0106] In the first embodiment, the specific process of forming the second plastic package body 62' is as follows:

[0107] like Fig. 9 As shown in FIG. 2 , a second plastic package 62 ′ is formed on the redistribution layer 58 by vacuum lamination of the film layer or conventional plastic packaging process. The second plastic package 62 ′ wraps the chip 52 , the first convex column 80 and the dielectric column 82 to protect the chip 52 , the first convex column 80 and the dielectric column 82 .

[0108] like Fig.10 As shown in FIG. 1 , the surface of the second plastic package 62′ away from the redistribution layer 58 is thinned by a process such as grinding to expose the conductive bumps 50 and the dielectric pillars 82 on the first surface of the chip 52. Specifically, the surface of the second plastic package 62′ away from the redistribution layer 58 is thinned by a process such as grinding to expose the conductive bumps 50 and the photoresist pillars on the front side of the chip 52.

[0109] In the second embodiment, if Fig.13As shown, the specific process of fixing the plurality of chips 52 to the redistribution layer 58 is as follows:

[0110] like Fig.13 As shown in FIG. 1 , after forming the redistribution layer 58, the first surfaces of the plurality of chips 52 are fixed to the redistribution layer 58, wherein the conductive bumps 50 are electrically connected to the redistribution layer 58. Specifically, the front surfaces of the plurality of chips 52 are flip-chip fixed to the interconnection metal layer of the redistribution layer 58 through the plurality of solder balls 53. In other words, the plurality of chips 52 are soldered to the interconnection metal layer of the redistribution layer 58 through the plurality of solder balls 53.

[0111] In the second embodiment, the specific process of forming the second plastic package body 62' is as follows:

[0112] like Fig.13 As shown in FIG. 2 , a second plastic package 62 ′ is formed on the redistribution layer 58 by vacuum lamination of the film layer or conventional plastic packaging process. The second plastic package 62 ′ wraps the plurality of chips 52 , the first convex pillars 80 and the dielectric pillars 82 , thereby protecting the plurality of chips 52 , the first convex pillars 80 and the dielectric pillars 82 .

[0113] The surface of the second plastic package body 62 ′ facing away from the redistribution layer 58 is thinned by a grinding process or the like to expose the dielectric pillars 82 .

[0114] It should be noted that if Fig.14 As shown in FIG. 1 , in the second embodiment, after the second plastic package 62' is formed, the second plastic package 62' can be thinned to expose the back side of the chip 52 and the dielectric pillar 82 at the same time. Whether the second plastic package 62' needs to be thinned to expose the back side of the chip 52 can be selected according to actual needs, and this embodiment does not make any specific limitation.

[0115] In this embodiment, high-density interconnection between chips is achieved by forming a redistribution layer in the second chip module.

[0116] S150, removing the dielectric column to form a blind hole, and forming a second convex column in the blind hole, wherein the second convex column is connected to the first convex column to form a plastic package conductive column.

[0117] like Fig.10 and Fig.14 As shown, in the first embodiment and the second embodiment, after forming the second plastic encapsulation layer 62', the dielectric pillar 82 is removed to form a blind hole 64, and a second convex pillar 65 is formed in the blind hole 64. The specific process of forming the second convex pillar 65 can be as follows:

[0118] First, if Fig.10 b and Fig.14b, the dielectric column 82 is removed to form the blind hole 64 on the second plastic package 62' to expose the first convex column 80. Specifically, in this embodiment, the photoresist column is removed by photolithography, and the blind hole 64 is formed at the corresponding position of the second plastic package 62' to expose the first convex column 80.

[0119] Secondly, if Fig.10 c and Fig.14 As shown in c, the second protrusion 65 is formed on the exposed first protrusion 80 by electroplating copper liquid in the blind hole 64 using an electroplating process, that is, the second protrusion 65 is also a copper column. Among them, since the size of the first protrusion 80 is the same as the size of the dielectric column 82, the size of the blind hole 64 formed after removing the dielectric column 82 is the same as the size of the first protrusion 80, so the size of the second protrusion 65 formed in the blind hole 64 is the same as the size of the first protrusion 80. The second protrusion 65 is connected to the first protrusion 65 to form a plastic package conductive column 66.

[0120] In this embodiment, by pre-forming the first convex column, the depth-to-width ratio of the blind hole is optimized when forming the plastic package body conductive column, so that when the second convex column is formed in the blind hole, the uniformity of the second convex column surface is improved, thereby improving the reliability of the entire plastic package body conductive column, thereby improving the reliability of the entire chip packaging structure. In addition, the first convex column and the second convex column have the same size, and the same electroplating parameters can be used to perform electroplating twice to form the first convex column and the second convex column respectively, simplifying the process flow.

[0121] S160, forming a second interconnection layer electrically connected to the conductive pillars of the plastic package on a surface of the second plastic package away from the redistribution layer to form a second chip module.

[0122] In the first embodiment, if Fig.11 As shown, the specific process of forming the second interconnection layer is as follows:

[0123] First, if Fig.11 As shown in FIG. 1 , a third photoresist layer 68 is formed on the surface of the second plastic package 62' away from the redistribution layer 58. Specifically, the third photoresist layer 68 can be formed on the surface of the second plastic package 62' away from the redistribution layer 58 by spin coating, spray coating, physical vapor deposition (PVD), chemical vapor deposition (CVD) and other processes.

[0124] Secondly, if Fig.11 As shown in FIG. 1 , the third photoresist layer 68 is patterned to form corresponding second openings on the corresponding exposed conductive bumps 50 and the conductive pillars 66 of the plastic package.

[0125] Again, if Fig.11As shown in FIG. 2 b, a second solder joint 72' is formed in the second opening, and the second solder joint 72' is electrically connected to the corresponding conductive bump 50 and the plastic package conductive column 66. Specifically, the solder 70' is electroplated at the second opening by using an electroplating process. Fig.11 As shown in FIG. c, the remaining third photoresist layer 68 is removed by etching or other processes. Fig.11 d, the solder 70' is reflowed to form second solder joints 72' on the conductive bumps 50 and the plastic package conductive pillars 66, respectively, and the second solder joints 72' are electrically connected to the corresponding conductive bumps 50 and the plastic package conductive pillars 66. That is, in the first embodiment, the second interconnection layer is a plurality of second solder joints 72' electrically connected to the conductive bumps 50 and the plastic package conductive pillars 66, respectively. In this embodiment, the second solder joints 72' can be solder balls.

[0126] like Fig.11 As shown in FIG. 5 , in the first embodiment, after forming the second interconnection layer, the temporary carrier 56 and the temporary bonding adhesive layer 54 are removed and inverted to form a second chip module B. That is, the second chip module B includes a second plastic package 62', a plurality of chips 52 wrapped in the second plastic package 62', a plurality of plastic package conductive pillars 66 running through the thickness of the second plastic package 62', a redistribution layer 58 disposed on one surface of the second plastic package 62', and a plurality of second solder joints 72' disposed on the conductive bumps 50 and the plastic package conductive pillars 66 on the other surface of the second plastic package 62'. The second chip module B realizes vertical interconnection with other chip modules through the plurality of second solder joints 72'.

[0127] In the second embodiment, if Fig.15 As shown, the specific process of forming the second interconnection layer is as follows:

[0128] First, a wiring layer is formed on a surface of the second plastic package body away from the redistribution layer, and the wiring layer is electrically connected to the conductive pillars of the plastic package body.

[0129] Specifically, Fig.15 As shown in FIG. 1 , a dielectric layer and an interconnect metal layer are sequentially formed on the back of the chip 52 and the surface of the second plastic package 62 ′ away from the redistribution layer 58 , and wiring is completed to form a wiring layer 71 , which is electrically connected to the conductive pillars 66 of the plastic package.

[0130] Secondly, a plurality of solder balls electrically connected to the wiring layer are formed on the wiring layer, and the wiring layer and the solder balls together constitute the second interconnection layer.

[0131] Specifically, Fig.15 As shown in FIG. 5 b , a plurality of solder balls 73 are formed on the wiring layer 71 by ball planting. The plurality of solder balls 73 are arranged on the interconnection metal layer of the wiring layer 71 and are electrically connected to the wiring layer 71 .

[0132] It should be noted that if Fig.16 As shown, when the second plastic package 62' is thinned so as not to expose the back of the chip 52, a wiring layer 71 and solder balls 73 can be sequentially formed on the surface of the second plastic package 62' away from the redistribution layer 58. That is, in the formed second chip module B, the wiring layer 71 contacts the second plastic package 62' and does not directly contact the back of the chip 52, and the electrical interconnection of the upper and lower stacked chip modules is achieved through the conductive pillars 66 of the plastic package.

[0133] In this embodiment, the second interconnection layer is a wiring layer and a plurality of solder balls formed on the wiring layer, so that the first surface and the second surface of each chip in each second chip module are both circuit layers, providing abundant solder point outputs for each chip to achieve efficient electrical connection.

[0134] like Fig.15 c, after forming the second interconnection layer, the temporary carrier 56 and the temporary bonding adhesive layer 54 are removed and inverted to form a second chip module B. That is, the second chip module B includes a second plastic package 62', a plurality of chips 52 wrapped in the second plastic package 62', a plurality of plastic package conductive pillars 66 running through the thickness of the second plastic package 62', a redistribution layer 58 disposed on the surface of the second plastic package 62' that exposes the conductive bumps 50 on the front side of the chip 52, and a wiring layer 71 disposed on the back side of the second plastic package away from the redistribution layer 58 and the chip 52, and solder balls 73 disposed on the wiring layer 71. The second chip module B is vertically interconnected with other chip modules through the wiring layer 71 and the solder balls 73.

[0135] S170, stacking a plurality of the second chip modules in sequence on the substrate through the second interconnection layer, and stacking the first chip modules to the uppermost second chip module through the first interconnection layer, wherein the plastic package conductive pillars realize vertical interconnection between the chip modules.

[0136] The second interconnection layer of the bottom second chip module B is electrically connected to the substrate 74. The second interconnection layer of the top second chip module B is electrically connected to the redistribution layer 58 of the bottom second chip module B. The first interconnection layer of the first chip module A is electrically connected to the redistribution layer 58 of the top second chip module A.

[0137] like Fig.12As shown in FIG. 1 , in the first embodiment, a plurality of second chip modules B are sequentially stacked on a substrate 74 through first solder joints 72'. That is, a second chip module B is firstly stacked on the substrate 74, and then the other second chip modules B are sequentially stacked on the bottom second chip module B. Among them, the second chip module B in the bottom layer is electrically connected to the substrate 74 through the first solder joints 72'. Among the other plurality of second chip modules B, the second solder joints 72' of the upper second chip module B are electrically connected to the redistribution layer 58 of the lower second chip module B, and at the same time, the second chip modules B are vertically interconnected through the conductive pillars 66 of the plastic package, thereby realizing vertical interconnection between the chips 52 in each second chip module B.

[0138] like Fig.12 As shown in FIG. 2 , in the first embodiment, after a plurality of second chip modules B are stacked in sequence on a substrate 74, the first chip module A is stacked on the redistribution layer 58 of the topmost second chip module B through the first solder joint 72 to realize the interconnection between each chip 52 in the first chip module A and each chip 52 in the topmost second chip module B.

[0139] like Fig.12 As shown in FIG. 3 , in the first embodiment, after the first chip module A and multiple second chip modules B are stacked in sequence on a substrate 74, an underfill layer 76 is formed between the first chip module A and the topmost second chip module B, between two adjacent second chip modules B, and between the bottommost second chip module B and the substrate 74. The underfill layer 76 wraps the first solder joint 72 and the second solder joint 72', respectively, to further fix each chip module.

[0140] In the first embodiment, after the bottom filling between the chip modules and between the second chip module B and the substrate 74 is completed, a plurality of interconnection solder balls 78 are formed on the side of the substrate 74 away from the chip modules to form a chip package. The chip package is cut according to the packaging requirements to obtain the following: Fig.12 d shows the chip packaging structure, wherein the packaging structure is electrically connected to the outside world through interconnection solder balls 78.

[0141] refer to Fig.17 As shown in FIG. 17a, in the second embodiment, a plurality of second chip modules B are stacked sequentially on a substrate 74 through a plurality of solder balls 73. Among them, the bottom second chip module B is electrically connected to the substrate 74 through a plurality of solder balls 73. In the other plurality of second chip modules B, a plurality of solder balls 73 of the upper second chip module B are electrically connected to the redistribution layer 58 of the lower second chip module B, and at the same time, each second chip module B is vertically interconnected through the plastic package conductive column 66, thereby realizing vertical interconnection between the chips 52 in each second chip module B.

[0142] like Fig.17 As shown in a, in the second embodiment, after multiple second chip modules B are stacked in sequence on the substrate 74, the first chip module A is stacked on the redistribution layer 58 of the top second chip module B through the first solder joint 72 to achieve interconnection between each chip 52 in the first chip module A and each chip 52 in the top second chip module B.

[0143] like Fig.17 As shown in FIG. 2 , in the second embodiment, after the first chip module A and multiple second chip modules B are stacked in sequence on a substrate 74, an underfill layer 76 is formed between the first chip module A and the topmost second chip module B, between two adjacent second chip modules B, and between the bottommost second chip module B and the substrate 74. The underfill layer 76 respectively wraps the solder balls 73 and the first solder joints 72 to further fix each chip module.

[0144] In the second embodiment, after the bottom filling between the chip modules and between the second chip module B and the substrate 74 is completed, a plurality of interconnection solder balls 78 are formed on the side of the substrate 74 away from the chip modules to form a chip package. The chip package is cut according to the packaging requirements to obtain the following: Fig.17 The chip packaging structure shown in FIG. 3 is a chip packaging structure in which the packaging structure is electrically connected to the outside world through interconnection solder balls 78.

[0145] In the multi-layer stacked chip packaging method of the disclosed embodiment, multiple chips can be arranged in each first chip module and the second chip module, which significantly improves the storage capacity of the chip packaging structure, reduces the number of stacking layers, and improves the stability of the entire chip packaging structure; the chip modules are vertically interconnected by plastic-encapsulated conductive columns with larger diameters, and the plastic-encapsulated conductive columns can be better aligned with the redistribution layer and the pads of the substrate, significantly reducing the alignment accuracy requirements and improving the stability of the chip packaging structure. By pre-forming the first convex column, the depth-to-width ratio of the blind hole is optimized when the plastic-encapsulated conductive column is formed, so that when the second convex column is formed in the blind hole, the uniformity of the second convex column surface is improved, thereby improving the reliability of the entire plastic-encapsulated conductive column, thereby improving the reliability of the entire chip packaging structure.

[0146] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A multi-layer stacked chip packaging method, characterized in that: The method comprises: Forming a plurality of chips, wherein a conductive bump is formed on a first surface of each of the chips; forming a first plastic package body encapsulating the plurality of chips, and forming a first interconnection layer on the conductive bumps exposed by the first plastic package body to form a first chip module; forming a redistribution layer, forming a first convex column on the redistribution layer, and forming a dielectric column on the first convex column; Fixing a plurality of the chips to the redistribution layer, and forming a second plastic package on the redistribution layer to respectively encapsulate the chips, the first convex pillars and the dielectric pillars; The dielectric column is removed to form a blind hole, and a second convex column is formed in the blind hole, wherein the second convex column is connected to the first convex column to form a plastic package conductive column; Forming a second interconnection layer electrically connected to the conductive pillars of the plastic package on a surface of the second plastic package away from the redistribution layer to form a second chip module; Multiple second chip modules are stacked in sequence on the substrate through the second interconnection layer, and the first chip modules are stacked to the uppermost second chip module through the first interconnection layer, wherein the plastic package conductive pillars realize vertical interconnection between the chip modules.

2. The method according to claim 1, characterized in that: The method comprises: stacking a plurality of the second chip modules in sequence on a substrate through the second interconnection layer, and stacking the first chip modules to the uppermost second chip module through the first interconnection layer, comprising: The second interconnection layer of the second chip module at the bottom is electrically connected to the substrate; The second interconnect layer of the second chip module at the upper layer is electrically connected to the redistribution layer of the second chip module at the lower layer; The first interconnect layer of the first chip module is electrically connected to the redistribution layer of the uppermost second chip module.

3. The method according to claim 1, characterized in that The step of forming a first convex column on the redistribution layer comprises: forming a first photoresist layer on the redistribution layer; sequentially exposing and developing the first photoresist layer to form a first opening on the first photoresist layer; The first protrusion is formed in the first opening by an electroplating process.

4. The method according to any one of claims 1 to 3, characterized in that: The step of forming a dielectric column on the first convex column comprises: forming a second photoresist layer on the redistribution layer to wrap the first convex pillar; The second photoresist layer is sequentially exposed and developed to form the dielectric pillar on the first convex pillar; wherein, The size of the dielectric pillar is the same as that of the first convex pillar.

5. The method according to any one of claims 1 to 3, characterized in that: The step of removing the dielectric pillar to form a blind hole and forming a second convex pillar in the blind hole comprises: Removing the dielectric column to form the blind hole on the second plastic package body to expose the first convex column; The second convex column is formed on the first convex column exposed in the blind hole by using an electroplating process; wherein, The size of the first protrusion is the same as the size of the second protrusion.

6. The method according to any one of claims 1 to 3, characterized in that: The step of fixing the plurality of chips to the redistribution layer comprises: Fixing the second surfaces of the plurality of chips to the redistribution layer; The forming of the second plastic package body comprises: forming the second plastic package body on the redistribution layer; The side of the second plastic package body facing away from the redistribution layer is thinned to expose the conductive bumps and the dielectric pillars on the first surface of the chip.

7. The method according to claim 6, characterized in that A second interconnect layer electrically connected to the conductive pillars of the plastic package is formed on a surface of the second plastic package away from the redistribution layer, comprising: forming a third photoresist layer on a surface of the second plastic package body away from the redistribution layer; Patterning the third photoresist layer to form corresponding second openings on the corresponding exposed conductive bumps and conductive columns of the plastic package body; A second soldering point is formed in the second opening, and the second soldering point is electrically connected to the corresponding conductive bump and the conductive column of the plastic package body respectively.

8. The method according to any one of claims 1 to 3, characterized in that: The step of fixing the plurality of chips to the redistribution layer further comprises: Fixing the first surfaces of the plurality of chips to the redistribution layer, wherein the conductive bumps are electrically connected to the redistribution layer; The forming of the second plastic package body further includes: forming the second plastic package body on the redistribution layer; The side of the second plastic package body facing away from the redistribution layer is thinned to expose the dielectric column.

9. The method according to claim 8, characterized in that The second interconnection layer electrically connected to the conductive pillar of the plastic package body is formed on the surface of the second plastic package body away from the redistribution layer, and further includes: Forming a wiring layer on a surface of the second plastic package body away from the redistribution layer, wherein the wiring layer is electrically connected to the conductive pillars of the plastic package body; A plurality of solder balls electrically connected to the wiring layer are formed on the wiring layer, and the wiring layer and the solder balls together constitute the second interconnection layer.

10. The method according to any one of claims 1 to 3, characterized in that: After stacking a plurality of the second chip modules in sequence on the substrate through the second interconnect layer, and stacking the first chip modules to the uppermost second chip module through the first interconnect layer, the method further includes: An underfill layer is formed between the first chip module and the uppermost second chip module, between two adjacent second chip modules, and between the lowermost second chip module and the substrate.

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