Enhanced gallium oxide CAVET device

Abstract

The invention belongs to the technical field of power semiconductors, and relates to an enhanced gallium oxide CAVET device. When the external voltage of the grid electrode is zero, the current blocking layer enables the device to be in a turn-off state; along with the increase of the gate voltage, an electron accumulation layer is formed on the surface of the current blocking layer below the gate insulating medium, the N + source region and the current path region are communicated, and the device enters a forward conduction state. Therefore, during forward conduction, the current barrier layer reduces the electron concentration on the surface of the drift region to realize positive threshold voltage, and the high electron concentration in the current path region enhances the forward current capability and reduces the conduction resistance. In a voltage-withstanding state, reverse bias voltage is applied to the device, at the moment, the N-type gallium oxide drift region and the thermal oxidation region are used up and bear voltage, high-low junction optimization electric field distribution is formed between the N-type gallium oxide drift region and the thermal oxidation region with low carrier concentration after thermal oxidation, and meanwhile, the current blocking layer enhances the effect of suppressing leakage current above the thermal oxidation region, so that the reliability of the device is improved. The two improve the withstand voltage of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology and relates to an enhanced gallium oxide CAVET device. Background Technology

[0002] In recent years, β-phase Ga2O3 (β-Ga2O3) has become a popular new material for high-performance power electronic devices due to its unique material properties and high crystal quality. As an ultra-wide bandgap E... g =4.5-4.9 eV semiconductor material, β-Ga₂O₃ has a breakdown electric field of 8 MV / cm. The Baliga figure of merit of β-Ga₂O₃ devices is 4 times that of GaN, 10 times that of SiC, and 3444 times that of Si, theoretically offering higher operating temperatures, higher power, lower losses, smaller size, and stronger radiation resistance. Compared to the high-cost production methods of SiC / GaN materials, β-Ga₂O₃ can be grown into high-quality, large-size single crystals using various lower-cost melt methods. Therefore, gallium oxide is expected to become a preferred material for high-voltage, high-power, low-loss power devices, meeting the demands of high power density, high conversion efficiency, and small, lightweight power systems, and has broad application prospects.

[0003] In recent years, both lateral and longitudinal devices based on β-Ga₂O₃ have reported excellent performance parameters. However, in terms of fully utilizing the two major advantages of β-Ga₂O₃ material, longitudinal devices offer a better electric field distribution. Furthermore, by utilizing a highly doped, low-resistivity β-Ga₂O₃ self-supporting substrate, extremely high breakdown voltage and low on-resistance can be achieved. However, effective p-type doping of gallium oxide has not yet been achieved, making it difficult to achieve enhancement-mode devices with positive threshold voltages in gallium oxide-based power field-effect transistors, significantly limiting the development of β-Ga₂O₃ longitudinal field-effect transistors. In recent years, some researchers have successfully fabricated longitudinal field-effect transistors (CAVETs) with current aperture structures by using N-ion implantation to form a high-resistivity layer (CBL) in the β-Ga₂O₃ drift layer to impede electron transport.

[0004] Currently, a common method to reduce the on-resistance of β-Ga2O3 CAVET devices is to increase the carrier concentration in the channel layer. However, due to the limited depletion capability of the gate, the channel layer electrons cannot be depleted, resulting in a depletion-mode device that cannot achieve enhancement mode. To achieve enhancement mode, the channel layer electron concentration must be reduced, which in turn increases the on-resistance and affects the power figure of merit (PFOM) value. Moreover, due to the limitation of the gate metal's depletion capability, even if enhancement mode is achieved by reducing the channel layer electron concentration, the threshold voltage of the device will be very low, leading to an increased false turn-on rate. In addition, the CBL layer of current β-Ga2O3 CAVET devices is difficult to suppress leakage current, resulting in an excessively low breakdown voltage. Summary of the Invention

[0005] To address the above problems, this invention proposes an enhanced gallium oxide CAVET device.

[0006] The technical solution of this invention is as follows:

[0007] An enhanced gallium oxide CAVET device includes a drain electrode 1, an N-type gallium oxide drain region 2, and an N-type gallium oxide drift region 3, which are stacked sequentially from bottom to top along the vertical direction of the device.

[0008] The N-type gallium oxide drift region 3 is characterized in that its upper surface has a thermally oxidized region 4, and the upper ends of the thermally oxidized region 4 have symmetrical source structures. A current path region 6 is formed between the source structures. The source structure includes a current blocking layer 5, an N+ source region 7, and a second conductive material 10. The current blocking layer 5 is in contact with the current path region 6, and the junction depth of the current blocking layer 5 is greater than the junction depth of the current path region 6. The N+ source region 7 is located at the end of the upper layer of the current blocking layer 5 away from the current path region 6, and the second conductive material 10 is located at the end of the upper layer of the N+ source region 7 away from the current path region 6, with the lower end of the second conductive material 10 embedded in the N+ source region 7. The upper surface of the current path region 6 has an insulating medium 8, and both ends of the insulating medium 8 extend to contact the upper surface of the N+ source region 7. The upper surface of the insulating medium 8 has a first conductive material 9, and the first conductive material 9 and the upper surface of the insulating medium 8 completely overlap. The first conductive material 9 is led out as a gate electrode, and the second conductive material 10 is led out as a source electrode.

[0009] Furthermore, the bottom of the current path region 6 extends downward along the vertical direction of the device beyond the two side current blocking layers 5 and contacts the N-type gallium oxide drift region 3.

[0010] The beneficial effects of this invention are as follows: by using a global surface thermal oxidation process to form a thermal oxide layer to reduce the carrier concentration on the surface of the gallium oxide drift region, the electric field distribution of the CAVET device under breakdown voltage is optimized. Then, by using reverse doping ion implantation technology to form a current blocking layer, the threshold voltage can be adjusted to achieve enhancement mode while enhancing the effect of suppressing leakage current. Afterwards, ion implantation is performed again in the current path region to increase the carrier concentration in this region and achieve low on-resistance. The gallium oxide CAVET device of this invention has the effects of high threshold voltage, high breakdown voltage, low leakage current and low on-state voltage drop. Attached Figure Description

[0011] Figure 1 This is a cross-sectional structural diagram of Embodiment 1 of the present invention;

[0012] Figure 2 This is a cross-sectional structural diagram of Embodiment 2 of the present invention; Detailed Implementation

[0013] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0014] Example 1:

[0015] like Figure 1 As shown, this example includes a drain electrode 1, an N-type gallium oxide drain region 2 located on the upper surface of the drain electrode 1, and an N-type gallium oxide drift region 3 located on the upper surface of the N-type gallium oxide drain region 2, stacked sequentially from bottom to top along the vertical direction of the device. The N-type gallium oxide drift region 3 is characterized by having a thermal oxidation region 4 on its upper surface and a current blocking layer 5, a current path region 6, and another current blocking layer 5 arranged sequentially along the lateral direction of the device on the upper surface of the thermal oxidation region 4. An N+ source region 7 is located on the upper layer of the current blocking layer 5, and the N+ source region 7 and the current path region 6 are separated by the current blocking layer 5. Isolation; the insulating medium 8 completely covers the upper surface of the current blocking layer 5 and the current path region 6, and also covers a portion of the upper surface of the N+ source region 7 near the current path region 6; the upper surface of the insulating medium 8 has a first conductive material 9, and the first conductive material 9 and the upper surface of the insulating medium 8 completely overlap; the second conductive material 10 is located on the upper surface of the N+ source region 7 away from the current blocking layer 6, and the second conductive material 10 and the first conductive material 9 do not contact each other; the first conductive material 9 is led out as a gate electrode, and the second conductive material 10 is led out as a source electrode.

[0016] The working principle of this example is as follows:

[0017] This invention proposes an enhanced gallium oxide (GaO) CAVET device. When the applied voltage to the gate electrode 9 is zero, the current blocking layer 5 keeps the device in the off state. As the gate voltage increases, an electron accumulation layer forms on the surface of the current blocking layer 5 beneath the gate insulating dielectric, creating an electron channel that connects the N+ source region 7 and the current path region 6, allowing the device to enter the forward conduction state. Therefore, during forward conduction, the high electron concentration in the current path region enhances the forward current capability and reduces the on-resistance. The current blocking layer reduces the electron concentration on the surface of the drift region to achieve a positive threshold voltage. When a reverse bias voltage is applied, the device is in a breakdown state. At this time, the N-type GaO drift region 3 and the thermally oxidized region 4 are depleted and bear the voltage. The N-type GaO drift region 3 and the thermally oxidized region 4, which has a low carrier concentration after thermal oxidation, form a high-low junction, optimizing the electric field distribution and improving the breakdown voltage. In addition, the current blocking layer 5 above the thermally oxidized region 4 enhances the suppression of leakage current. Therefore, the GaO CAVET device of this invention has the advantages of high threshold voltage, high breakdown voltage, low on-state voltage drop, and low leakage current.

[0018] Example 2:

[0019] like Figure 2As shown, the difference between this embodiment and embodiment 1 is that the bottom of the current path region 6 extends downward beyond the current blocking layers 5 on both sides along the vertical direction of the device. Compared with embodiment 1, when the device is in forward conduction, the high-concentration current path region 6 is directly connected to the N-type gallium oxide drift region 3, thereby reducing the on-resistance.

Claims

1. An enhanced gallium oxide CAVET device, comprising a drain electrode (1), an N-type gallium oxide drain region (2), and an N-type gallium oxide drift region (3) which are stacked in sequence from bottom to top along the vertical direction of the device; It is characterized in that The upper surface of the N-type gallium oxide drift region (3) has a thermal oxidation region (4), the upper two ends of the thermal oxidation region (4) have symmetrical source structures, between the source structures is a current path region (6), the source structure comprises a current blocking layer (5), an N+ source region (7) and a second conductive material (10), wherein the current blocking layer (5) is in contact with the current path region (6), and the junction depth of the current blocking layer (5) is greater than the junction depth of the current path region (6); the N+ source region (7) is located at one end of the upper layer of the current blocking layer (5) away from the current path region (6), and the second conductive material (10) is located at The upper layer of the N+ source region (7) is away from one end of the current path region (6), and the lower end of the second conductive material (10) is embedded in the N+ source region (7); the upper surface of the current path region (6) has an insulating medium (8), and the two ends of the insulating medium (8) are respectively extended to contact the upper surface of the N+ source region (7); the upper surface of the insulating medium (8) has a first conductive material (9), and the first conductive material (9) and the upper surface of the insulating medium (8) completely overlap; the first conductive material (9) is led out as a gate electrode, and the second conductive material (10) is led out as a source electrode.

2. An enhanced-mode gallium oxide CAVET device according to claim 1, characterized in that: The bottom of the current path region (6) extends downward along the vertical direction of the device until it contacts the N-type gallium oxide drift region (3).

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