Preparation method of tunneling oxide layer and solar cell

Abstract

The invention provides a preparation method of a tunneling oxide layer, and a solar cell. The preparation method comprises the following steps: pre-sintering a semiconductor substrate under an oxygen-free condition and within a first preset temperature range for a first preset time; the pre-sintered semiconductor substrate is cooled at the room temperature; and preparing a tunneling oxide layer on the cooled semiconductor substrate. According to the preparation method, the crystal structure and the grain size distribution in the semiconductor substrate material can be more uniform, and defects and impurities on the surface of the semiconductor substrate are eliminated, so that the surface state, the surface potential and the like of the semiconductor substrate tend to be consistent. Furthermore, the ordered growth of crystals can be better promoted in the growth process of the tunneling oxide layer, the non-uniformity of the grain size is reduced, and the more uniform tunneling oxide layer is obtained.

Description

Technical Field

[0001] The present application belongs to the technical field of solar cells, and in particular, relates to a method for preparing a tunneling oxide layer and a solar cell. Background Art

[0002] Tunnel Oxide Layer (TOL) is an ultra-thin silicon dioxide (SiO2) film with a thickness usually in the range of several nanometers. Its working principle is based on the tunneling effect in quantum mechanics. In semiconductor devices, when electrons or holes encounter a sufficiently thin insulating layer, they may still pass through this barrier through the tunneling mechanism, even though their energy is lower than the band gap of the insulating layer. In the tunneling oxide layer, although it is insulating for most carriers, minority carriers with appropriate energy and momentum, especially thermally excited carriers, can tunnel through the oxide layer to the other side.

[0003] With the continuous advancement of photovoltaic technology, various high-efficiency batteries are being continuously developed. Both TOPCON batteries and BC batteries are seeking better passivation structures to improve the performance of the battery itself. The passivation contact structure formed by superimposing a layer of phosphorus-doped or boron-doped polysilicon on an ultra-thin tunneling oxide layer is considered to be the most effective structure to improve passivation and contact performance. It has been widely used in TOPCON batteries. The tunneling oxide layer allows minority carriers to tunnel into the polysilicon layer to achieve effective charge collection, while preventing the reverse diffusion of majority carriers, thereby improving the open circuit voltage and fill factor of the device; the tunneling oxide layer can significantly reduce the number of surface states and interface states, which are usually the source of carrier recombination and charge loss. By forming a high-quality tunneling oxide layer, the recombination rate of the surface and interface can be significantly reduced, and the photoelectric conversion efficiency of the device can be improved, achieving considerable results.

[0004] The quality of the tunneling oxide layer is directly related to the performance of the passivation contact structure. The tunneling oxide layer requires extremely high thickness and precise control. A too thick tunneling oxide layer will increase the charge transfer resistance and reduce the tunneling efficiency. A too thin tunneling oxide layer may not be able to effectively isolate the charge, resulting in increased leakage current and decreased device performance. The tunneling oxide layer currently formed generally has the phenomenon of unevenness within the cell. When the unevenness is high, it will affect the overall passivation contact effect of the cell. Summary of the invention

[0005] In view of the problems existing in the prior art, the present application provides a method for preparing a uniform tunneling oxide layer and a solar cell.

[0006] Specifically, this application involves the following aspects:

[0007] A method for preparing a tunneling oxide layer comprises the following steps:

[0008] Pre-sintering the semiconductor substrate in an oxygen-free condition and within a first preset temperature range for a first preset time;

[0009] Cooling the pre-sintered semiconductor substrate at room temperature;

[0010] A tunnel oxide layer is formed on the cooled semiconductor substrate.

[0011] Optionally, pre-sintering the semiconductor substrate in an oxygen-free condition and within a first preset temperature range for a first preset time includes: pre-sintering the semiconductor substrate in an oxygen-free condition and within a first preset temperature range at a constant temperature for a first preset time.

[0012] Optionally, the first preset temperature range is 400° C.-600° C., and the first preset time is 3 min-5 min.

[0013] Optionally, the cooling temperature is 20°C-30°C, and the cooling time is 3min-10min.

[0014] Optionally, the pre-sintering and the preparation of the tunnel oxide layer are performed in the same furnace tube.

[0015] Optionally, the pre-sintering and the preparing the tunnel oxide layer are performed in different furnace tubes.

[0016] Optionally, the method for preparing the tunnel oxide layer is selected from thermal oxidation, chemical vapor deposition, atomic layer deposition, and wet oxidation.

[0017] Optionally, the step of preparing the tunnel oxide layer comprises the following steps:

[0018] placing the cooled semiconductor substrate into a furnace tube, evacuating the furnace tube and purging the furnace tube with nitrogen;

[0019] introducing oxygen within a second preset temperature range, a second preset time, and a preset pressure;

[0020] The oxygen inlet valve is closed, and the semiconductor substrate is kept in the furnace tube for a third preset time to prepare a tunneling oxide layer on the semiconductor substrate.

[0021] Optionally, the second preset temperature range is 560°C-650°C, the second preset time is 5min-20min, the flow rate of the oxygen is 5000-50000sccm, the preset pressure is normal pressure, and the third preset time is 10min-30min.

[0022] A solar cell comprises a silicon substrate and a tunneling oxide layer arranged on the silicon substrate, wherein the intra-chip uniformity of the tunneling oxide layer is 2% to 6%; wherein the intra-chip uniformity = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / (maximum thickness of the tunneling oxide layer + minimum thickness of the tunneling oxide layer) * 100%.

[0023] Optionally, tunneling oxide layers are formed on both sides of the silicon substrate, wherein the in-chip uniformity of the tunneling oxide layers on both sides is 2% to 6%; wherein the in-chip uniformity of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / (maximum thickness of the tunneling oxide layer + minimum thickness of the tunneling oxide layer) * 100%.

[0024] The present application does not limit the type of solar cells. Those skilled in the art will understand that the tunneling oxide layer can be located on one side of the silicon substrate. Of course, the tunneling oxide layer can be located on part of the surface or the entire surface of one side of the silicon substrate. For example, it is a back contact cell, that is, at least one region of the P region or the N region of the cell has a tunneling oxide layer, or it is a hybrid back contact cell, one region of the silicon substrate has a tunneling oxide layer, and the other region is a heterojunction structure; if it is a TBC cell, then both the P region or the N region of the cell have a tunneling oxide layer.

[0025] Of course, the tunneling oxide layer can be located on both sides of the silicon substrate. In this case, the tunneling oxide layer can be located on part or all of the surfaces on both sides of the silicon substrate. For example, for a double-sided solar cell, part or all of the surfaces on both sides can have a tunneling oxide layer.

[0026] It can be understood that in the present application, for a solar cell with a tunnel oxide layer having good thickness uniformity within the chip, the whole-surface passivation effect is improved, and it is also beneficial to control the uniformity of the distribution of doping elements on the whole surface.

[0027] Optionally, the maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to a corner of the silicon substrate, and a thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0028] Optionally, the maximum thickness of the tunneling oxide layer on both sides of the silicon substrate occurs at a position corresponding to a corner of the silicon substrate, and a thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0029] Optionally, the maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to the periphery of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0030] Optionally, the maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to the periphery of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0031] Optionally, the maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at positions corresponding to corners and peripheries of the silicon substrate, and a thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0032] Optionally, the maximum thickness of the tunneling oxide layer on both sides of the silicon substrate occurs at a position corresponding to the periphery of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0033] It can be understood that a solar cell in which the thickness of the tunneling oxide layer at the corner of the silicon substrate is greater than the thickness of the tunneling oxide layer at the center of the silicon substrate can improve the passivation and carrier transfer effects at the edge of the cell, reduce the passivation and contact differences inside the cell, and is beneficial to mass production.

[0034] Similarly, a solar cell in which the thickness of the tunneling oxide layer at the periphery of the silicon substrate is greater than the thickness of the tunneling oxide layer at the center of the silicon substrate can improve the passivation and carrier transport effects at the edge of the cell, reduce the passivation and contact differences inside the cell, and is beneficial to mass production.

[0035] Optionally, for the tunneling oxide layer on one side of the silicon substrate, the thickness of the tunneling oxide layer at a corner position corresponding to the silicon substrate is greater than the thickness of the tunneling oxide layer at a peripheral position corresponding to the silicon substrate.

[0036] Optionally, for the tunneling oxide layers on both sides of the silicon substrate, the thickness of the tunneling oxide layer at the corner position corresponding to the silicon substrate is greater than the thickness of the tunneling oxide layer at the periphery position corresponding to the silicon substrate.

[0037] Understandably, the edges of the cell, especially the corners, are more likely to have structural defects such as tiny holes. The more defects there are, the more likely they are to cause carrier capture, reduce filling, and increase recombination and contact resistance. Therefore, if the maximum thickness occurs at the position corresponding to the corner of the silicon substrate, a solar cell with such a tunneling oxide layer can specifically solve the recombination and contact problems at the edge of the cell, which is beneficial to improving the efficiency of the cell.

[0038] In addition, due to the surface tension of the droplets, the edges of the cell are more likely to carry etching droplets, which will cause over-etching at the edges of the cell and damage the silicon substrate. For cells whose maximum thickness of the tunneling oxide layer appears at the corners, the acid and alkali corrosion resistance of the cell corners can be further effectively improved, the edge silicon substrate can be protected, and the generation of defective cells at the corners can be reduced, which is beneficial to improving cell efficiency and yield.

[0039] The present application also relates to a solar cell assembly, which comprises the solar cell described in the present application.

[0040] Optionally, the inter-sheet uniformity of the tunneling oxide layer of each of any two solar cells is 0% to 20%; wherein, the inter-sheet uniformity of any two tunneling oxide layers = (the maximum thickness value appearing on any two tunneling oxide layers - the minimum thickness value appearing on any two tunneling oxide layers) / (the maximum thickness value of the tunneling oxide layer appearing on any two tunneling oxide layers + the minimum thickness value of the tunneling oxide layer appearing on any two tunneling oxide layers) * 100%.

[0041] It can be understood that for a battery module, if each solar cell of the battery module is a battery with a tunneling oxide layer with good thickness uniformity between cells, the battery passivation effect is improved in mass production, and it is also beneficial to improve the uniformity of the doping element distribution on the back of the battery in mass production.

[0042] The preparation method of the present application adopts a two-step method to prepare the tunneling oxide layer, first pre-sintering and cooling the semiconductor substrate, and then preparing the tunneling oxide layer. Through the pre-sintering and cooling process, the crystal structure and grain size distribution inside the semiconductor substrate material can be made more uniform, and the defects and impurities on the surface of the semiconductor substrate can be eliminated, so that the surface state, surface potential, etc. of the semiconductor substrate tend to be consistent. In this way, the tunneling oxide layer can better promote the orderly growth of crystals during the growth process, reduce the non-uniformity of the grain size, and obtain a more uniform tunneling oxide layer.

[0043] As described above, the solar cell of the present application has an improved passivation effect on the entire surface, and is also conducive to controlling the uniformity of doping element distribution on the entire surface. In addition, in some cases, the passivation and carrier transport effects at the edge of the cell can be improved, and the passivation and contact differences within the cell can be reduced, which is beneficial to mass production.

[0044] As described above, the solar cell group of the present application has an improved cell passivation effect in mass production and is also beneficial to improving the uniformity of doping element distribution on the back of the cell in mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is an exemplary flow chart of the preparation method of the present application;

[0046] Figure 2 Shows the average thickness of each tunnel oxide layer obtained in the examples and comparative examples of the present application;

[0047] Figure 3 The uniformity of each tunnel oxide layer obtained in the examples and comparative examples of the present application is shown;

[0048] Figure 4 Schematic showing a back-contact cell with a tunneling oxide layer;

[0049] Figure 5 Thermal map and thickness data showing the thickness of the tunnel oxide layer on a silicon substrate prepared in Example 1.

[0050] Reference numerals

[0051] 1: front pyramid structure with passivation layer, 2: silicon substrate, 3: tunneling oxide layer, 4: P-type or N-type doped polycrystalline conductive layer, 5: N-type or P-type doped polycrystalline conductive layer. DETAILED DESCRIPTION

[0052] The present application is further described below in conjunction with examples. It should be understood that the examples are only used to further describe and illustrate the present application and are not used to limit the present application.

[0053] Unless otherwise defined, the technical and scientific terms in this specification have the same meaning as those generally understood by those skilled in the art. Although similar or identical methods and materials as described herein may be used in experiments or practical applications, materials and methods are described herein below. In the event of a conflict, the present specification including the definitions therein shall prevail. In addition, materials, methods and examples are provided for illustration only and are not restrictive. The present application is further described below in conjunction with specific embodiments, but is not intended to limit the scope of the present application.

[0054] As described above, the tunneling oxide layer prepared by the existing method has the problem of unevenness, which in turn affects the passivation contact effect of the solar cell.

[0055] In view of the problems existing in the prior art, the present application provides a method for preparing a uniform tunneling oxide layer, comprising the following steps:

[0056] Step S1: pre-sintering the semiconductor substrate in an oxygen-free condition and within a first preset temperature range for a first preset time.

[0057] Step S2: Cooling the pre-sintered semiconductor substrate at room temperature.

[0058] Step S3: preparing a tunneling oxide layer on the cooled semiconductor substrate.

[0059] In the present application, the semiconductor substrate may be a silicon wafer, germanium (Ge), or gallium arsenide (GaAs), etc. The silicon wafer may be of N-type or P-type.

[0060] In step S1, the semiconductor substrate is pre-sintered under oxygen-free conditions without generating a tunnel oxide layer, wherein the oxygen-free conditions can be achieved by methods known in the art, for example, the semiconductor substrate can be placed in a vacuum furnace tube.

[0061] In some examples, step S1 may include:

[0062] The semiconductor substrate is pre-sintered in an oxygen-free condition and maintained at a constant temperature within a first preset temperature range for a first preset time.

[0063] Those skilled in the art will appreciate that the pre-sintering may also be performed within the first preset temperature range by using a varying temperature, such as a gradually increasing temperature, and maintaining the first preset time.

[0064] In a specific embodiment, the first preset temperature range is 400-600°C, for example, it can be 400°C, 410°C, 420°C, 430°C, 440°C, 450°C, 460°C, 470°C, 480°C, 490°C, 500°C, 510°C, 520°C, 530°C, 550°C, 550°C, 560°C, 570°C, 580°C, 590°C, 600°C, and any values ​​therebetween; the first preset time is 3-5min, for example, it can be 3min, 3.5min, 4min, 4.5min, 5min, and any values ​​therebetween.

[0065] Among them, the pre-sintering temperature higher than 600°C or lower than 400°C is not conducive to the adjustment of the surface state of the semiconductor substrate. The pre-sintering time less than 3 minutes cannot achieve the effect of pre-sintering, and more than 5 minutes will affect the production process time and reduce production capacity. Those skilled in the art can understand that the first preset temperature and the first preset time are a whole, and the effect of pre-sintering can only be achieved when the first preset temperature and the first preset time are met at the same time.

[0066] Those skilled in the art will appreciate that the pre-sintering device may be the same as or different from the device for preparing the tunnel oxide layer, as long as the sintering of the semiconductor substrate can be achieved. For example, the pre-sintering and the preparation of the tunnel oxide layer may be performed in the same furnace tube, such as a furnace tube of LPCVD (Low Pressure Chemical Vapor Deposition), which can simplify the equipment. The pre-sintering and the preparation of the tunnel oxide layer may be performed in different furnace tubes, such as different LPCVD furnace tubes, which can improve efficiency.

[0067] In step S2 , the pre-sintered semiconductor substrate is cooled at room temperature.

[0068] In a specific embodiment, the room temperature is 20-30°C, for example, it can be 20°C, 21°C, 22°C, 23°C, 24°C, 25°C, 26°C, 27°C, 28°C, 29°C, 30°C, and any value therebetween.

[0069] In a specific embodiment, the cooling time is 3-10 min, for example, it can be 3 min, 3.5 min, 4 min, 4.5 min, 5 min, 5.5 min, 6 min, 6.5 min, 7 min, 7.5 min, 8 min, 8.5 min, 9 min, 9.5 min, 10 min, and any value between these values.

[0070] The cooling time is controlled to be 3-10 minutes. If the time is too short, the semiconductor substrate cannot be effectively cooled. If the cooling time is too long, the semiconductor substrate will begin to grow a tunnel oxide layer in the air, and its thickness is difficult to control.

[0071] Through the pre-sintering and cooling process, the crystal structure and grain size distribution inside the semiconductor substrate material can be made more uniform, and the defects and impurities on the surface of the semiconductor substrate can be eliminated, so that the surface state and surface potential of the semiconductor substrate tend to be consistent. Furthermore, in step S3, the tunneling oxide layer can better promote the orderly growth of crystals during the growth process, reduce the non-uniformity of the grain size, and obtain a more uniform tunneling oxide layer.

[0072] The uniformity of the tunnel oxide layer can be detected by testing the intra-chip uniformity of the tunnel oxide layer.

[0073] Specifically, for a silicon substrate having a tunneling oxide layer formed thereon, multiple points can be taken at random on the semiconductor substrate to test the thickness of the tunneling oxide layer, and then the intra-chip uniformity of the tunneling oxide layer can be calculated based on the measured thickness. For example, five points corresponding to the four corner positions and the center position of the semiconductor substrate can be taken to measure the thickness of the tunneling oxide layer respectively. The thickness can be measured by equipment known in the art, such as an ellipsometer (for example, for a case where a tunneling oxide layer has been formed on a silicon wafer but other structures have not yet been formed, or for a case where other layer structures have been formed and other structures on the tunneling oxide layer are removed to expose the tunneling oxide layer), or a TEM can be used to test the cross section of the cell (for example, for a case where a tunneling oxide layer has been formed on a silicon wafer but other structures have not yet been formed, or for a case where other layer structures have been formed, or a complete solar cell). In-chip uniformity of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / (maximum thickness of the tunneling oxide layer + minimum thickness of the tunneling oxide layer) * 100%.

[0074] Furthermore, in the present application, the maximum value of the thickness of the tunnel oxide layer on a silicon wafer or the minimum value of the thickness of the tunnel oxide layer on a silicon wafer is mentioned. At this time, those skilled in the art should understand that it is necessary to select multiple test points for testing at will, and then select the maximum and minimum values ​​from these test points, for example, at least 5 points, or at least 9 points, or at least 16 points, or at least 25 points, or at least 36 points, or at least 49 points, or at least 64 points, or at least 81 points, or at least 100 points, and when selecting multiple points, the positions of the selected sites should be evenly distributed. Figure 5 As shown, you can follow Figure 5 The method shown selects four corners and the center of the silicon wafer as five sites for detection. Figure 5 The measurement points located at the corners of the solar cell were selected at a distance of 1 cm from the edge of the cell, from which the maximum and minimum values ​​were selected.

[0075] The in-chip uniformity of the tunnel oxide layer obtained by the preparation method of the present application can reach less than 6%.

[0076] In step S3, the tunneling oxide layer may be prepared by any known technique in the art. For example, thermal oxidation, chemical vapor deposition, atomic layer deposition, wet oxidation, etc. may be used. When the tunneling oxide layer is formed by chemical vapor deposition, specifically, the tunneling oxide layer may be formed by low-pressure chemical vapor deposition.

[0077] In a specific embodiment, the tunnel oxide layer is prepared by thermal oxidation.

[0078] Specifically, preparing the tunnel oxide layer includes the following steps:

[0079] S31: placing the cooled semiconductor substrate into a furnace tube, evacuating the furnace tube and purging the furnace tube with nitrogen.

[0080] S32: introducing oxygen within a second preset temperature range, a second preset time and a preset pressure.

[0081] S33: closing the oxygen inlet valve, and keeping the semiconductor substrate in the furnace tube for a third preset time to form a tunneling oxide layer on the semiconductor substrate.

[0082] In step S31, the furnace tube may be a furnace tube in a LPCVD device.

[0083] In step S32, the second preset temperature range may be 560°C-650°C. The second preset time may be 5min-20min. The flow rate of oxygen may be 5000-50000sccm, for example, 5000sccm, 10000sccm, 15000sccm, 20000sccm, 25000sccm, 30000sccm, 35000sccm, 40000sccm, 45000sccm, 50000sccm, and any values ​​therebetween; the time for passing oxygen may be 5-20min, for example, 5min, 6min, 7min, 8min, 9min, 10min, 11min, 12min, 13min, 14min, 15min, 16min, 17min, 18min, 19min, 20min, and any values ​​therebetween.

[0084] If the second preset temperature is too low, the reaction rate will be too slow, and if it is too high, it will be unfavorable for the subsequent preparation of the polysilicon layer. The oxygen flow rate of 5000-50000 sccm can match the furnace tubes of various diameters involved in the prior art.

[0085] In a specific embodiment, the pressure after the oxygen is introduced is normal pressure.

[0086] In step S32, the third preset time is 10min-30min, for example, it can be 10min, 11min, 12min, 13min, 14min, 15min, 16min, 17min, 18min, 19min, 20min, 21min, 22min, 23min, 24min, 25min, 26min, 27min, 28min, 29min, 30min, and any value between these values.

[0087] If the third preset time is too short, the thickness of the prepared tunnel oxide layer will be too thin, while if the third preset time is too long, the thickness of the prepared tunnel oxide layer will be too thick.

[0088] Those skilled in the art can understand that, before step S1, the preparation method of the present application can also include step S0: cleaning and polishing the semiconductor substrate. The surface of the semiconductor substrate after cleaning and polishing can be a velvet surface, such as a pyramid velvet surface, or a polished surface.

[0089] The cleaning or polishing method may be any method known in the art.

[0090] In a specific embodiment, the preparation method of the present application comprises the following steps: Step S1: pre-sintering a silicon wafer under oxygen-free conditions and at a constant temperature within a first preset temperature range for a first preset time, wherein the first preset temperature range is 400°C-600°C, and the first preset time is 3min-5min; Step S2: cooling the pre-sintered silicon wafer at room temperature, wherein the cooling temperature is 20°C-30°C, and the cooling time is 3min-10min; Step S3: preparing a tunneling oxide layer on the cooled silicon wafer.

[0091] In a specific embodiment, the preparation method of the present application comprises the following steps: Step S1: pre-sintering a silicon wafer under oxygen-free conditions and at a constant temperature within a first preset temperature range for a first preset time, wherein the first preset temperature range is 400°C-600°C, and the first preset time is 3min-5min; Step S2: cooling the pre-sintered silicon wafer at room temperature, wherein the cooling temperature is 20°C-30°C, and the cooling time is 3min-10min; Step S31: placing the cooled silicon wafer into a furnace tube, evacuating the furnace tube and purging it with nitrogen; S32: introducing oxygen within a second preset temperature range, a second preset time and a preset pressure; S33: closing the oxygen inlet valve, and keeping the silicon wafer in the furnace tube for a third preset time to prepare a tunneling oxide layer on the silicon wafer.

[0092] In a specific embodiment, the preparation method of the present application comprises the following steps: Step S1: pre-sintering a silicon wafer under oxygen-free conditions and at a first preset temperature range for a first preset time, wherein the first preset temperature range is 400°C-600°C, and the first preset time is 3min-5min; Step S2: cooling the pre-sintered silicon wafer at room temperature, wherein the cooling temperature is 20°C-30°C, and the cooling time is 3min-10min; Step S31: placing the cooled silicon wafer into a furnace tube, The furnace tube is evacuated and purged with nitrogen; S32: oxygen is introduced under a second preset temperature range, a second preset time and a preset pressure; S33: the oxygen inlet valve is closed, and the silicon wafer is kept in the furnace tube for a third preset time to prepare a tunneling oxide layer on the silicon wafer; wherein the second preset temperature range is 560°C-650°C, the second preset time is 5min-20min, the flow rate of the oxygen introduced is 5000-50000sccm, the preset pressure is normal pressure, and the third preset time is 10min-30min.

[0093] The present application also provides a solar cell, comprising a silicon substrate and a tunneling oxide layer disposed on the silicon substrate; wherein the tunneling oxide layer can be formed by any one of the above-mentioned preparation methods.

[0094] The intra-chip uniformity of the tunneling oxide layer of the solar cell provided in the present application is 2% to 6%; wherein, intra-chip uniformity = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / (maximum thickness of the tunneling oxide layer + minimum thickness of the tunneling oxide layer) * 100%.

[0095] For example, the intra-chip uniformity of the tunnel oxide layer of the solar cell may be 2%, 3%, 4%, 5%, 6%, etc.

[0096] It can be understood that the smaller the value of the intra-chip uniformity of the tunnel oxide layer is, the better the intra-chip uniformity of the tunnel oxide layer is.

[0097] Since the intra-chip uniformity of the tunneling oxide layer of the solar cell provided by the present application is 2% to 6%, the intra-chip uniformity of the tunneling oxide layer is good, and thus the passivation contact effect of the solar cell can be improved.

[0098] It should be noted that when detecting the thickness of the tunneling oxide layer of a solar cell, measurement points are selected at different positions of the solar cell, usually at the four corners of the solar cell and the center of the cell. In some cases, points located on the four sides of the solar cell can also be selected. When the side length of the solar cell is L, the measurement points located at the corners and four sides of the solar cell are usually selected from points within the range of L / 5 from the edge of the cell. After measurement, the maximum and minimum values ​​of the tunneling oxide layer are obtained, and the intra-chip uniformity of the tunneling oxide layer is calculated according to the above calculation formula. It should be noted that for some types of batteries, the tunneling oxide layer exists in a local form or in a partitioned form because it has been graphically processed, such as hybrid batteries, TBC batteries, HPBC batteries, etc. Therefore, when taking measurement points, suitable points with a tunneling oxide layer can be selected in a certain area at the four corners, four sides, and the center of the solar cell for measurement. For TBC cells, the intra-chip uniformity of the tunneling oxide layer is usually calculated for the P region and the N region respectively. In this case, the above method can be used for the P region or the N region respectively, because the P region and the N region are uniformly distributed on the solar cell. Therefore, the P region distribution area can be regarded as the above solar cell, and the measurement points on the corners and four sides of the P region distribution area are usually selected from the points within the range of L1 / 5 from the edge of the P region distribution area (the side length of the P region is L1); the N region distribution area can be regarded as the above solar cell, and the measurement points on the corners and four sides of the N region distribution area are usually selected from the points within the range of L2 / 5 from the edge of the N region distribution area (the side length of the N region is L2). It should also be noted that when using an ellipsometer for measurement, since there are doped polysilicon layers and passivation layers, as well as electrodes, on the tunneling oxide layer of the solar cell, the structure on the tunneling oxide layer needs to be removed, and the method for removing other layer structures can be any method conventionally used by technicians in this field, for example, acid solutions such as hydrofluoric acid and hydrochloric acid can be selected; when using TEM, samples are taken at the measuring point to measure the cross-section of the battery for analysis.

[0099] In addition, the solar cell provided in the present application can be various types of solar cells in the art, as long as it has the above-mentioned substrate and tunneling oxide layer. Specifically, for example, the solar cell provided in the present application can be a bifacial solar cell or a back-contact solar cell. When the solar cell is a bifacial solar cell, a tunneling oxide layer and a doped polysilicon layer can be provided on the back of the solar cell; a tunneling oxide layer and a doped polysilicon layer can also be provided on the entire back of the solar cell, and a tunneling oxide layer and a doped polysilicon layer can be provided in a local area of ​​the front of the solar cell, such as a position in contact with an electrode.

[0100] When the solar cell provided in the present application is a back-contact solar cell, the back-contact solar cell can be a hybrid cell, that is, one of the P region and the N region of the back-contact solar cell is a passivation contact structure provided by a tunneling oxide layer and a doped polycrystalline silicon layer stacked, and the other region is a heterojunction contact structure provided by an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked; the back-contact solar cell can also be a TBC cell, that is, both the P region and the N region of the back-contact solar cell are passivation contact structures provided by a tunneling oxide layer and a doped polycrystalline silicon layer stacked; the back-contact solar cell can also be a HPBC cell, that is, one of the P region and the N region of the back-contact solar cell is a passivation contact structure provided by a tunneling oxide layer and a doped polycrystalline silicon layer stacked, and the other region is a PERC structure.

[0101] For different battery types, those skilled in the art can fully understand that the tunneling oxide layer can be located on one side of the silicon substrate or on the other side of the silicon substrate. In this case, only the tunneling oxide layer on at least one side needs to satisfy the above-mentioned in-chip uniformity. Of course, the tunneling oxide layers on both sides can also satisfy the above-mentioned in-chip uniformity.

[0102] In one embodiment, tunneling oxide layers are formed on both sides of the silicon substrate of the present application, wherein the intra-chip uniformity of the tunneling oxide layers on both sides is 2% to 6%. At this time, the intra-chip uniformity of the tunneling oxide layers on both sides can be 2%, 3%, 4%, 5%, 6%, etc. independently. The intra-chip uniformity of the tunneling oxide layers on both sides can be the same or different. At this time, the above-mentioned method of the present application can be used to detect the intra-chip uniformity of the tunneling oxide layers on both sides.

[0103] For TBC cells, at this time, since there are P region and N region on one side of the silicon base, both the P region and the N region are passivation contact structures set up by tunneling oxide layer and doped polysilicon layer stacking, such as Figure 4 As shown, in Figure 4The silicon substrate of the TBC battery shown has two regions on one side, and region 4 and region 5 represent two regions with opposite polarities. In some cases, the tunneling oxide layer of one of the P region and the N region satisfies the above-mentioned intra-chip uniformity. In the most optimized case, when the tunneling oxide layers of the P region and the N region meet the above-mentioned intra-chip uniformity, the battery cell has better performance. At this time, the intra-chip uniformity of the tunneling oxide layers of the two regions of the P region and the N region can be 2%, 3%, 4%, 5%, 6%, etc. independently. The intra-chip uniformity of the tunneling oxide layers of the two regions can be the same or different. At this time, the above-mentioned method of the present application can be used to detect and calculate the intra-chip uniformity of the tunneling oxide layers of the two regions respectively. In a more preferred case, the absolute value of the intra-chip uniformity difference between the P region and the N region is greater than or equal to 0 and less than or equal to 5%, which can be 0, 0.5%, 0.8%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%. In terms of effect, the smaller the absolute value of the difference in the uniformity of the P and N regions, the better, and a more preferred solution is greater than or equal to 0 and less than or equal to 2%. When the intra-chip uniformity of the tunnel oxide layer in the two regions is relatively small, the carriers in the P and N regions can be balanced, the optimal configuration of the PN region can be achieved, and the efficiency of the cell can be improved.

[0104] In one embodiment, a TBC cell, the back contact cell (TBC cell) comprises: a silicon substrate, and a tunneling oxide layer formed on the backlight surface of the silicon substrate, the tunneling oxide layer comprises a plurality of first tunneling oxide layers and a plurality of second tunneling oxide layers, the first tunneling oxide layer and the second tunneling oxide layer extend along a first direction, are alternately arranged along a second direction, the first direction and the second direction intersect, and the back contact cell has a first edge and a second edge arranged oppositely along the first direction, and a third edge and a fourth edge arranged oppositely along the second direction. As described above, the first tunneling oxide layer and the second tunneling oxide layer respectively satisfy an intra-chip uniformity of 2% to 6%, and preferably the absolute value of the intra-chip uniformity difference between the first tunneling oxide layer and the second tunneling oxide layer is greater than or equal to 0 and less than or equal to 5%, which can be 0, 0.5%, 0.8%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%. And in another more preferred embodiment, the thickness of the end of the first tunnel oxide layer adjacent to the first edge and / or the second edge is greater than the thickness of the portion of the first tunnel oxide layer away from the first edge and the second edge along the first direction; and / or, the thickness of the end of the second tunnel oxide layer adjacent to the first edge and / or the second edge is greater than the thickness of the portion of the second tunnel oxide layer away from the first edge and the second edge along the first direction. The thickness of the first tunnel oxide layer adjacent to the third edge and / or the fourth edge is greater than the thickness of the first tunnel oxide layer located in the middle of the cell; and / or, the thickness of the second tunnel oxide layer adjacent to the third edge and / or the fourth edge is greater than the thickness of the second tunnel oxide layer located in the middle of the cell. Such a TBC battery can specifically passivate edge defects, improve edge carrier transport, solve recombination problems and contact problems at the battery edge, and is beneficial to improving battery efficiency.

[0105] In one embodiment, a HPBC battery, the back contact battery (HPBC) comprises: a silicon substrate, and a plurality of tunnel oxide layers formed on the backlight surface of the silicon substrate, the tunnel oxide layers extend along a first direction, are arranged at intervals along a second direction, the first direction and the second direction intersect, the back contact battery has a first edge and a second edge arranged oppositely along the first direction, and a third edge and a fourth edge arranged oppositely along the second direction, as described above, the tunnel oxide layers respectively meet the intra-chip uniformity of 2% to 6%. And in another more preferred embodiment, the thickness of the end of the tunnel oxide layer adjacent to the first edge and / or the second edge is greater than the thickness of the portion of the tunnel oxide layer away from the first edge and the second edge along the first direction. The thickness of the tunnel oxide layer adjacent to the third edge and / or the fourth edge is greater than the thickness of the tunnel oxide layer located in the middle of the battery cell. Such an HPBC battery specifically passivates edge defects, improves edge carrier transport, solves the recombination problem and contact problem at the edge of the battery, and is beneficial to improving battery efficiency.

[0106] In one embodiment, a hybrid cell, the back contact cell (hybrid cell) comprises: a silicon substrate, and a plurality of tunnel oxide layers formed on the backlight surface of the silicon substrate, the tunnel oxide layers extend along a first direction, are arranged at intervals along a second direction, the first direction and the second direction intersect, the back contact cell has a first edge and a second edge arranged oppositely along the first direction, and a third edge and a fourth edge arranged oppositely along the second direction, as described above, the tunnel oxide layers respectively satisfy the intra-chip uniformity of 2% to 6%. And in another more preferred embodiment, the thickness of the end of the tunnel oxide layer adjacent to the first edge and / or the second edge is greater than the thickness of the portion of the tunnel oxide layer away from the first edge and the second edge along the first direction. The thickness of the tunnel oxide layer adjacent to the third edge and / or the fourth edge is greater than the thickness of the tunnel oxide layer located in the middle of the cell. Such a hybrid cell can passivate edge defects in a targeted manner, improve edge carrier transport, solve the recombination problem and contact problem at the edge of the cell, and is beneficial to improving the efficiency of the cell.

[0107] The thickness of the tunnel oxide layer formed on the silicon substrate in the present application can be detected by the above method as described above. Specifically, the cell structure prepared in the embodiment is tested. An exemplary result is as follows: Figure 5 shown. Figure 5 The thickness of the tunnel oxide layer on the silicon substrate is only shown to be appropriate. Figure 5 The silicon wafer is divided into 9 areas, and the thickness of the tunnel oxide layer in the area corresponding to the corner and the center is tested. The numbers represent the thickness of the tunnel oxide layer on the silicon substrate in the area. Figure 5 In the structure shown, the thickest areas occur in the corners, and the within-sheet uniformity is 3.53%.

[0108] In the present application, the above method can be used to determine the thickness of each area by detecting the thickness of the tunneling oxide layer in different areas on the silicon substrate. One point can be selected in each area for detection, or 3 points can be selected on each area and the average value can be used as the thickness of the tunneling oxide layer in the area.

[0109] On the silicon substrate of a specific embodiment of the present application, the applicant divides it into 9 areas. Of course, those skilled in the art can fully understand that based on the different sizes of the silicon wafers used to form the silicon substrate, it can be further divided into 16 areas, 25 areas, etc. In the present application, there is no further limitation on the silicon wafer itself involved in the above-mentioned present application. It can be a silicon wafer (also called a bare silicon wafer) obtained after machining and slicing after the silicon rod is drawn. The silicon substrate in the present application can be a part of the silicon substrate peeled off and recovered from the battery assembly, as long as it can have a certain shape and can be in the form of a sheet, that is, the size of one surface is larger than the size of the surface perpendicular to it, and it is flat or plate-shaped.

[0110] There is no limitation on the size of the silicon substrate of the present application. The silicon substrate can be of any size, such as a silicon substrate after the light absorber is recovered from the battery component and other layer structures are peeled off. In addition, those skilled in the art will understand that when peeling, if some areas are damaged, as long as there are still some areas on which the thickness of the tunnel oxide layer can be detected, it should be understood that it is the silicon substrate described in the present application, and the battery with such a silicon substrate is also a battery that meets the definition of the present application. For example, in a specific embodiment, the length of at least one side of the silicon substrate of the present application (including the silicon substrate after the recovery and peeling of other layer structures) is greater than 156 mm, for example, it can be 158 ± 2 mm, (160 ± 2) mm, (165 ± 2) mm, (170 ± 2) mm, (175 ± 2) mm, (180 ± 2) mm, (185 ± 2) mm, 190 ± 2 mm, (195 ± 2) mm, (200 ± 2) mm, (2 05±2)mm, (210±2)mm, (215±2)mm, (220±2)mm, (225±2)mm, (230±2)mm, (235±2)mm, (240±2)mm, (245±2)mm, (250±2)mm, (255±2)mm, (260±2)mm, (265±2)mm, (270±2)mm, (275±2)mm, and any range between these values. For example, in a specific embodiment, the thickness of the silicon substrate of the present application (including the partial silicon substrate after stripping after recycling and stripping other layer structures) is at least 40 to 170 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm. In a specific manner, the size of the partial silicon substrate after stripping after recycling and stripping other layer structures can be smaller than the above size, as long as the thickness of the tunneling oxide layer in the area on one side can be detected. Based on the size of the area, those skilled in the art can also understand how to calculate the intra-chip uniformity of the area, that is, the maximum value of the thickness of the tunneling oxide layer in the recycled area - the minimum value of the thickness of the tunneling oxide layer in the recycled area) / (the maximum value of the thickness of the tunneling oxide layer in the recycled area + the minimum value of the thickness of the tunneling oxide layer in the recycled area) * 100%. The detection method for the recovered local area can also be carried out by using the above-mentioned ellipsometer, or by testing the cross section of the battery cell through TEM.

[0111] also, Figure 5 The thickness of the tunnel oxide layer is shown only as an example. Figure 5The thickness of the tunnel oxide layer on one side of the silicon substrate is displayed. The number in each area is the thickness of the tunnel oxide layer in that area. If there is a tunnel oxide layer on both sides, each side can meet Figure 5 The displayed pattern and the thickness distribution on both sides can be different.

[0112] Figure 5 The structure shown can be directly used to further deposit other layer structures to prepare the solar cell of the present application, or it can be cut into half to deposit other layer structures to prepare the solar cell of the present application.

[0113] As described above, the TBC battery, HPBC battery and hybrid battery described in the present application can be prepared using the silicon substrate with a tunneling oxide layer of the present application.

[0114] In a solar cell prepared using such a structure, the maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to the corner of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0115] The maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to the corner of the silicon substrate, that is, the maximum thickness of the tunneling oxide layer occurs at the position of the corner of the silicon substrate. Those skilled in the art can understand that the tunneling oxide layer is located on one side of the silicon substrate, so the position where the maximum thickness of the tunneling oxide layer occurs is located at the corner, which means that its projection is at the corner of the silicon substrate, or the thickness of the tunneling oxide layer at the position equivalent to the corner of the silicon substrate is the largest.

[0116] Exemplarily, the thickness difference ratio of the tunnel oxide layer can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29% or 30%.

[0117] As described above, only the situation on one side of the silicon substrate is described. It is fully understood by those skilled in the art that if it appears on both sides of the silicon substrate, then any one or both sides of the two sides satisfy that the maximum thickness of the above-mentioned tunneling oxide layer appears at the position corresponding to the corner of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%. The thickness difference ratio of the tunneling oxide layer can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29% or 30%. In addition, when both sides are satisfied, the thickness difference ratio can be the same or different.

[0118] In another embodiment, the maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to the periphery of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

[0119] The maximum thickness of the tunneling oxide layer on one side of the silicon substrate occurs at a position corresponding to the periphery of the silicon substrate, that is, the maximum thickness of the tunneling oxide layer occurs at a position at the periphery of the silicon substrate. Those skilled in the art can understand that the tunneling oxide layer is located on one side of the silicon substrate, so the location where the maximum thickness of the tunneling oxide layer occurs is located at the periphery, which means that its projection on the periphery of the silicon substrate, or the thickness of the tunneling oxide layer at a position equivalent to the periphery of the silicon substrate is the largest.

[0120] Exemplarily, the thickness difference ratio of the tunnel oxide layer can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29% or 30%.

[0121] As described above, only the situation on one side of the silicon substrate is described. Those skilled in the art can fully understand that if it appears on both sides of the silicon substrate, then any one or both sides of the two sides meet the above-mentioned maximum thickness of the tunneling oxide layer appears at the position corresponding to the periphery of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%. The thickness difference ratio of the tunneling oxide layer can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29% or 30%. In addition, when both sides are satisfied, the thickness difference ratio can be the same or different.

[0122] In one embodiment, a tunneling oxide layer is formed on one side of the silicon substrate, and a thickness of the tunneling oxide layer at a corner position of the silicon substrate is greater than a thickness of the tunneling oxide layer at a peripheral position of the silicon substrate.

[0123] In one embodiment, for the tunneling oxide layers on both sides of the silicon substrate, the thickness of the tunneling oxide layers at the corners of the silicon substrate is greater than the thickness of the tunneling oxide layers at the periphery of the silicon substrate.

[0124] Those skilled in the art can fully understand that the above-described situations are applicable to local situations and have nothing to do with the size of the silicon wafer.

[0125] In another embodiment of the present application, in an assembly composed of the above-mentioned cells of the present application, in addition to each cell itself satisfying any of the above-mentioned conditions, the inter-sheet uniformity of the tunneling oxide layer of any two solar cells is 0% to 20%; wherein, the inter-sheet uniformity of any two tunneling oxide layers = (the maximum thickness value appearing on any two tunneling oxide layers - the minimum thickness value appearing on any two tunneling oxide layers) / (the maximum thickness value of the tunneling oxide layer appearing on any two tunneling oxide layers + the minimum thickness value of the tunneling oxide layer appearing on any two tunneling oxide layers) * 100%.

[0126] Exemplarily, the inter-chip uniformity can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, or 20%.

[0127] Those skilled in the art can understand that inter-cell uniformity is intended to control the relationship between any two cells in a component, and each cell satisfies at least one of the above-mentioned schemes of the solar cell described in this application.

[0128] For any battery in the battery assembly, the maximum thickness or the minimum thickness of the tunneling oxide layer on the battery is detected as described above, that is, it is necessary to select any multiple sites on the battery for detection, select the maximum and minimum values, and compare them with the data of any other battery in pairs to calculate the inter-sheet uniformity of any two tunneling oxide layers.

[0129] It can be understood that the solar cell provided in the present application includes but is not limited to the solar cell provided above, as long as the provided solar cell includes the tunneling oxide layer formed by the above method.

[0130] When the solar cell is a half-cell formed by cutting the silicon wafer end: the selection of measurement points can refer to the situation of the whole cell. When the solar cell is a half-cell formed by cutting the whole cell: the selection of measurement points can also refer to the situation of the whole cell. However, due to different preparation processes, the damage caused by different processes is distributed differently in the half-cell. For example, when the solar cell is a half-cell formed by cutting the silicon wafer end, the thickness distribution of the tunneling oxide layer of the half-cell can be set to the same characteristics as the whole cell. For details, please refer to the description of the whole cell. When the solar cell is a half-cell formed by cutting the whole cell, one side of the half-cell corresponds to the midline position of the original whole cell. Therefore, the thickness of the tunneling oxide layer at this position has a minimum value. Because there are fewer defects here, there is no need to set a thick tunneling oxide layer to ensure better electron transmission.

[0131] Two specific embodiments are provided below:

[0132] Example 1

[0133] A method for preparing a uniform tunneling oxide layer by pre-sintering and cooling, comprising the following steps:

[0134] Step 1: Select 15 N-type silicon wafers as substrate materials, and create a tower base structure on the surface of the silicon wafers through cleaning and polishing.

[0135] Step 2: First, place the 15 polished silicon wafers into the LPCVD tube furnace, evacuate the furnace, adjust the temperature to 550°C, and maintain the constant temperature for 3 minutes.

[0136] Step 3: Pull the 15 pre-sintered silicon wafers out of the tube furnace and cool them in air for 5 minutes.

[0137] Step 4: Put the 15 cooled silicon wafers into the furnace tube again, evacuate and purge with nitrogen in the furnace tube, introduce oxygen at a flow rate of 30,000 sccm, set the temperature to 610°C, and keep the pressure at normal pressure for 10 minutes. Then close the oxygen inlet valve, and keep the 15 silicon wafers in the tube for 15 minutes. Then take them out of the furnace to prepare the tunneling oxide layer.

[0138] Example 2

[0139] A method for preparing a uniform tunneling oxide layer by pre-sintering and cooling, comprising the following steps:

[0140] Step 1: Select 15 N-type silicon wafers as substrate materials, and create a tower base structure on the surface of the silicon wafers through cleaning and polishing.

[0141] Step 2: First, place the 15 polished silicon wafers into the LPCVD tube furnace, evacuate the furnace, adjust the temperature to 600°C, and maintain the constant temperature for 3 minutes.

[0142] Step 3: Pull the 15 pre-sintered silicon wafers out of the tube furnace and cool them in air for 5 minutes.

[0143] Step 4: Put the 15 cooled silicon wafers into the furnace tube again, evacuate and purge with nitrogen in the furnace tube, introduce oxygen at a flow rate of 30,000 sccm, set the temperature to 610°C, and keep the pressure at normal pressure for 10 minutes. Then close the oxygen inlet valve, and keep the 15 silicon wafers in the tube for 15 minutes. Then take them out of the furnace to prepare the tunneling oxide layer.

[0144] Comparative Example

[0145] A method for preparing a tunneling oxide layer comprises the following steps:

[0146] Step 1: Select 15 N-type silicon wafers as substrate materials, and create a tower base structure on the surface of the silicon wafers through cleaning and polishing.

[0147] Step 2: Place 15 polished silicon wafers into the LPCVD furnace tube, evacuate the tube and purge with nitrogen, introduce an oxygen flow rate of 30,000 sccm, set the temperature to 610°C, and keep the pressure at normal pressure for 10 minutes. Then close the oxygen inlet valve and keep the 15 silicon wafers in the tube for 15 minutes. Then take them out of the furnace to prepare the tunneling oxide layer.

[0148] For the tunneling oxide layer on each of the 15 silicon wafers prepared in the above-mentioned Examples 1, 2 and the comparative example, the thickness was measured using an ellipsometer. Specifically, the 15 silicon wafers were placed on 15 boats loaded with semiconductor substrates in different temperature zones in a tube furnace, and the semiconductor substrate in each boat was taken for thickness measurement. For the semiconductor substrate at each position in the furnace tube, the tunneling oxide layer thickness of the semiconductor substrate at the four corner positions and the center position, a total of 5 points, was tested, and the average thickness of the 5 points was taken as the average thickness of the semiconductor substrate. The measured results are shown in FIG. Figure 2 shown.

[0149] Furthermore, the thickness of the tunnel oxide layer at the five points detected on each silicon wafer is used to select the maximum and minimum values, and the uniformity of each tunnel oxide layer within the wafer is calculated. The calculation results are as follows: Figure 3 As shown in the figure, the intra-chip uniformity of the tunneling oxide layer = (the maximum value of the thickness of the tunneling oxide layer - the minimum value of the thickness of the tunneling oxide layer) / (the maximum value of the thickness of the tunneling oxide layer + the minimum value of the thickness of the tunneling oxide layer) * 100%. The smaller the value of the intra-chip uniformity is, the better the intra-chip uniformity is.

[0150] Depend on Figure 2 It can be seen that the average thickness of the tunnel oxide layer prepared in the embodiment of the present application and the comparative example is not much different, basically between 1.75nm-1.85nm, but from Figure 3 It can be seen that the in-chip uniformity of the tunneling oxide layers of Examples 1 and 2 and the comparative example is quite different. The in-chip uniformity of the tunneling oxide layers of the 15 silicon substrates with tunneling oxide layers of Examples 1 and 2 is in the range of 2%-6%, while the in-chip uniformity of the corresponding tunneling oxide layers of the comparative example is in the range of 7%-16%. Figure 3 It can also be seen that the in-wafer uniformity of the silicon wafers at different positions in Example 1 and Example 2 is better than that in the comparative example. By comparison, it can be seen that the in-wafer uniformity of Example 1 and Example 2 is significantly better than that in the comparative example, indicating that the in-wafer uniformity of the tunnel oxide layer can be significantly improved by pre-sintering and cooling processes.

[0151] A single semiconductor silicon substrate was selected from the 16th boat in Example 1, and the thickness of the tunnel oxide layer at 5 points, including the four corner positions and the center position of the semiconductor substrate, was tested. The results are as follows: Figure 5 As shown, it can be seen that the maximum thickness of the silicon wafer occurs at a position corresponding to a corner of the silicon substrate, which is corner 3. The average thickness of the semiconductor substrate is 1.84 mm, and the in-wafer uniformity of the silicon wafer is 3.53%.

Claims

1. A method for preparing a tunneling oxide layer, comprising the following steps: Pre-sintering the semiconductor substrate in an oxygen-free condition and within a first preset temperature range for a first preset time; Cooling the pre-sintered semiconductor substrate at room temperature; A tunnel oxide layer is formed on the cooled semiconductor substrate.

2. The preparation method according to claim 1, wherein the semiconductor substrate is pre-sintered in an oxygen-free condition and maintained within a first preset temperature range for a first preset time, comprising: The semiconductor substrate is pre-sintered in an oxygen-free condition and maintained at a constant temperature within a first preset temperature range for a first preset time.

3. The preparation method according to claim 1 or 2, wherein the first preset temperature range is 400°C-600°C, and the first preset time is 3 min-5 min.

4. The preparation method according to claim 1 or 2, wherein the cooling temperature is 20°C-30°C and the cooling time is 3min-10min. 5 . The preparation method according to claim 1 , wherein the pre-sintering and the preparation of the tunneling oxide layer are performed in the same furnace tube. The preparation method according to claim 1 , wherein the pre-sintering and the preparation of the tunneling oxide layer are performed in different furnace tubes. 7 . The preparation method according to claim 1 , wherein a method for preparing the tunneling oxide layer is selected from a thermal oxidation method, a chemical vapor deposition method, an atomic layer deposition method, and a wet oxidation method.

8. The preparation method according to claim 1, wherein the preparation of the tunnel oxide layer comprises the following steps: placing the cooled semiconductor substrate into a furnace tube, evacuating the furnace tube and purging the furnace tube with nitrogen; introducing oxygen within a second preset temperature range, a second preset time, and a preset pressure; The oxygen inlet valve is closed, and the semiconductor substrate is kept in the furnace tube for a third preset time to prepare a tunneling oxide layer on the semiconductor substrate.

9. The preparation method according to claim 8, wherein the second preset temperature range is 560°C-650°C, the second preset time is 5min-20min, the flow rate of the oxygen is 5000-50000sccm, the preset pressure is normal pressure, and the third preset time is 10min-30min.

10. A solar cell, characterized in that: It comprises a silicon substrate and a tunneling oxide layer arranged on the silicon substrate, wherein the in-chip uniformity of the tunneling oxide layer is 2% to 6%; The intra-chip uniformity of the tunneling oxide layer=(maximum thickness of the tunneling oxide layer-minimum thickness of the tunneling oxide layer) / (maximum thickness of the tunneling oxide layer+minimum thickness of the tunneling oxide layer)*100%.

11. The solar cell according to claim 10, wherein: Tunneling oxide layers are formed on both sides of the silicon substrate, wherein the in-chip uniformity of the tunneling oxide layers on both sides is 2% to 6%; wherein the in-chip uniformity of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / (maximum thickness of the tunneling oxide layer + minimum thickness of the tunneling oxide layer) * 100%.

12. The solar cell according to claim 10 or 11, wherein: The maximum thickness of the tunneling oxide layer on one side or both sides of the silicon substrate appears at a position corresponding to the corner of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100% ； and / or The maximum thickness of the tunneling oxide layer on one side or both sides of the silicon substrate occurs at a position corresponding to the periphery of the silicon substrate, and the thickness difference ratio of the tunneling oxide layer is greater than 0% and less than or equal to 30%, wherein the thickness difference ratio of the tunneling oxide layer = (maximum thickness of the tunneling oxide layer - minimum thickness of the tunneling oxide layer) / minimum thickness of the tunneling oxide layer * 100%.

13. The solar cell according to claim 12, wherein: For the tunneling oxide layer on one side or both sides of the silicon substrate, the thickness of the tunneling oxide layer at a corner position corresponding to the silicon substrate is greater than the thickness of the tunneling oxide layer at a peripheral position corresponding to the silicon substrate.

14. A solar cell module comprising two or more solar cells according to any one of claims 10 to 13.

15. The assembly of claim 14, wherein: The inter-sheet uniformity of the tunneling oxide layers of any two of the solar cells is 0% to 20%; Among them, the inter-sheet uniformity of any two of the tunneling oxide layers = (the maximum thickness value appearing on any two tunneling oxide layers - the minimum thickness value appearing on any two tunneling oxide layers) / (the maximum thickness value of the tunneling oxide layers appearing on any two tunneling oxide layers + the minimum thickness value of the tunneling oxide layers appearing on any two tunneling oxide layers) * 100%.

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