Efficient extraction and layout optimization method and system for parasitic inductance parameters

Abstract

The invention belongs to the technical field of inductance parameter extraction, discloses an efficient extraction and layout optimization method and system for parasitic inductance parameters of a power semiconductor module, and realizes efficient interaction of simulation data among software based on powerful simulation capabilities of commercial software ANSYS and MATLAB and a joint simulation interface. And convenience is provided for extracting module parasitic inductance parameters and current sharing characteristics. An effective algorithm for analyzing parasitic inductance parameters and current sharing characteristics is applied, scientific guidance is provided for optimizing module layout, and the method has the following remarkable advantages that compared with a method of'artificial experience + hardware debugging ', an efficient simulation development means is adopted, frequent hardware iteration in manufacturing and verification links can be avoided, and the method has the advantages that development cost is reduced, and efficiency is improved. Therefore, the research and development efficiency of the multi-chip silicon carbide power module is improved, and the advantages of higher quality and flexible development of the multi-chip silicon carbide power module are better supported.

Description

Technical Field

[0001] The present invention belongs to the technical field of inductance parameter extraction, and in particular relates to a method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing the layout. Background Art

[0002] Power semiconductor devices are core devices for power conversion, control and utilization, and their characteristics directly affect the efficiency and reliability of power electronic systems. With the increasing maturity of silicon carbide power devices represented by SiC MOSFET, the continuous advancement of integrated packaging technology and the continuous extension of power conversion needs, silicon carbide power modules have become an important way to develop ultra-high power density power conversion equipment. Due to the large design content, long process flow and complicated manufacturing verification of multi-chip parallel power modules, the development model that relies on manual experience and hardware testing is difficult to meet the design requirements of power devices in terms of parasitic parameter extraction and current sharing characteristics. When considering the use of ANSYS simulation to design power semiconductors, the long simulation time, uncertainty and complex design process make the process also time-consuming and labor-intensive. Therefore, there is still a lack of accurate and efficient power module current sharing methods.

[0003] Through the above analysis, the problems and defects of the prior art are as follows:

[0004] In the past, methods for obtaining the parasitic inductance and current sharing characteristics of power modules mostly relied on the designer's "artificial experience + hardware testing" or manually calling a variety of finite element and time domain circuit analysis software. Although these methods can accurately obtain the required module parasitic inductance and current sharing characteristics, they are usually difficult to meet the growing performance and development time requirements of power modules, and there are the following problems:

[0005] (1) The initial design and iteration direction selection are mainly determined by the designer’s experience. Due to the high degree of freedom in power module design, the module layout and electrical parameters are not a simple linear relationship, and it is difficult to approach the design limit manually;

[0006] (2) Parameter evaluation requires manual use of multiple finite element and time domain circuit analysis software, which is computationally intensive, time-consuming, and has high human resource costs. Summary of the invention

[0007] In view of the problems existing in the prior art, the present invention provides a method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing its layout.

[0008] The present invention is implemented as follows: a method for efficiently extracting and optimizing the layout of parasitic inductance parameters of a power semiconductor module, which realizes efficient and accurate design optimization through four main steps. First, in step 1, the initial parameters are defined and the parasitic inductance is extracted, and an advanced simulation tool such as ANSYS Q3D is used to automatically identify the circuit network and preliminarily extract the inductance value. Subsequently, in step 2, these simulation data are transferred to the MATLAB environment for further analysis and processing. Step 3 re-analyzes the optimization suggestions provided by MATLAB through an automated ANSYS script, and the automated process significantly improves the analysis efficiency. Finally, in step 4, result feedback and iterative optimization are performed based on the re-analysis results, and advanced optimization techniques such as genetic algorithms are used to adjust the circuit layout to minimize parasitic inductance and improve module performance. This process integrates the latest computing technologies and algorithms, significantly improves the accuracy and efficiency of circuit design, and ensures the high performance and reliability of the final product.

[0009] Further, the initial parameter definition and parasitic inductance extraction method are as follows:

[0010] (1) Design basic circuit layout;

[0011] (2) Determine the material properties of the power module;

[0012] (3) Arrange circuits and automatically identify networks;

[0013] First, select the excitation source SOURCE and ground SINK. The specific meaning of each port has been determined during the circuit diagram making process;

[0014] Through ANSYS Q3D's automatic network recognition function, the unique electrical path of the model is determined and displayed;

[0015] (4) Extract parasitic inductance;

[0016] The circuit is simulated and the resistance and inductance parameters of the circuit are extracted.

[0017] Further, the basic circuit layout of the design is:

[0018] 1) Package parasitic inductance calculation model - accumulation method;

[0019] The inductance of a rectangular conductor is:

[0020]

[0021] Where, L σ is the inductance, H; l R , b R 、h R are the length, width and thickness of the conductor, mm; μ0=4π×10 -7H / m is the vacuum permeability;

[0022] The inductance of a long straight wire is:

[0023]

[0024] In the formula, l L and d L are the length and diameter of the wire, mm; if d L <<l L , then the inductance of a long straight wire can be expressed as:

[0025]

[0026] For the case of multiple bonding wires in parallel, the parasitic inductance presented by a cluster of bonding wires is equivalent to:

[0027]

[0028] Where N is the number of bonding wires;

[0029] 2) Calculation model of parasitic inductance of rectangular loop package—magnetic field cancellation method;

[0030] Inductance λ σ , which is derived as follows:

[0031] The closed rectangular loop inductance is:

[0032]

[0033] In the formula, a C and b C are the length and width of the rectangle, d C is the diameter of the conductor, mm; if d C <<a C and b C , which can be simplified to:

[0034]

[0035] In the formula, C C =2(a C +b C ) and S C =a C b C are the perimeter and area of ​​the rectangular conductor, respectively; therefore, the inductance of the open rectangular loop is:

[0036]

[0037] Open rectangular loop inductance λ σ It can be defined as:

[0038] λσ =C C oeLh C -b C [ln(2b C )-1].

[0039] Further, the material properties of the power module are determined:

[0040] The preliminary model generated by SOLIDWORKS is transferred to ANSYS, and the materials of each part of the circuit are determined during the simulation process. The determined parts are divided into bonding wires, DBCs, power chips and bus bars.

[0041] Further, the simulation data is transmitted:

[0042] After completing the extraction of parasitic inductance, the simulation data in ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report.

[0043] Further, the ANSYS script automates and reanalyzes:

[0044] According to the new layout scheme provided by MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis.

[0045] Another object of the present invention is to provide a system for efficiently extracting and optimizing the layout of parasitic inductance parameters of a power semiconductor module, comprising:

[0046] Extraction module, used for initial parameter definition and parasitic inductance extraction;

[0047] Data transfer module, used for simulating data transfer;

[0048] Analysis module for ANSYS script automation and reanalysis;

[0049] The feedback module is used to feed back the results of the parasitic inductance analysis under the new layout after completing it through ANSYS software to MATLAB.

[0050] Another object of the present invention is to provide a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method for efficiently extracting parasitic inductance parameters of the power semiconductor module and optimizing the layout.

[0051] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the method for efficiently extracting and optimizing the layout of parasitic inductance parameters of a power semiconductor module.

[0052] Another object of the present invention is to provide an information data processing terminal, which is used to implement the efficient extraction and layout optimization system of the parasitic inductance parameters of the power semiconductor module.

[0053] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0054] First, the present invention is based on the powerful simulation capabilities and joint simulation interface of commercial software ANSYS and MATLAB, which realizes efficient interaction of simulation data between software and facilitates the extraction of module parasitic inductance parameters and current sharing characteristics. By using effective algorithms for analyzing parasitic inductance parameters and current sharing characteristics, scientific guidance is provided for optimizing module layout. The present invention has the following significant advantages:

[0055] Compared with the "manual experience + hardware debugging" method, the present invention adopts efficient simulation development means, which can avoid frequent hardware iterations in the manufacturing and verification links, reduce development costs, and thus improve the research and development efficiency of multi-chip silicon carbide power modules, and better support its advantages of higher quality and flexible development.

[0056] Compared with calling analysis software, the real-time interaction between ANSYS and MATLAB not only ensures the accuracy of ANSYS finite element analysis, but also takes advantage of the simplicity of MATLAB in programming intelligent optimization algorithms and writing mathematical model objective functions. This real-time interaction can save a lot of time and human resources, significantly reduce manual intervention, and greatly improve the degree of automation and intelligence.

[0057] Second, the present invention proposes a method for efficiently extracting and optimizing the layout of parasitic inductance parameters of power semiconductor modules, which solves the problems of low efficiency and insufficient accuracy in the prior art when dealing with parasitic inductance parameter extraction and optimization. Through this method, the parasitic inductance parameters of power semiconductor modules can be extracted and optimized more accurately and efficiently, thereby improving the electrical performance and reliability of the modules.

[0058] The definition of initial parameters and the extraction of parasitic inductance lay the foundation for the entire process. By designing the basic circuit layout, clarifying the material properties of the power module, and using simulation software to automatically identify the circuit network, this stage ensures the pertinence and efficiency of subsequent optimization. In particular, the parasitic inductance of conductors of different geometric shapes is calculated through the accumulation method and magnetic field elimination method, providing accurate initial data and theoretical basis.

[0059] The integration of simulation data transmission, automatic execution of ANSYS scripts and re-analysis work makes the whole process highly automated, reduces manual intervention and improves the speed and accuracy of data processing. In particular, the use of ANSYS makes the simulation closer to the actual situation and provides a more accurate evaluation of inductance parameters.

[0060] The result feedback and iterative optimization stage not only optimizes and adjusts the system according to the simulation results, but also continuously refines the model parameters based on the iterative process until the optimal design is achieved. This feedback-based iterative optimization method can significantly improve design efficiency, reduce trial and error costs, and accelerate product development cycles.

[0061] The present invention significantly improves the accuracy and efficiency of power semiconductor module design by combining an accurate parasitic inductance calculation model, an efficient data processing flow, and an intelligent iterative optimization strategy, and provides an effective means for improving the performance and reliability of power semiconductor modules. This not only helps to reduce power loss and improve energy efficiency, but also promotes the application and development of power semiconductor technology in the fields of energy, electronics, etc.

[0062] Third, as auxiliary evidence of the inventiveness of the claims of the present invention, it is also reflected in the following important aspects:

[0063] (1) The technical solution of the present invention fills the technical gap in the industry at home and abroad:

[0064] After more than 40 years of research and development of power devices, the physical properties of Si power modules have approached the physical limit. In recent years, the research on SiC advanced semiconductor materials has become a hot area of ​​scientific research. SiC advanced semiconductor materials have higher energy gap, breakdown field strength, thermal conductivity and other excellent properties, which bring hope and opportunities for the development of high-voltage, high-temperature and high-frequency power devices, and provide technical advantages for high-efficiency, high-power density and high-reliability power conversion. With the increasing maturity of silicon carbide power devices represented by SiC MOSFET, the continuous progress of integrated packaging technology and the continuous extension of power conversion needs, SiC power modules have become an important way to develop ultra-high power density conversion equipment. However, SiC power devices have a large-scale breakthrough in the technical system of Si power devices, especially in packaging integration, transient testing and other aspects. There is a lack of basic theory and key technical support. In addition, due to the large design content, long process flow and complicated manufacturing verification of multi-chip parallel power modules, the development model relying on manual experience and hardware testing is difficult to meet the design requirements of SiC power devices in terms of parasitic parameter extraction and current sharing characteristics. In terms of simulation systems, the use of ANSYS to simulate and design power semiconductors has disadvantages such as long simulation time, complex design process and large uncertainty in simulation results, which makes the simulation process also time-consuming and labor-intensive. Therefore, there is still a lack of accurate and efficient power module current equalization methods.

[0065] Based on the above technical status and scientific research difficulties in the industry at home and abroad, the present invention is committed to developing a fast, accurate, efficient and automatic joint simulation system to fill the gap in the field of parasitic parameter extraction simulation of SiC multi-chip parallel power semiconductors. The present invention is based on the powerful simulation capabilities and joint simulation interface of the two major commercial software ANSYS and MATLAB, and researches and develops the real-time interactive function of ANSYS and MATLAB, making full use of ANSYS's own script recording and script simulation functions, so as to build an ANSYS-MATLAB interactive simulation bridge through the script code, a readable carrier, which greatly improves the directionality, controllability and readability of simulation control. Developers can use the present invention to easily convey simulation goals to ANSYS through MATLAB, and the parameter extraction and layout optimization scheme of the power module can be controlled through lines of concise MATLAB code. The entire simulation system iterates until the designer's functional needs for the module are met. The invention makes full use of the accuracy of ANSYS in the field of finite element analysis and the simplicity of MATLAB in programming intelligent optimization algorithms and writing mathematical model objective functions. The real-time interaction between the two greatly improves the automation and intelligence of power module parasitic parameter extraction, avoids frequent hardware iterations in power module manufacturing and verification, greatly reduces its development cost, saves a lot of time and human resources, and significantly reduces manual intervention.

[0066] Based on the present invention, the parameter extraction and layout optimization research of power modules will have a more efficient, convenient, high-quality and flexible simulation method as technical support, which provides very important basic technical support for research directions such as obtaining the current sharing characteristics of power modules and improving and developing the layout of power modules in fields with higher technical levels and strong applicability.

[0067] (2) The technical solution of the present invention solves a technical problem that people have been eager to solve but have never been able to solve successfully:

[0068] Previous development methods can also use digital software to achieve virtual iterative design of power modules, but they are still highly dependent on designer experience and have the following limitations:

[0069] 1) Parameter evaluation requires manual calling of multiple finite element simulation analysis software, which is computationally intensive, time-consuming, and has high human resource costs.

[0070] 2) Both the initial design and the iterative direction selection depend on the designer’s experience. Due to the high degree of freedom in power module design and the influence of high-frequency switching excitation and coupling effects, the module layout and parameters are not a simple linear relationship, and it is difficult to approach the design limit manually.

[0071] 3) Traditional simulation methods struggle to handle multi-objective problems and produce single results. Since there are multiple trade-offs between power module design objectives and different applications have different trade-off requirements for parasitic parameters, traditional simulation methods usually require repeated iterations when updating design objectives, resulting in low design flexibility.

[0072] In summary, when developers obtain the parasitic inductance and current sharing characteristics of power modules, they usually rely on "artificial experience + hardware testing" or manually call a variety of finite element and time domain circuit analysis software. Although these methods can accurately obtain the required module parasitic inductance and current sharing characteristics, they are usually difficult to meet the growing performance and development time requirements of power modules. The industry urgently needs flexible, efficient, and complete digital design tools.

[0073] The present invention solves the above technical problems in the following three aspects:

[0074] 1) Power module parameter evaluation and layout optimization no longer require manual calling of multiple finite element simulation analysis software. The ANSYS-MATLAB joint simulation method developed in the present invention can realize fully automatic simulation analysis in a direction after specifying the power module layout optimization target until the developer's design requirements are met, which greatly saves experimental links, experimental time and human resources.

[0075] 2) The ANSYS-MATLAB joint simulation method developed by the present invention can completely rely on digital algorithms to select the iterative direction of module layout, so as to achieve full digital design and no longer rely on the designer's experience. Digital algorithms have incomparable advantages over manual experience design in terms of high degree of freedom and nonlinear problems. In the field of power module layout design, which is difficult to approach the design limit manually, developers can use digital algorithms to convert the design goals into rows of visually readable digital algorithms (such as genetic algorithms, particle swarm algorithms or simulated annealing algorithms, etc.) in MATLAB. MATLAB can guide ANSYS to extract parasitic parameters and improve module layout step by step according to the algorithm. The two interact and iterate in a loop to finally solve nonlinear problems with high degree of freedom such as power module design.

[0076] 3) The present invention can also properly solve the multi-objective collaborative planning problems often encountered in power module parameter extraction and layout design. Using MATLAB to write a digital intelligent algorithm to guide the simulation process is a major technical innovation of the present invention, especially in the multi-objective collaborative planning problem, it can better reflect its important role. For example, the application of the NSGA-II algorithm in the multi-objective collaborative design of power modules can use digital algorithms to realize the computer's "unraveling" of design goals and design mechanisms to find the appropriate direction of the design. Traditional design solutions that rely on manual experience usually expose problems such as long time consumption, low efficiency, and rigid design process when solving multi-objective collaborative design problems. The ANSYS-MATLAB joint simulation method developed by the present invention relies on its advantages of fewer links, high efficiency, and flexible development to greatly make up for the industry's predicament in simulation design.

[0077] Fourth, the present invention provides a method for efficiently extracting parasitic inductance parameters of power semiconductor modules and optimizing their layout, which solves the technical problems of low efficiency, insufficient accuracy and insufficient layout optimization in the prior art, and has achieved significant technical progress in industrial applications. The core technical features of the present invention and its application results in industry are analyzed in detail below.

[0078] Existing technical problems solved:

[0079] 1. Low extraction efficiency:

[0080] In traditional methods, parameter extraction of parasitic inductance often relies on manual measurement or simple circuit simulation, which is inefficient and cannot quickly adapt to the design requirements of complex circuits.

[0081] The present invention uses an automated script in combination with a simulation tool (such as ANSYS Q3D) to automatically identify circuit networks and extract inductance parameters, thereby greatly improving efficiency.

[0082] 2. Lack of precision:

[0083] Traditional extraction methods fail to accurately simulate circuit behavior under actual working conditions, resulting in deviations between the extracted inductance parameters and the actual application scenarios.

[0084] By implementing simulation based on physical models (using SOLIDWORKS and ANSYS to simulate material properties and geometric structures in detail), the present invention ensures the accuracy and reliability of the extracted parameters.

[0085] 3. Insufficient layout optimization:

[0086] Traditional layout design often relies on the designer's experience and intuitive judgment and lacks a systematic optimization process.

[0087] The present invention utilizes the genetic algorithm in MATLAB to automatically generate the optimized layout, and then verifies and analyzes it again through ANSYS to ensure the optimal circuit layout and the lowest parasitic inductance.

[0088] Technological Advancements in Industrial Applications:

[0089] 1. Automation and high efficiency:

[0090] The automated design and parameter extraction process significantly reduces the time from design to verification, greatly shortening the product development cycle and improving R&D efficiency and market response speed.

[0091] It is suitable for rapid iteration and optimization in mass production, which is extremely important in the power electronics industry.

[0092] 2. Improve design accuracy and reliability:

[0093] Accurate simulation analysis helps designers understand and optimize the impact of inductance in the circuit, thereby designing more efficient and stable power semiconductor modules.

[0094] This directly improves the performance and reliability of the end product, reducing power losses and failure rates.

[0095] 3. Significant cost-effectiveness:

[0096] By optimizing circuit layout and reducing unnecessary design iterations, material and manufacturing costs are significantly reduced.

[0097] The automated and efficient design process reduces labor and time costs, bringing greater economic benefits to the enterprise.

[0098] 4. Scalability and flexibility:

[0099] The method provided by the present invention can be widely applied to designs of different types of power semiconductor modules and has good scalability.

[0100] It supports the rapid adaptation and implementation of new design requirements and technological changes, enhancing the competitiveness of enterprises in the highly competitive market.

[0101] By combining advanced simulation technology and automated scripts, the present invention not only solves the efficiency and accuracy problems existing in traditional methods, but also achieves significant technological progress in the power semiconductor industry, providing an efficient, accurate and economical parasitic inductance parameter extraction and layout optimization solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] Figure 1 It is a flow chart of a method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing layout provided by an embodiment of the present invention.

[0103] Figure 2 It is a structural block diagram of a system for efficient extraction and layout optimization of parasitic inductance parameters of a power semiconductor module provided by an embodiment of the present invention.

[0104] Figure 3 It is a blueprint diagram of an optimized circuit provided by an embodiment of the present invention.

[0105] Figure 4 It is a SOILEWORKS model diagram provided by an embodiment of the present invention.

[0106] Figure 5 It is a material property diagram for determining a power module provided by an embodiment of the present invention.

[0107] Figure 6 It is a schematic diagram of selecting an excitation source and a ground provided in an embodiment of the present invention.

[0108] Figure 7 This is an automatic identification network diagram provided by an embodiment of the present invention.

[0109] Figure 8 1 is a diagram of extracted parasitic inductance provided by an embodiment of the present invention.

[0110] Fig. 9 This is a power semiconductor model diagram provided by an embodiment of the present invention.

[0111] Fig.10 It is an ANSYS and MATLAB interaction preparation diagram provided by an embodiment of the present invention.

[0112] Fig.11 This is the first iteration graph started after the circle function is run according to the embodiment of the present invention.

[0113] Fig.12 This is a first iteration nearly completed graph provided by an embodiment of the present invention.

[0114] Fig.13 This is a power semiconductor model diagram iterated 10 times according to an embodiment of the present invention.

[0115] Fig.14 This is a diagram for generating ACLiter.tab provided by an embodiment of the present invention.

[0116] Fig.15 This is a method for generating a line graph provided by an embodiment of the present invention.

[0117] Fig.16 It is a schematic diagram of the current sharing characteristics of the circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0118] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0119] The method for efficiently extracting parasitic inductance parameters of power semiconductor modules and optimizing layout of the present invention can be widely applied to different types of power electronic devices. The following are two specific application examples, which will illustrate how to apply the present invention to actual industrial design.

[0120] Application Example 1: Power Module Design in Electric Vehicle Drive System

[0121] In the drive system of electric vehicles, the power module is one of the key components, and its performance directly affects the efficiency and reliability of the motor. The power module of electric vehicles needs to handle high voltage and high current, so it is crucial to optimize its internal parasitic inductance to reduce switching losses and improve response speed.

[0122] Implementation method:

[0123] 1. Design basic circuit layout: Use SOLIDWORKS to design the preliminary physical structure of the power module, including IGBT, diode, conductive path, etc.

[0124] 2. Determine material properties: Select appropriate materials (such as silicon carbide) to ensure the stability of the module under high temperature and high pressure environments.

[0125] 3. ANSYS Q3D simulation: Import the design into ANSYS Q3D and use the software to automatically identify the circuit network and extract parasitic inductance.

[0126] 4. MATLAB optimization: The extracted data was imported into MATLAB and the circuit layout was optimized using genetic algorithms to try to reduce parasitic inductance.

[0127] 5. Re-simulation and physical testing: Adjust the ANSYS model according to the suggestions after MATLAB optimization, manufacture the prototype after simulation verification and conduct real vehicle testing.

[0128] The optimized power module demonstrated lower heat loss and higher power output efficiency in actual vehicle tests, effectively extending the driving range and battery life of electric vehicles.

[0129] Application Example 2: Power Module Optimization of Solar Inverter

[0130] Solar inverters convert direct current from solar panels into alternating current that can be supplied to the grid. In the inverter, the efficiency and stability of the power module determine the performance and energy conversion efficiency of the entire system.

[0131] 1. Circuit Design: Design a complex circuit with multiple switches and filters to ensure it can handle the large variations in DC input from the solar panels.

[0132] 2. Material selection and simulation: Select semiconductor materials suitable for high-frequency switching and set the corresponding physical properties in ANSYS.

[0133] 3. Automatic identification and parasitic inductance extraction: Use the automatic network identification function of ANSYS Q3D to extract the parasitic inductance of the circuit and perform preliminary simulation.

[0134] 4. Layout optimization: Use algorithms in MATLAB to analyze circuit layout and optimize wire placement and component locations to reduce parasitic inductance.

[0135] 5. Verification and implementation: Adjust the design and re-simulate in ANSYS. After confirming the inductance reduction, manufacture the test unit and perform performance testing in the actual solar system.

[0136] Through optimization, the new solar inverter power module shows higher energy efficiency and lower heat loss, which improves the reliability and economy of the entire system and reduces operating costs.

[0137] like Figure 1 As shown, a method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing layout provided by an embodiment of the present invention comprises the following steps:

[0138] S101, initial parameter definition and parasitic inductance extraction;

[0139] S102, simulation data transmission;

[0140] S103, ANSYS script automation and reanalysis;

[0141] S104, result feedback and iterative optimization.

[0142] The initial parameter definition and parasitic inductance extraction method provided by the embodiment of the present invention are as follows:

[0143] (1) Design basic circuit layout;

[0144] (2) Determine the material properties of the power module;

[0145] (3) Arrange circuits and automatically identify networks;

[0146] First, select the excitation source SOURCE and ground SINK. The specific meaning of each port has been determined during the circuit diagram making process;

[0147] Through ANSYS Q3D's automatic network recognition function, the unique electrical path of the model is determined and displayed;

[0148] (4) Extract parasitic inductance;

[0149] The circuit is simulated and the resistance and inductance parameters of the circuit are extracted.

[0150] The basic circuit layout provided by the embodiment of the present invention is:

[0151] 1) Package parasitic inductance calculation model - accumulation method;

[0152] The inductance of a rectangular conductor is:

[0153]

[0154] Where, L σ is the inductance, H; l R 、b R 、h R are the length, width and thickness of the conductor, mm; μ0=4π×10 -7 H / m is the vacuum permeability;

[0155] The inductance of a long straight wire is:

[0156]

[0157] In the formula, l L and d L are the length and diameter of the wire, mm; if d L <<l L , then the inductance of a long straight wire can be expressed as:

[0158]

[0159] For the case of multiple bonding wires in parallel, the parasitic inductance presented by a cluster of bonding wires is equivalent to:

[0160]

[0161] Where N is the number of bonding wires;

[0162] 2) Calculation model of parasitic inductance of rectangular loop package—magnetic field cancellation method;

[0163] Inductance λ σ , which is derived as follows:

[0164] The closed rectangular loop inductance is:

[0165]

[0166] In the formula, aC and b C are the length and width of the rectangle, d C is the diameter of the conductor, mm; if d C <<a C and b C , which can be simplified to:

[0167]

[0168] In the formula, C C =2(a C +b C ) and S C =a C b C are the perimeter and area of ​​the rectangular conductor, respectively; therefore, the inductance of the open rectangular loop is:

[0169]

[0170] Open rectangular loop inductance λ σ It can be defined as:

[0171] λ σ =C C oeLh C -b C [ln(2b C )-1].

[0172] The material properties of the power module provided by the embodiment of the present invention are determined as follows:

[0173] The preliminary model generated by SOLIDWORKS is transferred to ANSYS, and the materials of each part of the circuit are determined during the simulation process. The determined parts are divided into bonding wires, DBCs, power chips and bus bars.

[0174] The simulation data transmission provided by the embodiment of the present invention:

[0175] After completing the extraction of parasitic inductance, the simulation data in ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report.

[0176] ANSYS script automation and re-analysis provided by the embodiment of the present invention:

[0177] According to the new layout scheme provided by MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis.

[0178] like Figure 2 As shown, an efficient extraction and layout optimization system of parasitic inductance parameters of a power semiconductor module provided by an embodiment of the present invention includes:

[0179] Extraction module, used for initial parameter definition and parasitic inductance extraction;

[0180] Data transfer module, used for simulating data transfer;

[0181] Analysis module for ANSYS script automation and reanalysis;

[0182] The feedback module is used to feed back the results of the parasitic inductance analysis under the new layout after completing it through ANSYS software to MATLAB.

[0183] An embodiment of the present invention provides a computer device, which includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of the method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing the layout.

[0184] A computer-readable storage medium provided by an embodiment of the present invention stores a computer program. When the computer program is executed by a processor, the processor executes the steps of the method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing layout.

[0185] An embodiment of the present invention provides an information data processing terminal, which is used to implement a system for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing its layout.

[0186] In the field of electromagnetic simulation and optimization, effective parasitic inductance minimization strategy is of vital importance to improving the performance of electronic devices. This study uses a method that combines ANSYS Q3D and MATLAB to optimize parasitic inductance through genetic algorithms to achieve more efficient circuit design. The specific process is as follows:

[0187] Step 1: Initial parameter definition and parasitic inductance extraction

[0188] First, in ANSYS Q3D, parasitic inductance extraction is performed based on the given initial layout position. Through accurate simulation, the parasitic inductance value of the circuit under a specific configuration can be obtained.

[0189] The specific process to achieve this goal is as follows:

[0190] 1. Design basic circuit layout

[0191] It should be noted that this algorithm is optimized on the existing circuit layout, so it is essential to optimize the reference circuit. This project uses the following calculation model to design the circuit:

[0192] 1.1 Package parasitic inductance calculation model - accumulation method

[0193] When the power semiconductor module is working, the current commutation path is irregular, and the DBC copper layer and bonding wire will contribute parasitic inductance. The parasitic inductance calculation model of the DBC copper layer and bonding wire is obtained, the inductance value of each area is calculated, and then the sum is taken to obtain the parasitic inductance value of the entire power circuit.

[0194] The DBC copper layer is equivalent to a rectangular conductor, and the bonding wire is equivalent to a long straight wire. Based on the parasitic inductance of regular conductors, a calculation model of package parasitic inductance can be established.

[0195] The inductance of a rectangular conductor is

[0196]

[0197] Where, L σ is the inductance, H; l R 、b R 、h R are the length, width and thickness of the conductor, mm; μ0=4π×10 -7 H / m is the magnetic permeability of vacuum.

[0198] The inductance of a long straight wire is

[0199]

[0200] In the formula, l L and d L are the length and diameter of the wire, mm. L <<l L , then the inductance of a long straight wire can be expressed as

[0201]

[0202] For the case of multiple bonding wires in parallel, the parasitic inductance presented by a cluster of bonding wires is equivalent to

[0203]

[0204] Where N is the number of bonding wires.

[0205] The accumulation method uses simplified assumptions and has poor accuracy, but it has a fast calculation speed and is suitable for quickly evaluating the parasitic inductance value of the module. The ANSYS Q3D finite element method simulation introduced later is the most accurate, but the calculation time is long and it is not suitable for rapid iteration of module design.

[0206] 1.2 Calculation model of parasitic inductance of rectangular loop package - magnetic field cancellation method

[0207] In the process of power module design, sometimes we only need to quickly evaluate the relative size of parasitic inductance without calculating its specific value, so we can define the inductance coefficient λ σ , which is derived as follows:

[0208] The closed rectangular loop inductance is

[0209]

[0210] In the formula, a C and b C are the length and width of the rectangle, d C is the diameter of the conductor, mm. If d C <<a C and b C , which can be simplified to

[0211]

[0212] In the formula, C C =2(a C +b C ) and S C =a C b C are the perimeter and area of ​​the rectangular conductor respectively. Therefore, the inductance of the open rectangular loop is

[0213]

[0214] Open rectangular loop inductance λ σ Can be defined as

[0215] λ σ =C C oeLh C -b C [ln(2b C )-1]

[0216] This coefficient is proportional to the parasitic inductance. It is a practical and fast method when there are many power circuits in this project and the true value of inductance is not important.

[0217] Considering the above two calculation methods, our team referred to various methods of inductance reduction and current sharing, such as multiple commutation loops, symmetrical terminal layout, interconnection line comparison, etc. After much consideration, the final circuit diagram adopts a symmetrical double-terminal layout, symmetrically arranges the DC power terminals, and realizes double-terminal circulation, thereby achieving the purpose of reducing the difference between parasitic inductance and parallel inductance. The circuit schematic diagram used for optimization is as follows: Figure 3 As shown, the SOLIDWORKS model is Figure 4 As shown, SOLIDWORKS modeling will use this circuit schematic as a reference, and all subsequent algorithms are based on the above circuit.

[0218] 2. Determine the material properties of the power module

[0219] The preliminary model generated by SOLIDWORKS is transferred to ANSYS. Figure 5 The process of determining the materials of each part of the circuit during the simulation is demonstrated. The parts that need to be determined can be mainly divided into bonding wires, DBCs, power chips and bus bars.

[0220] The material of the bonding wire can be selected from gold, copper, silver, and aluminum. Among them, although gold wire has the best conduction efficiency, its high price makes general application difficult and is not considered. Copper is more economical, but its rigidity is too strong and requires the addition of protective gas when used. Its reliability is not as good as that of aluminum wire. Silver is mainly used in special parts such as LEDs. Its other indicators are not as good as the other three metals during normal use. Aluminum wire has low consumables cost, short welding time, can withstand large current, has low requirements for the welding metal surface, and has many advantages. Considering the above, aluminum is finally selected as the bonding wire material.

[0221] The material selection of DBC also has certain considerations. Since aluminum is used as the material for the bonding wire, aluminum is given priority to the surface of DBC. However, when searching for material options for general power semiconductors, a three-layer structure of copper-ceramic-copper is generally used. The two metals have little difference in conductivity. Copper has high hardness, which can ensure the mechanical strength of DBC and has good thermal conductivity. Since the surface of DBC where copper is located is the main part of the circuit, the heat dissipation performance of aluminum cannot meet the requirements for excessive current. The reason for adding ceramics in the middle layer is to increase electrical insulation and ensure the normal operation of the circuit. Therefore, the modeling is modified to change the bottom layer into three layers, and the material of copper-ceramic-copper is selected.

[0222] The material selection of busbar is very similar to that of DBC. Because busbar is the main part of the circuit and needs to carry large current, the electrical conductivity and thermal conductivity need to be considered. At the same time, the position of the busbar requires it to have high rigidity, so copper is obviously more competent than aluminum, so copper is selected as the busbar material.

[0223] The types of materials in power chips are complex, and using only one material will inevitably result in errors. However, its internal structure is too complex, and it is not realistic to conduct detailed modeling and simulation after in-depth understanding. After consulting materials and full discussion, our team chose silver as the main material for power chips, because silver is mainly used as chip connection wires, and its performance in electromagnetic distribution is similar to that of the chip itself.

[0224] 3. Lay out circuits and automatically identify networks

[0225] First, select the excitation source (SOURCE) and ground (SINK). The specific meaning of each port has been determined in the process of making the circuit diagram. Here, it is just represented on the model. Then, through the automatic identification network function of ANSYS Q3D, the unique electrical path of the model is determined and displayed, ensuring the correctness of the model and preparing for subsequent simulation research. The specific process is as follows Figure 6 , 7 As shown, this step is not repeated in subsequent cycles.

[0226] 4. Extract parasitic inductance

[0227] According to the previous preparation, the circuit is simulated and the resistance and inductance parameters of the circuit are extracted. The specific process is as follows: Figure 8 shown.

[0228] Step 2: Simulation data transfer

[0229] After completing the extraction of parasitic inductance, the simulation data in ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report. This process ensures seamless data transfer and lays the foundation for further data analysis and processing.

[0230] Specifically, the extracted data is first exported in ANSYS Q3D. After the export, the file is read by MATLAB to obtain the corresponding parasitic inductance data.

[0231] In the script,

[0232] oEditor.CreateRelativeCS Array("NAME:RelativeCSParameters","Mode:=","Axis / Position","OriginX:=",_"29.100000000mm","OriginY:=","0.000000000mm","OriginZ:=",_"14. 000000000mm","XAxisXvec:=","1mm","XAxisYvec:=","0mm","XAxisZvec:=", _"0mm","YAxisXvec:=","0mm","YAxisYvec:=","1mm","YAxisZvec:=","0mm"),

[0233] Array("NAME:Attributes","Name:=",_"RelativeCS27_1")

[0234] Corresponding to the actual operation of ANSYS, "move the origin of the relative coordinate system RelativeCS from the original origin in the X direction by OriginX = 29.100000000mm, in the Y direction by OriginY = 0.000000000mm, in the Z direction by OriginZ = 14.000000000mm, and name the new relative coordinate system RelativeCS27_1".

[0235] oEditor.Rotate Array("NAME:Selections","Selections:=","wirebond_MOSlower","NewPartsModelFlag:=",_"Model"),Array("NAME:RotateParameters","RotateAxis:=","Y","RotateAngle:=","2deg")

[0236] This corresponds to the actual operation of ANSYS: "Rotate the wirebond_MOSlower device 2° with RelativeCS27_1 as the origin and the Y axis as the rotation axis."

[0237] Set oModule=oDesign.GetModule("AnalysisSetup")

[0238] oModule.EditSetup"Setup1",Array("NAME:Setup1","AdaptiveFreq:=","1MHz","SaveFields:=",_false,"Enabled:=",true,Array("NAME:AC","MaxPass:=",10,"MinPass:=",1,"MinConvPass:=",_

[0239] 1,"PerError:=",1,"PerRefine:=",30),"EnableTransitionRegionSolve:=",false,"ErrorValue:=",_"0.1")

[0240] oModule.EditSetup"Setup1",Array("NAME:Setup1","AdaptiveFreq:=","1MHz","SaveFields:=",_false,"Enabled:=",true,Array("NAME:AC","MaxPass:=",10,"MinPass:=",1,"MinConvPass:=",_

[0241] 1,"PerError:=",1,"PerRefine:=",30),"EnableTransitionRegionSolve:=",false,"ErrorValue:=",_"0.1")

[0242] This corresponds to the actual operation of ANSYS: "Set Setup1 to a simulation frequency of 1 MHz, do not retain field conditions, use AC simulation mode, set the maximum number of iterations to 10, the minimum number of iterations to 1, etc."

[0243] oProject.Save

[0244] oDesign.Analyze "Setup1"

[0245] Set oModule=oDesign.GetModule("ReportSetup")

[0246] oModule.CreateReport"ACL Matrix Table 1","Matrix","Data Table",_"Setup1:LastAdaptive",Array("Context:=","Original"),Array("Freq:=",Array(_"All")),Array("X Component:=","Freq","Y Component:=",Array(_"abs(ACL(BusBar:Source1,BusBar:Source1))"))

[0247] This corresponds to the actual operation of ANSYS: "Create simulation report ACL Matrix Table 1, use Freq (frequency) as the X-axis and abs(ACL(BusBar:Source1,BusBar:Source1)) (the absolute value of the obtained ACL) as the Y-axis to draw a graph."

[0248] oModule.ExportToFile"ACL Matrix Table 1",dir+fname,false

[0249] This corresponds to "store the result ACL Matrix Table 1 in dir+fname" in actual ANSYS operation.

[0250] From the above analysis, we can see that the script recording function of ANSYS provides a medium for the interaction between ANSYS and the outside world. These specific statements are rewritten using software such as MATLAB and controlled by the MATLAB main function, so that automatic iteration of ANSYS can be performed.

[0251] Step 3: ANSYS script automation and reanalysis

[0252] According to the new layout scheme provided by MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis. This step not only demonstrates the powerful ability of cross-platform automated scripts, but also provides an experimental basis for further optimization.

[0253] It is a simple process for MATLAB to receive ANSYS data, but it is a relatively complicated task to let MATLAB control ANSYS operation. Specifically, it is divided into two steps: writing scripts and executing scripts. Among them, the process of writing scripts is the most complicated. The writing of scripts needs to consider the three major functions required of ANSYS, which include: model modification, simulation parameter determination and simulation start. The steps of simulation parameter determination and simulation start are simple and easy to write. You only need to write the content in the script file.

[0254] In this model, the modification of the model only involves the function of rotating the model. To achieve this function, all factors of model rotation are considered first: the object to be rotated, the reference coordinate axis to be rotated, the direction of rotation, and the angle of rotation. In order to flexibly modify the model according to the needs of the genetic algorithm, the position_change function is first established, and it is hoped that it only needs to know the above parameters to realize the rotation of the model. The position_change function essentially translates the algorithm requirements into a script. During the writing process, it is noted that the script uses the displacement values ​​in the X, Y, and Z directions to determine the position of the new coordinates, the model name to determine the rotation object, the Y axis direction to determine the rotation direction, and the deg value to determine the rotation angle. After considering the above conditions, the two elements of the rotation object and the new coordinate position are translated first. To make the position_change function more concise, first, the two parameters bondLineX and bondLineY are used to determine the name of the rotation target and the position of the rotation coordinate system, that is, the actual coordinates in the three directions of X, Y, and Z. The requirement of using two parameters to determine the name of the rotation target can be achieved. Just create a two-dimensional array and use the target name as the array content. Since the bond line rotation always uses its vertical part as the rotation axis, it is better to use the vertical part as the Y axis. The X and Z axes remain unchanged with the initial coordinate system, and the position of the rotation coordinate system is determined. This function is implemented in the two functions trans and findparameters. However, it is not enough to determine the position of the rotation coordinate system. It is also necessary to create the Moving_RelativeCS function to calculate the displacement values ​​in the three directions of X, Y, and Z. After completing this part of the translation, the rotation angle can be directly input into the function, and the Y axis direction can be determined according to the actual rotation requirements. It is worth mentioning that since the Y axis direction has continuity, when the Y axis direction is negative, it needs to be changed back to the positive direction after the rotation operation.

[0255]

[0256]

[0257]

[0258]

[0259]

[0260]

[0261] The script is as follows:

[0262]

[0263]

[0264]

[0265]

[0266]

[0267]

[0268]

[0269] Step 4: Result feedback and iterative optimization

[0270] After ANSYS software completes the parasitic inductance analysis under the new layout, it feeds the results back to MATLAB. Then, repeat steps one to three to enter the next iteration loop. This function is implemented through the circle function. By opening the blueprint script and writing a new script by comparing strings, the function of rotating any of the 18 bonding wires of the power semiconductor at any angle can be realized. Then use the "system("script.vbs")" command to run the newly written script to iterate. Through continuous iterative optimization, the goal of minimum parasitic inductance is gradually approached until the design requirements are met.

[0271] The entire process embodies an efficient cross-platform collaborative working method, combining the powerful electromagnetic field simulation capabilities of Ansys Q3D with the advantages of MATLAB in data processing and algorithm optimization, providing a new solution for the field of electromagnetic design. Through this method, researchers can optimize circuit layout more accurately and significantly improve the performance and reliability of electronic devices.

[0272] 1. Model and algorithm preparation

[0273] Fig. 9 Power semiconductor model (opened with ANSYS Q3D)

[0274] Fig.10 Preparation for interaction between ANSYS and MATLAB

[0275] 2. Run the circle function

[0276] This design is iterated 10 times. The upper MOSFET chip bonding wire (only the bonding wires that must not overlap with other bonding wires during rotation, 6 wires) move counterclockwise by 2, and the lower MOSFET chip bonding wire (12 wires) move counterclockwise by 3. After running the circle function, Fig.15 , 16As shown, the extraction of parasitic parameters of the first iteration begins.

[0277] 3. Results Analysis

[0278] After 10 iterations, the parasitic inductance data generated in the process is saved in ACLiter.tab. The parasitic inductance values ​​for each of the 10 iterations are as follows (in nH): 23.2489724983880 23.2494181170317 23.2619612881619 23.2610695565155 23.2772267075122 23.2874682288847 23.2980907281830 23.3122255214713 23.3213010685666 23.3418138606642

[0289] The generated line graph shows that the power semiconductor module has the minimum parasitic inductance in the first iteration, that is, the upper MOSFET chip bonding wire (only the bonding wires that must not overlap with other bonding wires during rotation are selected, 6 wires) move counterclockwise by 2, and the lower MOSFET chip bonding wire (12 wires) move counterclockwise by 3. The minimum parasitic inductance is 23.2489724983880nH, and when the angle gradually increases, the parasitic inductance roughly presents a monotonically increasing trend. If you need to further obtain the minimum parasitic inductance, you can actively select the bonding wire that needs to be rotated each time, and continuously refine the rotation angle until you get a better result.

[0290] With the increasing maturity of silicon carbide power devices represented by SiC MOSFET, the continuous advancement of integrated packaging technology and the continuous extension of power conversion needs, silicon carbide power modules have become an important way to develop ultra-high power density conversion equipment.

[0291] 1. New energy power generation. Under the guidance of grid parity, photovoltaic power stations are cost-sensitive applications. Improving the power density of inverters to reduce investment costs is a technical trend in power conversion in the photovoltaic field. The ANSYS-MATLAB joint simulation method developed by the present invention has the characteristics of high efficiency and accuracy in electrical parameter extraction and layout optimization. Parameters such as power density can be optimized in a directed manner through intelligent digital algorithms, which has a significant effect on reducing the investment cost of photovoltaic inverters.

[0292] 2. High-efficiency power supply. The energy routing system based on power electronic equipment can significantly improve the quality, efficiency and reliability of power supply, and can provide a variety of additional functions such as flexible power regulation, power quality control, backup power switching, etc. It is an important development direction of data center power supply system. The extensive use of power semiconductor modules is bound to increase equipment costs and land burden. Highly integrated power modules are the key to realizing the compact design of data center power supply systems.

[0293] 3. Electrified transportation. Due to its advantages in switching speed, temperature characteristics and voltage resistance, SiC power modules have gradually begun to be used in motor controllers of electric vehicles. Motor controllers are the core components of electric vehicles and have high requirements on the electrothermal characteristics of power modules, which poses a great challenge to SiC packaging. For electric vehicle applications, the requirements for motor controllers are high voltage, long life and high reliability. Correspondingly, the packaging design goals of automotive SiC power modules are: low parasitic inductance, low thermal resistance and high reliability. By optimizing the above packaging goals individually or collaboratively, the potential of SiC technology can be maximized. The ANSYS-MATLAB joint simulation method developed by the present invention can well achieve the packaging design goal of low parasitic inductance of SiC power modules through MATLAB digital intelligent algorithms. For multi-objective collaborative optimization problems, relevant algorithms (such as NSGA-II) can also be combined to achieve optimization goals.

[0294] The present invention has brought some positive results in the optimization of power semiconductor layout. Specifically, first, the present technology uses finite element analysis (FEA) to improve the accuracy and visualization of layout optimization. The layout optimization of this technology is based on ANSYS simulation. The currently disclosed optimization technologies are all based on fast simulation such as discrete circuit method (DCA). ANSYS simulation has the advantages of higher accuracy and higher visualization compared with DCA. Secondly, this technology can save a lot of manpower costs in the optimization process, because the finite element analysis (FEA) brings the problem of long time and non-fixedness, and manual control of ANSYS simulation is laborious. This technology introduces program automation processing, which liberates the time and energy of researchers. Finally, this technology is also highly portable. The core of this technology lies in the automation of ANSYS simulation. In addition to being used for layout optimization, this technology can also provide guidance for the establishment process of fast simulation models and the extraction process of a large number of circuit parameters, so it is portable and versatile.

[0295] 1. Effectively improve the accuracy and visualization of layout optimization

[0296] The layout optimization in this technology mainly focuses on the analysis of electromagnetic fields, without going deep into the level of thermodynamics or structural mechanics. Under this premise, the core task of layout optimization is transformed into the accurate extraction and analysis of line parasitic inductance. Traditionally, many technologies use discrete circuit method (DCA) as a fast simulation method to extract parasitic inductance. This method is widely used for its fast calculation speed, especially in specific occasions. It shows its irreplaceable advantages. However, ANSYS finite element simulation (FEA) provides a more accurate and intuitive analysis method, which should not be ignored when performing layout optimization.

[0297] The high accuracy of finite element simulation (FEA) can be explained from two aspects: the completeness of its mathematical model and the comprehensiveness of simulation details. First, unlike the discrete circuit method based on simplified circuit models and Kirchhoff's laws, the finite element analysis method focuses on the complete geometric layout and material properties of the circuit, and uses spatial discretization (gridding) to solve complex partial differential equations. This method enables FEA to accurately analyze the distribution of electromagnetic fields and the impact of the physical layout of the circuit and non-ideal interactions between components (such as electromagnetic coupling and signal integrity issues) on the simulation results. Secondly, from the perspective of simulation details, the discrete circuit method often ignores factors such as electromagnetic coupling and electromagnetic interference (EMI) between wires. Especially when dealing with complex three-dimensional structures, this neglect often leads to imperceptible errors, which adversely affects the simulation results. In contrast, finite element analysis comprehensively considers multiple influencing factors through precise field analysis, so its accuracy is higher.

[0298] Once the accuracy of finite element simulation has been proven, its advantages in visualization are self-evident. For example, in practical application cases, such as Fig.16 As shown in the figure, each new circuit layout optimized by the algorithm can not only show the specific parasitic inductance value, but also present the corresponding electric field distribution diagram. Such visualization tools enable designers to intuitively evaluate the current sharing characteristics of the circuit and further guide the decision-making process of optimizing the design.

[0299] 2. Save researchers’ energy and time

[0300] In the process of developing this technology, the inventor has conducted an in-depth study on the unique advantages of finite element analysis (FEA) in terms of accuracy and visualization. Although FEA excels in simulating the behavior of complex physical systems, the inventor has found that FEA is rarely widely adopted as a mainstream simulation technology in published papers and patented technologies. The main reason is that FEA simulation takes a long time and is unpredictable, which greatly limits its application efficiency in areas such as layout optimization and numerical extraction.

[0301] The reason is that FEA simulates the calculation principle of the system by subdividing complex physical systems into thousands to millions of small elements (meshes), analyzing the physical and material properties of each element and complex boundary conditions, and solving partial differential equations. Although this method is accurate, the time required for simulation and its uncertainty are affected by many factors when dealing with large and complex models. Although high-performance computing (HPC) and cloud computing technologies provide support for processing these calculations, not all research institutions have these computing resources.

[0302] Therefore, the present invention proposes a system optimization policy through the linkage of MATLAB and ANSYS to improve the automation of simulation and layout optimization, thereby significantly saving researchers' time and economic costs. The advantages of automated integration are mainly reflected in the following four aspects:

[0303] Significantly improve time efficiency: Automated programs can run continuously without human intervention, allowing simulation tasks to be started and ended at any appropriate time. For example, complex simulation tasks can be set to be automatically executed at night or on weekends, effectively avoiding daily working time and significantly reducing the overall project cycle. The application example of this technology is to set up a program and automatically execute it on weekends.

[0304] Reduce human operation errors: The automated process greatly reduces errors caused by manual operation and improves the reliability and repeatability of simulation results. When large-scale, repetitive simulations are needed, the automated script can accurately control each simulation parameter to ensure that the simulation process follows strict consistency standards.

[0305] Optimize computing resource utilization: Automation can allocate computing resources more efficiently, ensuring maximum utilization of high-performance computing resources. In addition, automation tools can monitor simulation progress and performance in real time and make timely resource adjustments to optimize computing efficiency.

[0306] Enhanced design iteration and optimization capabilities: Automated processing allows researchers to quickly test and compare multiple design configurations, accelerating the optimization iteration process. Researchers can use automated tools to adjust design parameters, run multiple simulation scenarios, and quickly obtain comparison results to identify the best design solution. This process is Fig.14 , Fig.15 , Fig.16 This is reflected in the operation of the program.

[0307] 3. Portability and versatility

[0308] Finally, it is worth emphasizing that this technique demonstrates excellent portability and wide applicability. Although this technique was originally developed for circuit layout optimization based on electromagnetic field analysis alone, its core advantage lies in the rapid extraction of circuit parameters using the linkage mechanism of MATLAB and ANSYS. The application scope of this technique is far from limited to preliminary electromagnetic field considerations, but can be widely used in various research projects related to power semiconductor layout optimization.

[0309] In the process of researching power semiconductor layout optimization, whether it is building fast simulation models or performing large-scale circuit parameter extraction, ANSYS's finite element analysis (FEA) capabilities are indispensable. FEA technology can provide deep insights and highly accurate analysis results through fine meshing and complex physical simulation. With this technology, researchers can significantly increase the speed of parameter extraction and model building through automated processes while maintaining ANSYS analysis accuracy.

[0310] More importantly, the automation of this technology not only improves work efficiency, but also optimizes resource allocation and use, allowing computing resources to be used more efficiently. Automated programs can perform complex data processing and simulation tasks without human supervision in the background, greatly reducing the need for manual operations and reducing the risk of human error.

[0311] In addition, due to the widespread use of MATLAB and ANSYS, this technology is highly portable and can be easily adapted to different research and industrial environments. Researchers can adjust and customize automation scripts according to specific application needs to make them more suitable for specific projects. This flexibility and customizability further enhances the market appeal and practical value of this technology.

[0312] The optimization process provided by the embodiment of the present invention can record the parameters of each model in the optimization process. It is only necessary to close the optimization process and only perform extraction to quickly extract data of a large number of circuits and compare it with the results of the fast simulation model or meet other requirements.

[0313] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing its layout, characterized in that: The following steps are involved: In step 1, the initial parameters are defined and the parasitic inductance is extracted. The simulation tool is used to automatically identify the circuit network and preliminarily extract the inductance value. In step 2, these simulation data are transferred to the MATLAB environment for further analysis and processing; Step 3: Re-analyze based on the optimization suggestions provided by MATLAB through automated ANSYS scripts; In step 4, feedback and iterative optimization are performed based on the reanalysis results, and the circuit layout is adjusted using genetic algorithm optimization technology to minimize parasitic inductance and improve module performance.

2. The method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing layout as claimed in claim 1, characterized in that: The initial parameter definition and parasitic inductance extraction method are as follows: (1) Design basic circuit layout; (2) Determine the material properties of the power module; (3) Arrange circuits and automatically identify networks; First, select the excitation source SOURCE and ground SINK. The specific meaning of each port has been determined during the circuit diagram making process; Through ANSYS Q3D's automatic network recognition function, the unique electrical path of the model is determined and displayed; (4) Extract parasitic inductance; The circuit is simulated and the resistance and inductance parameters of the circuit are extracted.

3. The method for efficiently extracting parasitic inductance parameters and optimizing layout of a power semiconductor module as claimed in claim 2, characterized in that: The basic circuit layout of the design: 1) Package parasitic inductance calculation model - accumulation method; The inductance of a rectangular conductor is: Where, L σ is the inductance, H; l R 、b R 、h R are the length, width and thickness of the conductor, mm; μ0=4π×10 -7 H / m is the vacuum permeability; The inductance of a long straight wire is: In the formula, l L and d L are the length and diameter of the wire, mm; if d L < <l L , then the inductance of a long straight wire can be expressed as: For the case of multiple bonding wires in parallel, the parasitic inductance presented by a cluster of bonding wires is equivalent to: Where N is the number of bonding wires; 2) Calculation model of parasitic inductance of rectangular loop package - magnetic field cancellation method; Inductance λ σ , which is derived as follows: The closed rectangular loop inductance is: In the formula, a C and b C are the length and width of the rectangle, d C is the diameter of the conductor, mm; if d C < C and b C , which can be simplified to:​ In the formula, C C =2(a C +b C ) and S C =a C b C are the perimeter and area of ​​the rectangular conductor, respectively; therefore, the inductance of the open rectangular loop is: Open rectangular loop inductance λ σ It can be defined as: λ σ =C C lnS C -b C [ln(2b C )-1]。 4. The method for efficiently extracting parasitic inductance parameters and optimizing layout of a power semiconductor module as claimed in claim 2, characterized in that: Determine the material properties of the power module: The preliminary model generated by SOLIDWORKS is transferred to ANSYS, and the materials of each part of the circuit are determined during the simulation process. The determined parts are divided into bonding wires, DBCs, power chips and bus bars.

5. The method for efficiently extracting parasitic inductance parameters and optimizing layout of a power semiconductor module according to claim 1, characterized in that: The simulation data transfer: After completing the extraction of parasitic inductance, the simulation data in ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report.

6. The method for efficiently extracting parasitic inductance parameters and optimizing layout of a power semiconductor module according to claim 1, characterized in that: The ANSYS script automates and reanalyzes: According to the new layout scheme provided by MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis.

7. A system for efficiently extracting and optimizing the layout of parasitic inductance parameters of a power semiconductor module, which implements the method for efficiently extracting and optimizing the layout of parasitic inductance parameters of a power semiconductor module as claimed in any one of claims 1 to 6, characterized in that: The efficient extraction and layout optimization system of parasitic inductance parameters of the power semiconductor module includes: Extraction module, used for initial parameter definition and parasitic inductance extraction; Data transfer module, used for simulating data transfer; Analysis module for ANSYS script automation and reanalysis; The feedback module is used to feed back the results of the parasitic inductance analysis under the new layout after completing it through ANSYS software to MATLAB.

8. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method for efficient extraction and layout optimization of parasitic inductance parameters of a power semiconductor module as described in any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the method for efficiently extracting parasitic inductance parameters of a power semiconductor module and optimizing layout as described in any one of claims 1 to 6.

10. An information data processing terminal, characterized in that: The information data processing terminal is used to implement the efficient extraction and layout optimization system of parasitic inductance parameters of the power semiconductor module as described in claim 7.

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