Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps that an active structure is formed on a semiconductor substrate, the active structure comprises a first part and a second part, and the second part is close to the semiconductor substrate relative to the first part; based on the first part, forming a front vertical stacked transistor, the front vertical stacked transistor comprising: a first transistor and a second transistor, the first transistor and the second transistor having different polarities, the first transistor and the second transistor being self-aligned in a first direction, the first direction being a direction perpendicular to the semiconductor substrate; reversing and removing the semiconductor substrate; on the basis of the second part, a reverse side vertical stacking transistor is formed, the reverse side vertical stacking transistor comprises a third transistor and a fourth transistor, the polarities of the third transistor and the fourth transistor are different, and the third transistor and the fourth transistor are self-aligned in the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, active regions of upper and lower layers of transistors of the same source are formed by etching, and stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, there is still room for optimization of transistor integration, so new schemes are needed to further improve the integration performance of transistors. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device to increase the integration density of the transistor and further enhance the integration performance of the transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: etching on a semiconductor substrate once to form an active structure, the active structure comprising a first part and a second part, the second part being closer to the semiconductor substrate relative to the first part; based on the first part, forming a front vertical stacked transistor, the front vertical stacked transistor comprising: a first transistor and a second transistor, the first transistor and the second transistor having different polarities, the first transistor and the second transistor being self-aligned in a first direction, and the first direction being a direction perpendicular to the semiconductor substrate; flipping the semiconductor substrate and removing it; based on the second part, forming a back vertical stacked transistor, the back vertical stacked transistor comprising: a third transistor and a fourth transistor, the third transistor and the fourth transistor having different polarities, the third transistor and the fourth transistor being self-aligned in the first direction; wherein the front vertical stacked transistor and the back vertical stacked transistor are arranged back to back, and the front vertical stacked transistor and the back vertical stacked transistor are self-aligned in the first direction.

[0006] In some possible embodiments, the first part includes a first sacrificial layer, and the first sacrificial layer is located in the middle part of the first part; based on the first part, a front vertical stacked transistor is formed, including: based on the first part, at least three first dummy gate structures surrounding the first part and dummy gate sidewalls covering the first dummy gate structure are formed, and the at least three first dummy gate structures are arranged along a second direction, and the second direction is perpendicular to the first direction; using the first dummy gate structure as a hard mask, etching the first part located in the source and drain region to form a first trench, wherein the area between the dummy gate sidewalls of two adjacent first dummy gate structures is the source and drain region, and the area where the first dummy gate structure and its dummy gate sidewall are located is the gate region; forming a front source and drain structure of the front vertical stacked transistor in the first trench, the front source and drain structure including a first source and drain structure of the first transistor, a front source and drain isolation structure, and a second source and drain structure of the second transistor; removing the first sacrificial layer and the first dummy gate structure in the gate region, and forming a front gate structure of the front vertical stacked transistor at the position where the first sacrificial layer and the first dummy gate structure are removed, the front gate structure including a first gate structure of the first transistor and a second gate structure of the second transistor, and the junction of the first gate structure and the second gate structure is located at the position where the first sacrificial layer is removed.

[0007] In some possible embodiments, the first part also includes: a third part and a fourth part, the first sacrificial layer is located between the third part and the fourth part, and the third part is closer to the semiconductor substrate than the fourth part; using the first pseudo gate structure as a hard mask, etching the first part located in the source and drain region to form a first trench, including: using the first pseudo gate structure as a hard mask, etching the fourth part and the first sacrificial layer located in the source and drain region to expose the fourth part and the first sacrificial layer in the gate region and form a first initial trench; forming a first barrier layer on the side walls of the fourth part and the first sacrificial layer in the gate region; etching the third part located below the first initial trench to expose the third part in the gate region and form a first trench.

[0008] In some possible embodiments, the first sacrificial layer and the first dummy gate structure in the gate region are removed, and a front gate structure of a front vertically stacked transistor is formed at the position where the first sacrificial layer and the first dummy gate structure are removed, including: removing the first dummy gate structure to expose the third part, the first sacrificial layer and the fourth part in the gate region; removing the first sacrificial layer in the gate region by an etching process to expose the first surface of the third part and the second surface of the fourth part, the first surface of the third part being the surface of the third part away from the semiconductor substrate, and the second surface of the fourth part being the surface of the fourth part close to the semiconductor substrate; forming a first gate structure surrounding the third part; forming a second gate structure surrounding the fourth part, and the junction of the first gate structure and the second gate structure is located between the first surface and the second surface.

[0009] In some possible embodiments, the first portion also includes a second sacrificial layer, which is closer to the semiconductor substrate than the third portion; etching the third portion located below the first initial trench to expose the third portion in the gate area and form a first trench, and also includes: etching the third portion and the second sacrificial layer located below the first initial trench to expose the third portion and the second sacrificial layer in the gate area; forming a second blocking layer on the side wall of the second sacrificial layer in the gate area, and forming a first trench.

[0010] In some possible embodiments, the first sacrificial layer and the first dummy gate structure in the gate region are removed, and a front gate structure of a front vertically stacked transistor is formed at the position where the first sacrificial layer and the first dummy gate structure are removed, and the method further includes: removing the first dummy gate structure to expose the third part, the first sacrificial layer, the fourth part, and the second sacrificial layer in the gate region; removing the first sacrificial layer and the second sacrificial layer in the gate region by an etching process to expose the first surface of the third part, the third surface of the third part, and the second surface of the fourth part, wherein the first surface of the third part is a surface of the third part away from the semiconductor substrate, the third surface of the third part is a surface of the third part close to the semiconductor substrate, and the second surface of the fourth part is a surface of the fourth part close to the semiconductor substrate; forming a first gate structure surrounding the third part; and forming a second gate structure surrounding the fourth part.

[0011] In some possible embodiments, a front source-drain structure of a front vertically stacked transistor is formed in a first trench, including: forming a first source-drain structure in the first trench by an epitaxial growth process based on a third portion in the gate region, the first source-drain structure being opposite to the third portion; removing the first barrier layer to expose a fourth portion in the gate region; forming a front source-drain isolation structure on the first source-drain structure, the front source-drain isolation structure being opposite to the first sacrificial layer; and forming a second source-drain structure in the first trench by an epitaxial growth process based on the exposed fourth portion in the gate region, the second source-drain structure being opposite to the fourth portion, above the front source-drain isolation structure.

[0012] In some possible embodiments, before forming a first barrier layer on the fourth portion in the gate region and on the side walls of the first sacrificial layer, the method further includes: using an etching process to laterally etch the side walls of the first sacrificial layer in the exposed gate region to form a first groove; filling the first groove with an insulating material to form a first pseudo gate side wall of the first transistor, the first pseudo gate side wall completely covering the side wall of the first sacrificial layer in the gate region, and the pseudo gate side wall of the first pseudo gate structure is used to form a second pseudo gate side wall of the second transistor.

[0013] In some possible embodiments, after forming a first source-drain structure in the first trench by an epitaxial growth process, the method further includes: depositing a metal material on the first source-drain structure to form a first source-drain metal; forming a front source-drain isolation structure on the first source-drain structure, including: depositing an insulating material on the first source-drain metal to form a front source-drain isolation structure, the first source-drain metal and the front source-drain isolation structure being opposite to the first sacrificial layer together; after forming a second source-drain structure in the first trench by an epitaxial growth process, the method further includes: depositing a metal material on the second source-drain structure to form a second source-drain metal.

[0014] In some possible implementations, the second portion includes a third sacrificial layer, and the third sacrificial layer is located in the middle of the second portion; based on the second portion, a reverse vertical stacked transistor is formed, including: based on the second portion, at least three second dummy gate structures surrounding the second portion and dummy gate sidewalls covering the second dummy gate structures are formed, and the at least three second dummy gate structures are arranged along the second direction; using the second dummy gate structure as a hard mask, etching the second portion located in the source and drain region to form a second trench, wherein the region between the dummy gate sidewalls of two adjacent second dummy gate structures is the source and drain region, and the region where the first dummy gate structure and its dummy gate sidewall are located is the source and drain region. The domain is the gate region; a reverse source-drain structure of a reverse vertically stacked transistor is formed in the second trench, the reverse source-drain structure includes a third source-drain structure of a third transistor, a reverse source-drain isolation structure and a fourth source-drain structure of a fourth transistor; the third sacrificial layer and the second dummy gate structure in the gate region are removed, and a reverse gate structure of a reverse vertically stacked transistor is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, the reverse gate structure includes a third gate structure of the third transistor and a fourth gate structure of the fourth transistor, and the junction of the third gate structure and the fourth gate structure is located at the position where the third sacrificial layer is removed.

[0015] In some possible embodiments, the second part also includes: a fifth part and a sixth part, the third sacrificial layer is located between the fifth part and the sixth part, and the fifth part is closer to the semiconductor substrate than the sixth part; using the second pseudo gate structure as a hard mask, etching the second part located in the source and drain area to form a second trench, including: using the second pseudo gate structure as a hard mask, etching the sixth part and the third sacrificial layer located in the source and drain area to expose the sixth part and the third sacrificial layer in the gate area and form a second initial trench; forming a third barrier layer on the side walls of the sixth part and the third sacrificial layer in the gate area; etching the fifth part located below the second initial trench to expose the fifth part in the gate area and form a second trench.

[0016] In some possible embodiments, the third sacrificial layer and the second dummy gate structure in the gate region are removed, and a reverse gate structure of a reverse vertically stacked transistor is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, including: removing the second dummy gate structure to expose the fifth portion, the third sacrificial layer and the sixth portion in the gate region; removing the third sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion and the fifth surface of the sixth portion, the fourth surface of the fifth portion being the surface of the fifth portion away from the semiconductor substrate, and the fifth surface of the sixth portion being the surface of the sixth portion close to the semiconductor substrate; forming a third gate structure surrounding the fifth portion; forming a fourth gate structure surrounding the sixth portion, and the junction of the third gate structure and the fourth gate structure is located between the fourth surface and the fifth surface.

[0017] In some possible embodiments, the second portion also includes a fourth sacrificial layer, which is closer to the semiconductor substrate than the fifth portion; etching the fifth portion located below the second initial trench to expose the fifth portion in the gate area and form a second trench, and also includes: etching the fifth portion and the fourth sacrificial layer located below the second initial trench to expose the fifth portion and the fourth sacrificial layer in the gate area; forming a fourth barrier layer on the side wall of the fourth sacrificial layer in the gate area, and forming a second trench.

[0018] In some possible embodiments, the third sacrificial layer and the second dummy gate structure in the gate region are removed, and a reverse gate structure of a reverse vertically stacked transistor is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, and the method also includes: removing the second dummy gate structure to expose the fifth portion, the third sacrificial layer, the sixth portion and the fourth sacrificial layer in the gate region; removing the third sacrificial layer and the fourth sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion, the sixth surface of the fifth portion and the fifth surface of the sixth portion, the fourth surface of the fifth portion being the surface of the fifth portion away from the semiconductor substrate, the sixth surface of the fifth portion being the surface of the fifth portion close to the semiconductor substrate, and the fifth surface of the sixth portion being the surface of the sixth portion close to the semiconductor substrate; forming a third gate structure surrounding the fifth portion; and forming a fourth gate structure surrounding the sixth portion.

[0019] In some possible embodiments, it is characterized in that a reverse source-drain structure of a reverse vertically stacked transistor is formed in the second trench, including: based on the fifth portion in the gate region, a third source-drain structure is formed in the second trench by an epitaxial growth process, and the third source-drain structure is opposite to the fifth portion; the third barrier layer is removed to expose the sixth portion in the gate region; a reverse source-drain isolation structure is formed on the third source-drain structure, and the reverse source-drain isolation structure is opposite to the third sacrificial layer; and above the reverse source-drain isolation structure, based on the exposed sixth portion in the gate region, a fourth source-drain structure is formed in the second trench by an epitaxial growth process, and the fourth source-drain structure is opposite to the sixth portion.

[0020] In some possible embodiments, before forming a third barrier layer on the sixth portion and the side wall of the third sacrificial layer in the gate region, the method also includes: using an etching process to laterally etch the side wall of the third sacrificial layer in the exposed gate region to form a second groove; filling the second groove with insulating material to form a third pseudo gate side wall of the third transistor, the third pseudo gate side wall completely covers the side wall of the third sacrificial layer in the gate region, and the pseudo gate side wall of the second pseudo gate structure is used to form a fourth pseudo gate side wall of the fourth transistor.

[0021] In some possible embodiments, after forming a third source-drain structure in the second trench by an epitaxial growth process, the method further includes: depositing a metal material on the third source-drain structure to form a third source-drain metal; forming a reverse source-drain isolation structure on the third source-drain structure, including: depositing an insulating material on the third source-drain metal to form a reverse source-drain isolation structure, the third source-drain metal and the reverse source-drain isolation structure being jointly opposite to the third sacrificial layer; after forming a fourth source-drain structure in the second trench by an epitaxial growth process, the method further includes: depositing a metal material on the fourth source-drain structure to form a fourth source-drain metal.

[0022] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: a front vertically stacked transistor, including: a first transistor and a second transistor, the first transistor and the second transistor have different polarities, and the first transistor and the second transistor are self-aligned in a first direction, and the first direction is a direction perpendicular to the semiconductor substrate; a back vertically stacked transistor, including: a third transistor and a fourth transistor, the third transistor and the fourth transistor have different polarities, and the third transistor and the fourth transistor are self-aligned in the first direction; wherein the front vertically stacked transistor and the back vertically stacked transistor are arranged back to back, and the front vertically stacked transistor and the back vertically stacked transistor are self-aligned in the first direction.

[0023] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0024] In an embodiment of the present application, an active structure having a certain depth is formed on a semiconductor substrate by etching once, so that the active areas of the vertically stacked transistors on the front and the vertically stacked transistors on the back can be self-aligned. Subsequently, a first transistor and a second transistor with different polarities can be prepared based on the first part of the active structure, and the semiconductor substrate is etched after flipping, so that a third transistor and a fourth transistor with different polarities can be prepared based on the second part of the active structure. It can be seen that by forming a pair of stacked transistors on the front side of the wafer and another pair of stacked transistors on the back side of the wafer, more transistors can be prepared using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0027] Figure 1 is a top view of a stacked transistor according to an embodiment of the present application;

[0028] Figure 2 A schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application;

[0029] Figures 3 to 21 It is a schematic diagram of a preparation process of a stacked transistor according to an embodiment of the present application.

[0030] Figures 10, stacked transistor; 101, front vertical stacked transistor; 1011, front metal interconnect layer; 102, back vertical stacked transistor; 1021, back metal interconnect layer; 11, first transistor; 12, second transistor; 13, third transistor; 14, fourth transistor; 111, first pseudo gate sidewall; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 121, second pseudo gate sidewall; 122 , second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 127, front dielectric layer; 131, third pseudo-gate sidewall; 132, third source-drain structure; 133, third interlayer dielectric layer; 134, third gate structure; 135, third source-drain metal; 141, fourth pseudo-gate sidewall; 142, fourth source-drain structure; 143, fourth interlayer dielectric layer; 144, fourth gate structure; 145, fourth source-drain metal; 147, reverse dielectric layer;

[0031] 20. Semiconductor substrate; 21. First part; 211. First sacrificial layer; 212. Third part; 213. Fourth part; 214. Second sacrificial layer; 22. Second part; 222. Fifth part; 223. Sixth part; 23. Stacked structure; 24. Isolation layer; 25. Shallow trench isolation structure; 26. First pseudo-gate structure; 27. First trench; 28. Front source-drain isolation structure; 29. ​​First initial trench; 30. First barrier layer; 31. Second barrier layer; 32. Insulation layer; 33. Carrier wafer; 34. Back source-drain isolation structure; 35. Fourth barrier layer. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0033] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0034] In one embodiment, there are two schemes for manufacturing processes of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0035] The sequential solution is based on wafer bonding and is processed layer by layer. However, thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. The main challenges faced by the sequential stacking transistor process include: (1) preparation of high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) alignment errors between the upper and lower transistors, which requires extremely high lithography accuracy.

[0036] In the monolithic stacked transistor technology, wafer bonding technology is not used. Instead, N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) are made on the same substrate, which also determines that the transistors on the same layer must be of the same type, that is, NFET or PFET. In addition, the upper and lower layers of transistors are strictly in the same plane space, and there is no alignment deviation. Obviously, the advantage of monolithic stacked transistors is higher integration density. However, its disadvantages are also obvious: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and it must rely on two layers of transistors to form a basic CMOS circuit, which has poor design flexibility.

[0037] In order to solve the technical problems of the above two solutions, a "self-aligned flip transistor" solution is proposed. This "self-aligned flip transistor" solution forms the active area of ​​the upper and lower layers of the same source transistors by etching, and realizes the production of stacked transistors on the front and back of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions. However, the preparation process of the self-aligned flip transistor still has room for optimization to further improve the integrated performance of the stacked transistor.

[0038] The present application embodiment provides a stacked transistor. Figure 1 FIG. 1 is a top view of a stacked transistor according to an embodiment of the present application, see Figure 1 As shown, the top view only shows the fin structure, gate structure and source-drain structure of the stacked transistor 10. It is understandable that the structure of the fin structure may be different based on the type of the stacked transistor.

[0039] Exemplarily, when the stacked transistor 10 is a fin field effect transistor, the fin structure can be formed by depositing a single semiconductor material. When the stacked transistor 10 is a gate-all-around nanosheet (GAANanosheet), the fin structure can be formed by alternately depositing a semiconductor material and a sacrificial layer material; for example, it can be formed by alternately depositing a silicon layer and a silicon germanium layer. This embodiment of the present application does not specifically limit this.

[0040] Figure 2 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application, see Figure 2 As shown, the method for preparing a stacked transistor may include:

[0041] S201: etching once to form an active structure on a semiconductor substrate, wherein the active structure includes a first portion and a second portion, and the second portion is closer to the semiconductor substrate than the first portion;

[0042] S202: Based on the first part, a front vertical stacked transistor is formed, wherein the front vertical stacked transistor includes: a first transistor and a second transistor, wherein the first transistor and the second transistor have different polarities, and the first transistor and the second transistor are self-aligned in a first direction, wherein the first direction is a direction perpendicular to the semiconductor substrate;

[0043] S203: flipping the wafer and removing the semiconductor substrate;

[0044] S204: Based on the second part, a reverse vertical stacked transistor is formed, wherein the reverse vertical stacked transistor includes: a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor have different polarities, and the third transistor and the fourth transistor are self-aligned in a first direction;

[0045] The front vertical stacked transistor and the back vertical stacked transistor are arranged back to back, and the front vertical stacked transistor and the back vertical stacked transistor are self-aligned in a first direction.

[0046] It should be noted that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0047] It can be understood that by forming an active structure with a certain depth on the semiconductor substrate through a single etching, the active areas of the vertically stacked transistors on the front and the vertically stacked transistors on the back can be self-aligned. Subsequently, a first transistor and a second transistor with different polarities can be prepared based on the first part of the active structure, and the semiconductor substrate can be etched after flipping, so that a third transistor and a fourth transistor with different polarities can be prepared based on the second part of the active structure. It can be seen that by forming a pair of stacked transistors on the front of the wafer and another pair of stacked transistors on the back of the wafer, more transistors can be prepared using the front and back of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors.

[0048] Figures 3 to 21FIG. 1 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 21 (a) shows the Figure 1 The cross-sectional view along the dashed line AA'. Figures 3 to 21 (b) shows the Figure 1 The cross-sectional view along the dotted line BB', Figures 3 to 21 (c) shows the Figure 1 The cross-sectional view along the dotted line CC' Figures 1 to 21 The method for preparing the stacked transistor provided in the embodiment of the present application and the prepared stacked transistor are exemplarily described.

[0049] In step S201: see Figure 4 As shown, an active structure is formed on the semiconductor substrate 20 by etching once.

[0050] It is understandable that material layer deposition, epitaxial growth and other processes may be performed on the semiconductor substrate 20 to form a stacked structure 23 on the semiconductor substrate 20, such as Figure 3 Subsequently, a single etching process may be used to etch the stacked structure 23 to form an active structure on the semiconductor substrate 20 .

[0051] Here, the stacked structure 23 includes sacrificial layers and supporting layers stacked alternately in sequence. The materials used for the sacrificial layers and supporting layers can be selected according to actual needs, and the embodiments of the present application do not specifically limit this. It should be noted that the supporting layer can be used to form an active structure.

[0052] In one embodiment, the stacked structure 23 may be formed by alternately depositing silicon material and silicon germanium material.

[0053] It can be understood that the active structure includes a first portion 21 and a second portion 22. The first portion 21 and the second portion 22 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20), and the second portion 22 is closer to the semiconductor substrate 20 than the first portion 21.

[0054] It can be understood that the first part 21 of the active structure is used in a subsequent step to form the active areas of the first transistor 11 and the second transistor 12 in the front vertical stacked transistor 101; the second part 22 of the active structure is used to form the active areas of the third transistor 13 and the fourth transistor 14 in the back vertical stacked transistor 102.

[0055] It should be noted that the front vertical stacked transistor 101 is formed based on the front side of the semiconductor substrate 20. After the stacked transistor 10 is prepared, the front vertical stacked transistor 101 is located at the bottom of the stacked transistor 10. The back vertical stacked transistor 102 is opposite to the front vertical stacked transistor 101.

[0056] It should be noted that if Figures 3 to 21 As shown in FIG. 1 , all transistors in the stacked transistor 10 shown in the figure are all-around gate transistors. Then, the stacked structure 23 can be as follows Figure 3 As shown in , it is formed by alternately depositing silicon material and silicon germanium material.

[0057] In one embodiment, the type of transistor in the stacked transistor 10 may be a fin field effect transistor, or other types of transistors, which are not specifically limited in the embodiment of the present application.

[0058] In some embodiments, see Figure 4 As shown, an isolation layer 24 can be formed between the first portion 21 of the active structure and the second portion 22 of the active structure, thereby electrically isolating the first portion 21 of the active structure and the second portion 22 of the active structure, thereby avoiding current interference between the circuit of the front vertically stacked transistor 101 and the circuit of the back vertically stacked transistor 102.

[0059] In one embodiment, the isolation layer 24 may be a buried oxide layer or a dielectric layer.

[0060] Here, the process of forming the buried oxide layer or the dielectric layer can be set according to actual needs, and the embodiments of the present application do not make specific limitations on this.

[0061] In one embodiment, the isolation layer 24 may be an ion implantation layer.

[0062] Here, the process of forming the ion implantation layer can be set according to actual needs, and the embodiment of the present application does not make any specific limitation on this.

[0063] It is understandable that when the first part 21 of the active structure and the second part 22 of the active structure are formed by photolithography, a larger etching depth can be used. For example, the height of the first part 21 of the active structure and the second part 22 of the active structure obtained by etching can realize the formation of four transistors in the first direction. Of course, the height of the active structure can also be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0064] It should be noted that the steps of the photolithography process may include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove a material layer corresponding to the portion of the photoresist material, etc.

[0065] In some embodiments, see Figure 5As shown, after the active structure is formed, an oxide material may be deposited on the semiconductor substrate 20 to form a shallow trench isolation (STI) structure 25 , wherein the STI structure encapsulates the second portion 22 of the active structure and exposes the first portion 21 of the active structure.

[0066] The oxide material forming the shallow trench isolation structure 25 may be silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0067] In one embodiment, the shallow trench isolation structure 25 may wrap the second portion 22 of the active structure and the isolation layer 24 , exposing the first portion 21 of the active structure.

[0068] In step S202: see Fig.17 As shown, based on the first portion 21 , a front-side vertically stacked transistor 101 is formed.

[0069] The front vertically stacked transistor 101 includes: a first transistor 11 and a second transistor 12 , the first transistor 11 and the second transistor 12 have different polarities, and the first transistor 11 and the second transistor 12 are self-aligned in a first direction.

[0070] It can be understood that the first transistor 11 and the second transistor 12 can be formed based on the first part 21 of the active structure. The first transistor 11 and the second transistor 12 have complementary polarities and are stacked along the first direction. At the same time, the front vertical stacked transistor 101 and the back vertical stacked transistor 102 are also stacked along the first direction, thereby greatly improving the integration of the stacked transistor 10 in the first direction.

[0071] In one embodiment, when the first transistor 11 is a P-type (P-channel) field effect transistor, the second transistor 12 may be an N-type (N-channel) field effect transistor; when the first transistor 11 is an N-type field effect transistor, the second transistor 12 may be a P-type field effect transistor.

[0072] It should be noted that the step of forming the front vertically stacked transistor 101 can be selected according to actual needs, and the embodiment of the present application does not specifically limit this.

[0073] Exemplarily, the front vertically stacked transistor 101 may be formed by a monolithic solution or a sequential solution in a semiconductor manufacturing process.

[0074] In one embodiment, the first transistor 11 may be formed first, and then the second transistor 12 may be formed. The first transistor 11 is closer to the semiconductor substrate 20 than the second transistor 12 .

[0075] In some embodiments, a first sacrificial layer 211 is formed in the middle of the first portion 21 of the active structure. With the first sacrificial layer 211 as the boundary, a portion of the first portion 21 closer to the semiconductor substrate 20 than the first sacrificial layer 211 is used to form the first transistor 11, and a portion of the first portion 21 farther from the semiconductor substrate 20 than the first sacrificial layer 211 is used to form the second transistor 12. Then, based on the first portion 21, a front vertical stacked transistor 101 is formed, including: based on the first portion 21, at least three first dummy gate structures 26 surrounding the first portion 21 and dummy gate sidewalls covering the first dummy gate structures 26 are formed. With the first dummy gate structure 26 as a hard mask, the first portion 21 located in the source and drain region is etched to form a first trench 27. A front source and drain structure of the front vertical stacked transistor 101 is formed in the first trench 27. The first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertical stacked transistor 101 is formed at the position where the first sacrificial layer 211 and the first dummy gate structure 26 are removed.

[0076] It can be understood that after the active structure is formed by executing step S201, the second portion 22 of the active structure can be wrapped by the shallow trench isolation structure 25, and the first portion 21 of the active structure can be exposed outside the shallow trench isolation structure 25. Subsequently, based on the exposed first portion 21 of the active structure, a dummy gate material such as polysilicon and amorphous silicon can be deposited to form at least three first dummy gate structures 26 surrounding the first portion 21 of the active structure. A sidewall material can also be deposited on the sidewalls of the first dummy gate structure to form a dummy gate sidewall of the first dummy gate structure 26.

[0077] Among them, see Figure 6 As shown, at least three first dummy gate structures 26 are arranged along the second direction, and the second direction is perpendicular to the first direction. The second direction can be understood as the extension direction of the active structure (fin structure). Among them, in the extension direction of the active structure, the area between the dummy gate sidewalls of two adjacent first dummy gate structures 26 is the source and drain area, and the area where the first dummy gate structure 26 and its dummy gate sidewall are located is the gate area.

[0078] It is understood that after forming the first dummy gate structure 26, the first portion 21 located in the source / drain region can be etched using the first dummy gate structure 26 as a hard mask to form a first trench 27 in the source / drain region, see Figures 6 to 9 Subsequently, a front source-drain structure of the front vertical stacked transistor 101 may be formed in the first trench 27 by epitaxial growth or deposition doping or other processes, see Figures 10 to 14 shown.

[0079] The front source-drain structure includes the first source-drain structure 112 of the first transistor 11, the front source-drain isolation structure and the second source-drain structure 122 of the second transistor 12. The front source-drain isolation structure 28 is used to electrically isolate the first source-drain structure 112 from the second source-drain structure 122.

[0080] In one embodiment, see Figures 7 to 14 As shown, a first source-drain structure 112 may be formed first in the first trench 27 near the semiconductor substrate 20 , and then a front source-drain isolation structure 28 may be formed, and then a second source-drain structure 122 may be formed first in the first trench away from the semiconductor substrate 20 .

[0081] It is understood that after forming the front source-drain structure of the front vertical stacked transistor 101, the first dummy gate structure 26 and the first sacrificial layer 211 can be removed to achieve that only the active structure is retained in the gate region. Subsequently, a gate material is deposited at the position where the first dummy gate structure 26 and the first sacrificial layer 211 are removed to form the front gate structure of the front vertical stacked transistor 101, see Fig.15 shown.

[0082] The front gate structure includes a first gate structure 114 of the first transistor 11 and a second gate structure 124 of the second transistor 12, and the junction of the first gate structure 114 and the second gate structure 124 is located at the position where the first sacrificial layer 211 is removed. It can be understood that the first sacrificial layer 211 separates the first part 21 in the gate region into two parts, so that the separated first part 21 can simultaneously form the active area of ​​the first transistor 11 and the second transistor 12, and the junction of the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 can be located at the position where the first part 21 is separated, that is, at the position of the first sacrificial layer 211.

[0083] It can be understood that by forming the front source-drain structure and the front gate structure of the front vertical stacked transistor 101 , the front-end process of the front vertical stacked transistor 101 can be completed.

[0084] In some embodiments, the first portion 21 of the active structure further includes: a third portion 212 and a fourth portion 213, the first sacrificial layer 211 is located between the third portion 212 and the fourth portion 213, and the third portion 212 is closer to the semiconductor substrate 20 than the fourth portion 213. Then, using the first dummy gate structure 26 as a hard mask, etching the first portion 21 located in the source and drain regions to form the first trench 27 may include: using the first dummy gate structure 26 as a hard mask, etching the fourth portion 213 and the first sacrificial layer 211 located in the source and drain regions to expose the fourth portion 213 and the first sacrificial layer 211 in the gate region, and forming a first initial trench 29; forming a first barrier layer 30 on the sidewalls of the fourth portion 213 and the first sacrificial layer 211 in the gate region; etching the third portion 212 located below the first initial trench 29 to expose the third portion 212 in the gate region, and forming the first trench 27.

[0085] It can be understood that by etching the fourth portion 213 and the first sacrificial layer 211 in the source and drain regions, the fourth portion 213 and the first sacrificial layer 211 in the gate region can be exposed to form a first initial trench 29. Here, the bottom of the first initial trench 29 can be formed by the third portion 212 in the source and drain regions, and the groove wall of the first initial trench 29 can be formed by the fourth portion 213 and the first sacrificial layer 211 in the gate region. Subsequently, a first barrier layer 30 can be formed on the sidewalls of the fourth portion 213 and the first sacrificial layer 211 in the exposed gate region to isolate the fourth portion 213 and the first sacrificial layer 211 from the first initial trench 29. Subsequently, the third portion 212 located below the first initial trench 29 is etched to expose the third portion 212 in the gate region to obtain the first trench 27 required for subsequent steps, see Figures 7 and 8 .

[0086] It is understandable that in subsequent steps, the first source-drain structure 112 can be formed in the first trench 27 (in the source-drain region) through an epitaxial growth process based on the third portion 212 in the gate region. Here, when forming the first trench 27, a first barrier layer 30 covering the fourth portion 213 and the first sacrificial layer 211 is formed. The first barrier layer 30 can effectively prevent the fourth portion 213 from also epitaxially growing an active structure, thereby ensuring the orderly preparation of the front vertical stacked transistor 101.

[0087] In one embodiment, the material forming the first barrier layer 30 may have a high selective etching property with the material forming the third portion 212 , so that the third portion 212 may be removed by a selective etching process.

[0088] For example, the third portion 212 may be formed of a silicon material, and the first barrier layer 30 may be formed of a silicon nitride material.

[0089] In some embodiments, the first portion 21 of the active structure further includes: a second sacrificial layer 214, and the second sacrificial layer 214 is closer to the semiconductor substrate 20 than the third portion 212. Then, etching the third portion 212 below the first initial trench 29 to expose the third portion 212 in the gate region and form the first trench 27, further includes: etching the third portion 212 and the second sacrificial layer 214 below the first initial trench 29 to expose the third portion 212 and the second sacrificial layer 214 in the gate region; forming a second barrier layer 31 on the sidewall of the second sacrificial layer 214 in the gate region, and forming the first trench 27.

[0090] It is understood that after forming the first barrier layer 30 covering the fourth portion 213 in the gate region and the sidewall of the first sacrificial layer 211, the third portion 212 and the second sacrificial layer 214 located below the first initial trench 29 may be etched to expose the third portion 212 and the second sacrificial layer 214 in the gate region. Subsequently, a second barrier layer 31 may be formed on the sidewall of the second sacrificial layer 214 in the gate region, thereby obtaining the first trench 27 required for subsequent steps, see Figures 7 to 9 .

[0091] It can be understood that the second barrier layer 31 has the same function as the first barrier layer 30 , and both are used to ensure that the first source-drain structure 112 can be epitaxially generated based on the third portion 212 .

[0092] It is understandable that, compared with the solution without the second sacrificial layer 214 , the solution with the second sacrificial layer 214 can completely expose the third portion 212 in the gate region in the subsequent step of forming the gate structure, thereby facilitating the formation of a ring gate structure.

[0093] In one embodiment, the material forming the second barrier layer 31 may be a dummy gate material, thereby directly forming a dummy gate sidewall between the gate region and the source / drain region, thereby achieving electrical isolation between the gate structure and the source / drain structure of the front vertically stacked transistor 101 .

[0094] In some embodiments, before forming the first barrier layer 30 on the fourth portion 213 in the gate region and the sidewall of the first sacrificial layer 211, the method further includes: using an etching process to laterally etch the sidewall of the first sacrificial layer 211 in the exposed gate region to form a first groove. Filling the first groove with an insulating material to form a first dummy gate spacer 111 of the first transistor 11.

[0095] It is understood that before forming the first barrier layer 30, an etching process may be used to laterally etch the sidewall of the first sacrificial layer 211 in the exposed gate region to form a first groove opening toward the source and drain region. Subsequently, an insulating material may be filled in the first groove to form a first dummy gate spacer 111 of the first transistor 11, see Figure 7 .

[0096] Here, the depth of the first groove can be selected according to actual needs, and is not specifically limited in the embodiments of the present application.

[0097] It should be noted that after the insulating material is deposited in the first groove, it can be used to form a sidewall structure for isolating the gate structure from the source and drain structure. After the insulating material is filled in the first groove, at least a first dummy gate sidewall of the first transistor 11 can be formed, and the dummy gate sidewall of the first dummy gate structure 26 is used to form a second dummy gate sidewall 121 of the second transistor 12.

[0098] In some embodiments, after the first groove is filled with insulating material, a portion of the first groove forms a first dummy gate spacer of the first transistor 11 , and another portion of the first groove forms a portion of a second dummy gate spacer 121 of the second transistor 12 .

[0099] In some possible implementations, after forming the first trench 27 by adopting any of the above embodiments, a front source-drain structure of the front vertical stacked transistor 101 may be formed in the first trench 27. Specifically, the steps include: forming a first source-drain structure 112 in the first trench 27 by an epitaxial growth process based on the third portion 212 in the gate region; removing the first barrier layer 30 to expose the fourth portion 213 in the gate region; forming a front source-drain isolation structure 28 on the first source-drain structure 112, the front source-drain isolation structure 28 being opposite to the first sacrificial layer 211; and forming a second source-drain structure 122 in the first trench 27 by an epitaxial growth process based on the exposed fourth portion 213 in the gate region on the front source-drain isolation structure 28.

[0100] It can be understood that the third portion 212 in the gate region is not covered by the first barrier layer 30 and the second barrier layer 31, so that the third portion 212 in the gate region can be connected to the first trench 27, so that an active structure can be epitaxially grown along the second direction on the sidewall of the third portion 212 in the gate region to form a first source-drain structure 112 in the first trench 27. Then, the position of the first source-drain structure 112 can be opposite to the position of the third portion 212, see Fig.10 shown.

[0101] It is understandable that after forming the first source-drain structure 112, the first barrier layer 30 may be removed to expose the fourth portion 213 in the gate region, see Fig.11Subsequently, a source-drain isolation structure (ie, a front isolation structure) may be formed between the first source-drain structure 112 and the second source-drain structure 122, see Fig.13 Specifically, an insulating material may be deposited on the first source-drain structure 112 to form a front source-drain isolation structure 28. Then, the front source-drain isolation structure 28 is located between the first source-drain structure 112 and the second source-drain structure 122, that is, the front source-drain isolation structure 28 may be located opposite to the first sacrificial layer 211.

[0102] It can be understood that after the front source-drain isolation structure 28 is formed, an active structure can be epitaxially grown along the second direction on the sidewall of the fourth portion 213 in the gate region on the front source-drain isolation structure 28 based on the exposed fourth portion 213 in the gate region through an epitaxial growth process to form a second source-drain structure 122 in the first trench 27, see Fig.12 Then, the position of the second source-drain structure 122 may be opposite to the position of the fourth portion 213 .

[0103] Here, the process of epitaxially growing the active structure can be selected according to actual needs, and the embodiments of the present application do not specifically limit this.

[0104] It should be noted that the first source-drain structure 112 and the second source-drain structure 122 have different polarities, so that the front vertical stacked transistor 101 can be a complementary stacked transistor.

[0105] In some embodiments, after forming the first source-drain structure 112 in the first trench 27 by an epitaxial growth process, the method further includes: depositing a metal material on the first source-drain structure 112 to form a first source-drain metal 115 .

[0106] It is understood that after forming the first source-drain structure 112, a dielectric layer material may be deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113 of the first transistor 11. Subsequently, a hole may be opened in the first interlayer dielectric layer 113 until the first source-drain structure 112 is exposed. Subsequently, a metal material may be deposited on the first source-drain structure 112 until a first source-drain metal 115 is formed, see Fig.12 shown.

[0107] In some embodiments, forming the front source-drain isolation structure 28 on the first source-drain structure 112 includes: depositing an insulating material on the first source-drain metal 115 to form the front source-drain isolation structure 28 .

[0108] It is understood that after forming the first source-drain metal 115, an insulating material may be deposited on the first source-drain metal 115 and the first interlayer dielectric layer 113 to form a front source-drain isolation structure 28, see Fig.13 shown.

[0109] In some embodiments, the first source-drain metal 115 and the front source-drain isolation structure 28 may be positioned relative to the first sacrificial layer 211 to prevent the first source-drain metal 115 and the front source-drain isolation structure 28 from affecting exposure of the fourth portion 213 .

[0110] In some embodiments, after forming the second source-drain structure 122 in the first trench 27 by an epitaxial growth process, the method further includes: depositing a metal material on the second source-drain structure 122 to form a second source-drain metal 125 .

[0111] It is understandable that after forming the second source-drain structure 122, a dielectric layer material may be deposited on the second source-drain structure 122 to form a second interlayer dielectric layer 123 of the second transistor 12, see Fig.15 As shown. Subsequently, a front dielectric layer 127 may be deposited on the second interlayer dielectric layer 123, and holes may be opened on the front dielectric layer 127 and the second interlayer dielectric layer 113 until the second source-drain structure 122 is exposed. Subsequently, a metal material may be deposited on the second source-drain structure 122 until a second source-drain metal 125 is formed, see Fig.16 shown.

[0112] In some possible embodiments, the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertically stacked transistor 101 is formed at the position where the first sacrificial layer 211 and the first dummy gate structure 26 are removed, including: removing the first dummy gate structure 26 to expose the third part 212, the first sacrificial layer 211 and the fourth part 213 in the gate region; removing the first sacrificial layer 211 in the gate region by an etching process to expose the first surface of the third part 212 and the second surface of the fourth part 213 to form a first gate structure 114 surrounding the third part 212; and forming a second gate structure 124 surrounding the fourth part 213.

[0113] It can be understood that after forming the front source-drain structure of the front vertical stacked transistor 101, the front gate structure of the front vertical stacked transistor 101 can be formed by removing the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region and filling the gate material. First, the first dummy gate structure 26 can be removed to expose the third portion 212, the first sacrificial layer 211 and the fourth portion 213 wrapped by the first dummy gate structure 26 in the gate region. Subsequently, an etching process can be used to remove the first sacrificial layer 211 in the exposed gate region to expose the surfaces of the third portion 212 and the fourth portion 213 that are connected to the first sacrificial layer 211, that is, to expose the first surface of the third portion 212 and the second surface of the fourth portion 213.

[0114] Here, the first surface of the third portion 212 is a surface of the third portion 212 away from the semiconductor substrate 20 , and the second surface of the fourth portion 213 is a surface of the fourth portion 213 close to the semiconductor substrate 20 .

[0115] It can be understood that after the first surface of the third portion 212 and the second surface of the fourth portion 213 are exposed, the third portion 212 and the fourth portion 213 in the gate region form a gap, and then, a gate material can be deposited in the gate region to form a first gate structure 114 surrounding the third portion 212 and a second gate structure 124 surrounding the fourth portion 213. The junction of the first gate structure 114 and the second gate structure 124 is located between the first surface and the second surface.

[0116] Here, the process of forming the first gate structure 114 surrounding the third portion 212 and the second gate structure 124 surrounding the fourth portion 213 can be selected according to actual needs, and the embodiment of the present application does not make any specific limitation on this.

[0117] Exemplarily, the process of forming the first gate structure 114 and the second gate structure 124 may include: depositing a gate dielectric material to form a gate dielectric layer of the first gate structure 114 and the second gate structure 124, and then depositing a first gate metal material to form the first gate structure 114; finally, depositing a second gate metal material to form the second gate structure 124.

[0118] In some embodiments, the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertically stacked transistor 101 is formed at the position where the first sacrificial layer 211 and the first dummy gate structure 26 are removed, including: removing the first dummy gate structure 26 to expose the third part 212, the first sacrificial layer 211, the fourth part 213 and the second sacrificial layer 214 in the gate region; using an etching process to remove the first sacrificial layer 211 and the second sacrificial layer 214 in the gate region to form a first gate structure 114 surrounding the third part 212 with the first surface of the third part 212, the third surface of the third part 212 and the second surface of the fourth part 213; forming a second gate structure 124 surrounding the fourth part 213.

[0119] It is understood that after forming the front source-drain structure of the front vertical stacked transistor 101, the front gate structure of the front vertical stacked transistor 101 can be formed by removing the first sacrificial layer 211, the second sacrificial layer 214 and the first dummy gate structure 26 in the gate region and filling the gate material. First, the first dummy gate structure 26 can be removed to expose the third portion 212, the first sacrificial layer 211, the fourth portion 213 and the second sacrificial layer 214 in the gate region that are wrapped by the first dummy gate structure 26. Subsequently, an etching process can be used to remove the first sacrificial layer 211 and the second sacrificial layer 214 in the exposed gate region to expose the first surface and the third surface of the third portion 212, and the second surface of the fourth portion 213, see Fig.15 shown.

[0120] Among them, the first surface of the third part 212 is the surface of the third part 212 away from the semiconductor substrate 20, the third surface of the third part 212 is the surface of the third part 212 close to the semiconductor substrate 20, and the second surface of the fourth part 213 is the surface of the fourth part 213 close to the semiconductor substrate 20.

[0121] It can be understood that after removing the first dummy gate structure 26, the front and rear surfaces of the third portion 212 are completely exposed. After removing the first sacrificial layer 211 and the second sacrificial layer, the upper and lower surfaces of the third portion 212 are completely exposed. Then, the third portion 212 in the gate region is completely exposed, so that the first gate structure 114 surrounding the third portion 212 can be formed.

[0122] It can be understood that after removing the first dummy gate structure 26, the front and rear surfaces and the upper surface of the fourth portion 213 are completely exposed. At the same time, after removing the first sacrificial layer 211, the lower surface of the fourth portion 213 is completely exposed. Then, the fourth portion 213 in the gate region is completely exposed, so that the second gate structure 124 surrounding the fourth portion 213 can be formed.

[0123] It can be seen from one or more of the above-mentioned embodiments of forming the gate structure that when the transistor type is a full-surround gate field effect transistor, it is necessary to form a second sacrificial layer 214 in the first part 21 of the active structure; when the transistor type is a fin field effect transistor, it is not necessary to form the second sacrificial layer 214 in the first part 21 of the active structure, thereby reducing the preparation steps and improving the preparation efficiency.

[0124] In one embodiment, after forming the second gate structure 124 and the second source-drain metal 125, a standard back-end process of semiconductor manufacturing (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) can be used on the second source-drain metal 125 and the second gate structure 124 to form a front metal interconnect layer 1011 of the front vertical stacked transistor, see Figure 16 to Figure 17 shown.

[0125] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain groove, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0126] In step S203 : the semiconductor substrate 20 is flipped over and removed.

[0127] It can be understood that after obtaining the front vertical stacked transistor 101, the front vertical stacked transistor 101 can be flipped over so that the completed front vertical stacked transistor 101 is located at the bottom, and the second part 22 of the active structure of the unfinished reverse vertical stacked transistor 102 can be located at the top, so as to facilitate the subsequent preparation of the reverse vertical stacked transistor 102.

[0128] In one embodiment, after the back-end process of the front vertical stacked transistor 101 is completed, the front vertical stacked transistor 101 can be bonded to the carrier wafer 33. For example, an insulating material (such as silicon oxide) can be deposited on the front vertical stacked transistor 101 to form an insulating layer 32, and the insulating layer 32 can be bonded to the carrier wafer 33. Then, the wafer is flipped. After the flip, the front vertical stacked transistor 101 is located at the bottom. Fig.18 shown.

[0129] In the embodiment of the present application, the bonded carrier wafer 33 can provide physical support for the flipped front vertical stacked transistor 101 after flipping over, effectively preventing the front vertical stacked transistor 101 from being broken by external force during the preparation of the reverse vertical stacked transistor 102.

[0130] In one embodiment, after flipping, the semiconductor substrate 20 and the shallow trench isolation structure 25 can be removed by polishing or chemical mechanical planarization to expose the second portion 22 of the active structure. Figures 19 to 20 shown.

[0131] In step S204 : based on the second portion 22 , a reverse vertical stacked transistor 102 is formed.

[0132] It can be understood that after exposing the second part 22 of the active structure, the reverse vertical stacked transistor 102 can be formed by the same method as the front vertical stacked transistor 101, or by a method different from the method of forming the front vertical stacked transistor 101. The embodiment of the present application does not specifically limit this.

[0133] For example, Figure 20 to Figure 21 It is shown that the back side vertical stacked transistor 102 is formed by the same method as the front side vertical stacked transistor 101 .

[0134] It can be understood that the reverse vertical stacked transistor 102 includes a third transistor 13 and a fourth transistor 14 stacked along the first direction. The third transistor 13 includes a third dummy gate spacer 131, a third source-drain structure 132, a third interlayer dielectric layer 133, a third gate structure 134, and a third source-drain metal 135; the fourth transistor 14 includes a fourth dummy gate spacer 141, a fourth source-drain structure 142, a fourth interlayer dielectric layer 143, a fourth gate structure 144, and a fourth source-drain metal 145.

[0135] In some embodiments, the second portion 22 includes a third sacrificial layer, and the third sacrificial layer is located in the middle of the second portion 22; based on the second portion 22, a reverse vertical stacked transistor 102 is formed, including: based on the second portion 22, at least three second dummy gate structures surrounding the second portion 22 and dummy gate sidewalls covering the second dummy gate structures are formed, and the at least three second dummy gate structures are arranged along the second direction; using the second dummy gate structure as a hard mask, etching the second portion 22 located in the source and drain region to form a second trench, wherein the area between the dummy gate sidewalls of two adjacent second dummy gate structures is the source and drain region, and the area where the first dummy gate structure 26 and its dummy gate sidewalls are located is the gate region; in the second A reverse source-drain structure of a reverse vertically stacked transistor 102 is formed in the groove, and the reverse source-drain structure includes a third source-drain structure 132 of the third transistor 13, a reverse source-drain isolation structure 34, and a fourth source-drain structure 142 of the fourth transistor 14; the third sacrificial layer and the second dummy gate structure in the gate area are removed, and a reverse gate structure of the reverse vertically stacked transistor 102 is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, and the reverse gate structure includes a third gate structure 134 of the third transistor 13 and a fourth gate structure 144 of the fourth transistor 14, and the junction between the third gate structure 134 and the fourth gate structure 144 is located at the position where the third sacrificial layer is removed.

[0136] In some embodiments, the second portion 22 also includes: a fifth portion 222 and a sixth portion 223, the third sacrificial layer is located between the fifth portion 222 and the sixth portion 223, and the fifth portion 222 is closer to the semiconductor substrate than the sixth portion 223; using the second pseudo gate structure as a hard mask, etching the second portion 22 located in the source and drain region to form a second trench, including: using the second pseudo gate structure as a hard mask, etching the sixth portion 223 and the third sacrificial layer located in the source and drain region to expose the sixth portion 223 and the third sacrificial layer in the gate region and form a second initial trench; forming a third barrier layer on the side walls of the sixth portion 223 and the third sacrificial layer in the gate region; etching the fifth portion 222 located below the second initial trench to expose the fifth portion 222 in the gate region and form a second trench.

[0137] In some embodiments, the third sacrificial layer and the second dummy gate structure in the gate region are removed, and a reverse gate structure of the reverse vertical stacked transistor 102 is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, including: removing the second dummy gate structure to expose the fifth portion 222, the third sacrificial layer and the sixth portion 223 in the gate region; removing the third sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion 222 and the fifth surface of the sixth portion 223, wherein the fourth surface of the fifth portion 222 is the surface of the fifth portion 222 away from the semiconductor substrate, and the fifth surface of the sixth portion 223 is the surface of the sixth portion 223 close to the semiconductor substrate; forming a third gate structure 134 surrounding the fifth portion 222; forming a fourth gate structure 144 surrounding the sixth portion 223, wherein the junction of the third gate structure 134 and the fourth gate structure 144 is located between the fourth surface and the fifth surface.

[0138] In some embodiments, the second portion 22 also includes a fourth sacrificial layer, which is closer to the semiconductor substrate than the fifth portion 222; etching the fifth portion 222 located below the second initial trench to expose the fifth portion 222 in the gate area and form a second trench, and also includes: etching the fifth portion 222 and the fourth sacrificial layer located below the second initial trench to expose the fifth portion 222 and the fourth sacrificial layer in the gate area; forming a fourth barrier layer 35 on the side wall of the fourth sacrificial layer in the gate area, and forming a second trench.

[0139] In some embodiments, the third sacrificial layer and the second dummy gate structure in the gate region are removed, and a reverse gate structure of the reverse vertical stacked transistor 102 is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, and the method also includes: removing the second dummy gate structure to expose the fifth portion 222, the third sacrificial layer, the sixth portion 223 and the fourth sacrificial layer in the gate region; removing the third sacrificial layer and the fourth sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion 222, the sixth surface of the fifth portion 222 and the fifth surface of the sixth portion 223, wherein the fourth surface of the fifth portion 222 is the surface of the fifth portion 222 away from the semiconductor substrate, the sixth surface of the fifth portion 222 is the surface of the fifth portion 222 close to the semiconductor substrate, and the fifth surface of the sixth portion 223 is the surface of the sixth portion 223 close to the semiconductor substrate; forming a third gate structure 134 surrounding the fifth portion 222; and forming a fourth gate structure 144 surrounding the sixth portion 223.

[0140] In some embodiments, a reverse source-drain structure of a reverse vertically stacked transistor 102 is formed in the second trench, including: based on the fifth portion 222 in the gate region, a third source-drain structure is formed in the second trench by an epitaxial growth process, and the third source-drain structure is opposite to the fifth portion 222; the third barrier layer is removed to expose the sixth portion 223 in the gate region; a reverse source-drain isolation structure 34 is formed on the third source-drain structure, and the reverse source-drain isolation structure 34 is opposite to the third sacrificial layer; and on the reverse source-drain isolation structure 34, based on the exposed sixth portion 223 in the gate region, a fourth source-drain structure is formed in the second trench by an epitaxial growth process, and the fourth source-drain structure is opposite to the sixth portion 223.

[0141] In some embodiments, before forming a third barrier layer on the sixth portion 223 and the side wall of the third sacrificial layer in the gate region, the method also includes: using an etching process to laterally etch the side wall of the third sacrificial layer in the exposed gate region to form a second groove; filling the second groove with insulating material to form a third pseudo gate side wall 131 of the third transistor 13, the third pseudo gate side wall 131 completely covering the side wall of the third sacrificial layer in the gate region, and the pseudo gate side wall of the second pseudo gate structure is used to form a fourth pseudo gate side wall 141 of the fourth transistor 14.

[0142] In some embodiments, after forming a third source-drain structure 132 in the second trench by an epitaxial growth process, the method further includes: depositing a metal material on the third source-drain structure 132 to form a third source-drain metal 135; forming a reverse source-drain isolation structure 34 on the third source-drain structure 132, including: depositing an insulating material on the third source-drain metal 135 to form a reverse source-drain isolation structure 34, the third source-drain metal 135 and the reverse source-drain isolation structure 34 being jointly opposite to the third sacrificial layer; after forming a fourth source-drain structure in the second trench by an epitaxial growth process, the method further includes: depositing a metal material on the fourth source-drain structure 142 to form a fourth source-drain metal 145.

[0143] In some embodiments, after forming the fourth source-drain structure 142, a dielectric layer material may be deposited on the fourth source-drain structure 142 to form a fourth interlayer dielectric layer 143 of the fourth transistor 14. Subsequently, a reverse dielectric layer 147 may be deposited on the fourth interlayer dielectric layer 143, and holes may be opened in the reverse dielectric layer 147 and the fourth interlayer dielectric layer 143 until the fourth source-drain structure 142 is exposed. Subsequently, a metal material may be deposited on the fourth source-drain structure 142 until a fourth source-drain metal 145 is formed, see Fig.21 shown.

[0144] In some embodiments, after forming the fourth gate structure 144 and the fourth source-drain metal 145, a standard back-end process of semiconductor preparation (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be used on the fourth source-drain metal 145 and the fourth gate structure 144 to form a reverse metal interconnect layer 1021 of the reverse vertically stacked transistor 102.

[0145] It should be noted that the process of forming the reverse vertical stacked transistor 102 may refer to the description of one or more of the processes of forming the forward vertical stacked transistor 101 , and for the sake of brevity of the specification, it will not be repeated here.

[0146] At this point, the preparation of the stacked transistor 10 is completed.

[0147] In an embodiment of the present application, by forming an active structure with a certain depth on a semiconductor substrate by etching once, it is possible to achieve self-alignment of the active areas of the front vertically stacked transistors and the back vertically stacked transistors. Subsequently, a first transistor and a second transistor with different polarities can be prepared based on the first part of the active structure, and the semiconductor substrate is etched after flipping, so that a third transistor and a fourth transistor with different polarities can be prepared based on the second part of the active structure. It can be seen that by forming a pair of stacked transistors on the front side of the wafer and another pair of stacked transistors on the back side of the wafer, it is possible to prepare more transistors using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors.

[0148] In an embodiment of the present disclosure, a stacked transistor 10 is provided. The stacked transistor 10 can be used Figures 3 to 21 The method of one or more corresponding embodiments is prepared. Fig.21 As shown, the stacked transistor 10 includes: a front vertically stacked transistor, including: a first transistor and a second transistor, the first transistor and the second transistor have different polarities, the first transistor and the second transistor are self-aligned in a first direction, and the first direction is a direction perpendicular to the semiconductor substrate.

[0149] The reverse vertical stacked transistor comprises: a third transistor and a fourth transistor, the third transistor and the fourth transistor have different polarities, and the third transistor and the fourth transistor are self-aligned in a first direction; wherein the front vertical stacked transistor and the reverse vertical stacked transistor are arranged back to back, and the front vertical stacked transistor and the reverse vertical stacked transistor are self-aligned in the first direction.

[0150] In some embodiments, the type of the first transistor 11 or the second transistor 12 is any one of the following: a planar transistor, a fin field effect transistor, or a gate-all-around transistor.

[0151] It is understandable that the stacked transistor in the embodiment of the present application can be used Figures 3 to 21 The corresponding one or more embodiments are prepared by the preparation method. The embodiment of the present application forms a front vertical stacked transistor on the front side of the wafer, the front vertical stacked transistor includes two stacked transistors, and forms a back vertical stacked transistor on the back side of the wafer, the back vertical stacked transistor includes two stacked transistors, so that the integration performance of the stacked transistor is further enhanced.

[0152] It should be noted that the solution of realizing upper and lower transistors by flipping the wafer in the embodiment of the present application is an organic fusion of the current sequential and monolithic stacked transistor solutions, taking into account the consistency, defect density, alignment and thermal budget of the active areas of the upper and lower transistors. This solution solves the long-standing problems existing in the mainstream technical solutions for stacked transistors, such as complex process, fixed polarity (monolithic solution) and difficult alignment, and high defect density of upper semiconductor materials (sequential solution), thereby promoting the industrialization of transistor stacking technology.

[0153] In addition, the mature technology of the flip-chip stacked transistor solution has high reuse, which can avoid a lot of expensive process development to save costs and has high feasibility. At the same time, the flip-chip transistor adopts a self-aligned "back-to-back" active area design. The front and back transistors have independent signal and power supply networks and are connected through local interconnection, which greatly releases metal wiring resources (compared to the current solution, it is increased by more than 60%), and there is huge room for collaborative optimization of process design.

[0154] Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures, and can realize the front and back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs) without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and is highly practical and has broad prospects for development. In an embodiment of the present application, the flip-chip transistor solution can also be a flip-chip stack of complementary stacked transistors of the type of planar transistors, FinFETs, GAA Nanosheets, and vertical transistors, thereby further increasing the integration density of the transistor and improving the integration performance of the transistor.

[0155] The present application embodiment provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be at least referred to in the above Fig.21 The stacked transistors shown are not described in detail here.

[0156] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above stacked transistor. The specific definition of the stacked transistor can be at least referred to in the above Fig.21 The structure shown will not be described in detail here.

[0157] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0158] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: Etching once to form an active structure on a semiconductor substrate, wherein the active structure includes a first portion and a second portion, wherein the second portion is closer to the semiconductor substrate than the first portion; Based on the first part, a front vertical stacked transistor is formed, wherein the front vertical stacked transistor comprises: a first transistor and a second transistor, wherein the first transistor and the second transistor have different polarities, and the first transistor and the second transistor are self-aligned in a first direction, wherein the first direction is a direction perpendicular to the semiconductor substrate; Flipping and removing the semiconductor substrate; Based on the second part, a reverse vertical stacked transistor is formed, wherein the reverse vertical stacked transistor includes: a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor have different polarities, and the third transistor and the fourth transistor are self-aligned in the first direction; The front vertical stacked transistor and the back vertical stacked transistor are arranged back to back, and the front vertical stacked transistor and the back vertical stacked transistor are self-aligned in the first direction.

2. The preparation method according to claim 1, characterized in that: The first portion includes a first sacrificial layer, and the first sacrificial layer is located in a middle portion of the first portion; Based on the first part, a front vertical stacked transistor is formed, comprising: Based on the first portion, at least three first dummy gate structures surrounding the first portion and dummy gate spacers covering the first dummy gate structures are formed, wherein the at least three first dummy gate structures are arranged along a second direction, and the second direction is perpendicular to the first direction; Using the first dummy gate structure as a hard mask, etching the first portion located in the source-drain region to form a first trench, wherein the region between the dummy gate sidewalls of two adjacent first dummy gate structures is the source-drain region, and the region where the first dummy gate structure and its dummy gate sidewalls are located is the gate region; forming a front source-drain structure of a front vertically stacked transistor in the first trench, wherein the front source-drain structure comprises a first source-drain structure of the first transistor, a front source-drain isolation structure, and a second source-drain structure of the second transistor; The first sacrificial layer and the first dummy gate structure in the gate area are removed, and a front gate structure of a front vertically stacked transistor is formed at the position where the first sacrificial layer and the first dummy gate structure are removed, the front gate structure includes a first gate structure of the first transistor and a second gate structure of the second transistor, and the junction of the first gate structure and the second gate structure is located at the position where the first sacrificial layer is removed.

3. The preparation method according to claim 2, characterized in that: The first portion further includes: a third portion and a fourth portion, the first sacrificial layer is located between the third portion and the fourth portion, and the third portion is closer to the semiconductor substrate than the fourth portion; The step of using the first dummy gate structure as a hard mask to etch the first portion located in the source / drain region to form a first trench includes: Using the first dummy gate structure as a hard mask, etching the fourth portion and the first sacrificial layer in the source / drain region to expose the fourth portion and the first sacrificial layer in the gate region and form a first initial trench; forming a first barrier layer on the sidewalls of the fourth portion and the first sacrificial layer in the gate region; The third portion below the first initial trench is etched to expose the third portion in the gate region and form the first trench.

4. The preparation method according to claim 3, characterized in that: The removing the first sacrificial layer and the first dummy gate structure in the gate region, and forming a front gate structure of a front vertically stacked transistor at a position where the first sacrificial layer and the first dummy gate structure are removed, comprises: removing the first dummy gate structure to expose the third portion, the first sacrificial layer and the fourth portion in the gate region; Using an etching process to remove the first sacrificial layer in the gate region to expose a first surface of the third portion and a second surface of the fourth portion, wherein the first surface of the third portion is a surface of the third portion away from the semiconductor substrate, and the second surface of the fourth portion is a surface of the fourth portion close to the semiconductor substrate; forming the first gate structure surrounding the third portion; The second gate structure surrounding the fourth portion is formed, and a junction between the first gate structure and the second gate structure is located between the first surface and the second surface.

5. The preparation method according to claim 3, characterized in that: The first portion further includes a second sacrificial layer, the second sacrificial layer being closer to the semiconductor substrate than the third portion; The etching of the third portion below the first initial trench to expose the third portion in the gate region and form the first trench further includes: Etching the third portion and the second sacrificial layer below the first initial trench to expose the third portion and the second sacrificial layer in the gate region; A second barrier layer is formed on the sidewall of the second sacrificial layer in the gate region, and the first trench is formed.

6. The preparation method according to claim 5, characterized in that: The method further comprises: removing the first sacrificial layer and the first dummy gate structure in the gate region, and forming a front gate structure of a front vertically stacked transistor at a position where the first sacrificial layer and the first dummy gate structure are removed. removing the first dummy gate structure to expose the third portion, the first sacrificial layer, the fourth portion and the second sacrificial layer in the gate region; Using an etching process to remove the first sacrificial layer and the second sacrificial layer in the gate region to expose the first surface of the third portion, the third surface of the third portion, and the second surface of the fourth portion, wherein the first surface of the third portion is a surface of the third portion away from the semiconductor substrate, the third surface of the third portion is a surface of the third portion close to the semiconductor substrate, and the second surface of the fourth portion is a surface of the fourth portion close to the semiconductor substrate; forming the first gate structure surrounding the third portion; The second gate structure is formed surrounding the fourth portion.

7. The preparation method according to any one of claims 3 to 6, characterized in that: The front source-drain structure of the front vertically stacked transistor is formed in the first trench, comprising: Based on the third portion in the gate region, forming the first source-drain structure in the first trench by an epitaxial growth process, the first source-drain structure being opposite to the third portion; removing the first barrier layer to expose the fourth portion in the gate region; forming the front source-drain isolation structure on the first source-drain structure, wherein the front source-drain isolation structure is opposite to the first sacrificial layer; On the front source-drain isolation structure, based on the exposed fourth portion in the gate region, the second source-drain structure is formed in the first trench through an epitaxial growth process, and the second source-drain structure is opposite to the fourth portion.

8. The preparation method according to claim 7, characterized in that: Before forming a first barrier layer on the fourth portion in the gate region and on the sidewall of the first sacrificial layer, the method further includes: Using an etching process, laterally etching the exposed sidewall of the first sacrificial layer in the gate region to form a first groove; An insulating material is filled in the first groove to form a first dummy gate sidewall of the first transistor, the first dummy gate sidewall completely covers the sidewall of the first sacrificial layer in the gate area, and the dummy gate sidewall of the first dummy gate structure is used to form a second dummy gate sidewall of the second transistor.

9. The preparation method according to claim 7, characterized in that: After forming the first source-drain structure in the first trench by an epitaxial growth process, the method further includes: Depositing a metal material on the first source-drain structure to form the first source-drain metal; The forming of the front source-drain isolation structure on the first source-drain structure comprises: Depositing an insulating material on the first source-drain metal to form the front source-drain isolation structure, wherein the first source-drain metal and the front source-drain isolation structure are opposite to the first sacrificial layer; After forming the second source-drain structure in the first trench by an epitaxial growth process, the method further includes: A metal material is deposited on the second source-drain structure to form a second source-drain metal.

10. The preparation method according to claim 1, characterized in that: The second portion includes a third sacrificial layer, and the third sacrificial layer is located in a middle portion of the second portion; Based on the second part, a reverse vertical stacked transistor is formed, comprising: Based on the second portion, at least three second dummy gate structures surrounding the second portion and dummy gate spacers covering the second dummy gate structures are formed, wherein the at least three second dummy gate structures are arranged along a second direction; Using the second dummy gate structure as a hard mask, etching the second portion located in the source and drain region to form a second trench, wherein the region between the dummy gate sidewalls of two adjacent second dummy gate structures is the source and drain region, and the region where the first dummy gate structure and its dummy gate sidewalls are located is the gate region; forming a reverse source-drain structure of a reverse vertically stacked transistor in the second trench, wherein the reverse source-drain structure includes a third source-drain structure of a third transistor, a reverse source-drain isolation structure, and a fourth source-drain structure of a fourth transistor; The third sacrificial layer and the second dummy gate structure in the gate area are removed, and a reverse gate structure of a reverse vertically stacked transistor is formed at the position where the third sacrificial layer and the second dummy gate structure are removed, the reverse gate structure includes a third gate structure of the third transistor and a fourth gate structure of the fourth transistor, and the junction of the third gate structure and the fourth gate structure is located at the position where the third sacrificial layer is removed.

11. The preparation method according to claim 10, characterized in that: The second portion further includes: a fifth portion and a sixth portion, the third sacrificial layer is located between the fifth portion and the sixth portion, and the fifth portion is closer to the semiconductor substrate than the sixth portion; The step of using the second dummy gate structure as a hard mask to etch the second portion located in the source / drain region to form a second trench comprises: Using the second dummy gate structure as a hard mask, etching the sixth portion and the third sacrificial layer in the source and drain region to expose the sixth portion and the third sacrificial layer in the gate region and form a second initial trench; forming a third barrier layer on the sidewalls of the sixth portion and the third sacrificial layer in the gate region; The fifth portion located below the second initial trench is etched to expose the fifth portion in the gate region and form the second trench.

12. The preparation method according to claim 11, characterized in that: The removing the third sacrificial layer and the second dummy gate structure in the gate region, and forming a reverse gate structure of a reverse vertically stacked transistor at a position where the third sacrificial layer and the second dummy gate structure are removed, comprises: removing the second dummy gate structure to expose the fifth portion, the third sacrificial layer and the sixth portion in the gate region; Removing the third sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion and the fifth surface of the sixth portion, wherein the fourth surface of the fifth portion is a surface of the fifth portion away from the semiconductor substrate, and the fifth surface of the sixth portion is a surface of the sixth portion close to the semiconductor substrate; forming the third gate structure surrounding the fifth portion; The fourth gate structure surrounding the sixth portion is formed, and a junction between the third gate structure and the fourth gate structure is located between the fourth surface and the fifth surface.

13. The preparation method according to claim 11, characterized in that: The second portion further includes a fourth sacrificial layer, the fourth sacrificial layer being closer to the semiconductor substrate than the fifth portion; The etching of the fifth portion below the second initial trench to expose the fifth portion in the gate region and form the second trench further includes: Etching the fifth portion and the fourth sacrificial layer below the second initial trench to expose the fifth portion and the fourth sacrificial layer in the gate region; A fourth barrier layer is formed on the sidewall of the fourth sacrificial layer in the gate region, and the second trench is formed.

14. The preparation method according to claim 13, characterized in that: The method further comprises: removing the third sacrificial layer and the second dummy gate structure in the gate region, and forming a reverse gate structure of a reverse vertically stacked transistor at a position where the third sacrificial layer and the second dummy gate structure are removed. removing the second dummy gate structure to expose the fifth portion, the third sacrificial layer, the sixth portion and the fourth sacrificial layer in the gate region; Removing the third sacrificial layer and the fourth sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion, the sixth surface of the fifth portion, and the fifth surface of the sixth portion, wherein the fourth surface of the fifth portion is a surface of the fifth portion away from the semiconductor substrate, the sixth surface of the fifth portion is a surface of the fifth portion close to the semiconductor substrate, and the fifth surface of the sixth portion is a surface of the sixth portion close to the semiconductor substrate; forming the third gate structure surrounding the fifth portion; The fourth gate structure is formed surrounding the sixth portion.

15. The preparation method according to any one of claims 11 to 14, characterized in that: The reverse source-drain structure of the reverse vertically stacked transistor is formed in the second trench, comprising: Based on the fifth portion in the gate region, forming the third source-drain structure in the second trench by an epitaxial growth process, the third source-drain structure being opposite to the fifth portion; removing the third barrier layer to expose the sixth portion in the gate region; forming the reverse source-drain isolation structure on the third source-drain structure, wherein the reverse source-drain isolation structure is opposite to the third sacrificial layer; On the reverse source-drain isolation structure, based on the exposed sixth portion in the gate region, the fourth source-drain structure is formed in the second trench by an epitaxial growth process, and the fourth source-drain structure is opposite to the sixth portion.

16. The preparation method according to claim 15, characterized in that: Before forming a third barrier layer on the sixth portion in the gate region and on the sidewalls of the third sacrificial layer, the method further includes: Using an etching process, laterally etching the exposed sidewall of the third sacrificial layer in the gate region to form a second groove; Fill the second groove with insulating material to form a third dummy gate sidewall of the third transistor, wherein the third dummy gate sidewall completely covers the sidewall of the third sacrificial layer in the gate region, and the dummy gate sidewall of the second dummy gate structure is used to form a fourth dummy gate sidewall of the fourth transistor.

17. The preparation method according to claim 15, characterized in that: After forming the third source-drain structure in the second trench by an epitaxial growth process, the method further includes: Depositing a metal material on the third source-drain structure to form the third source-drain metal; The forming of the reverse source-drain isolation structure on the third source-drain structure comprises: Depositing an insulating material on the third source-drain metal to form the reverse source-drain isolation structure, wherein the third source-drain metal and the reverse source-drain isolation structure are opposite to the third sacrificial layer; After forming the fourth source-drain structure in the second trench by an epitaxial growth process, the method further includes: A metal material is deposited on the fourth source-drain structure to form a fourth source-drain metal.

18. A stacked transistor, prepared by the method according to any one of claims 1 to 17, characterized in that: include: A front vertically stacked transistor, comprising: a first transistor and a second transistor, wherein the first transistor and the second transistor have different polarities, and the first transistor and the second transistor are self-aligned in a first direction, wherein the first direction is a direction perpendicular to the semiconductor substrate; A reverse vertically stacked transistor, comprising: a third transistor and a fourth transistor, the third transistor and the fourth transistor having different polarities, the third transistor and the fourth transistor being self-aligned in the first direction; The front vertical stacked transistor and the back vertical stacked transistor are arranged back to back, and the front vertical stacked transistor and the back vertical stacked transistor are self-aligned in the first direction.

19. A semiconductor device, characterized in that: include: The stacked transistor of claim 18.

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