Method, device and equipment for communication between NVMe equipment and host, and storage medium

Abstract

The invention relates to the technical field of storage, and discloses a method and device for communication between NVMe equipment and a host, equipment and a storage medium. The method is applied to an NVMe device controller, and comprises the following steps: acquiring at least two SQEs from an SQ queue of a host end as aggregation SQEs to be processed this time; the SQ queue is used for storing single SQE or aggregated SQE needing to be processed by an NVMe equipment controller; the aggregated SQE is at least two SQEs which have a relative sequence and need to be executed together; based on the SQE to be processed this time, creating a total CQE; the total CQE is used for recording a command execution result corresponding to each SQE; according to the sequence of the SQEs in the SQ queue, analyzing each SQE to obtain a corresponding command, executing the command, and obtaining a corresponding command execution result; recording all command execution results in the total CQE; returning the total CQE to a host end, and writing the total CQE into a CQ queue; the CQ queue is used for storing a single CQE or a total CQE generated when the NVMe device processes the SQE, and the CQ queue corresponds to the SQ queue. By adopting the method, the data volume for transmitting the CQE between the NVMe equipment and the host can be reduced, the system resources are saved, the transmission efficiency of the NVMe command is improved, the reading frequency of the host on the CQE is reduced, the data operation time delay is reduced, and the data processing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method, apparatus, device and storage medium for communication between an NVMe device and a host. Background Art

[0002] The NVMe (Nonvolatile Memory Express) protocol is a new storage access and transmission protocol for flash memory and next-generation solid-state drives (SSDs). It is a set of interface standards developed mainly for PCIe SSDs. Compared with the traditional AHCI standard, the NVMe standard can bring performance improvements in many aspects.

[0003] In a storage system using NVMe devices, when the host needs to send a command to the NVMe device, it will first write the command to SQ (Submission Queue) through SQE (Submission Queue Entry), and then send a message to the NVMe device controller. The NVMe device controller reads SQE(s) from the SQ queue, takes the command to the controller for internal processing, and then fills the command processing result, namely CQE (Completion Queue Entry), into CQ (Completion Queue), notifies the host side through an interrupt, and then the host side extracts the command execution result in the CQ queue.

[0004] During the command execution process, after the NVMe device controller processes each SQE, it will generate a corresponding CQE and return it to the host. The host needs to wait for the result data returned by the NVMe device controller and process all CQEs one by one. This process consumes more computing resources and has low data processing efficiency, reducing the overall performance of the storage system. Summary of the invention

[0005] In view of this, the present application aims to propose a method, apparatus, device and storage medium for NVMe device to communicate with a host, so as to save computing resources and improve data processing efficiency.

[0006] To achieve the above objectives, the technical solution of this application is as follows:

[0007] A first aspect of an embodiment of the present application provides a method for an NVMe device to communicate with a host, the method being applied to an NVMe device controller, comprising:

[0008] Obtain at least two SQEs from the SQ queue on the host side as the aggregate SQE to be processed this time; the SQ queue is used to store the single SQE or aggregate SQE that the NVMe device controller needs to process; the aggregate SQE is at least two SQEs that need to be executed together with a relative order;

[0009] Based on the SQE to be processed this time, a total CQE is created; the total CQE is used to record the command execution results corresponding to each SQE;

[0010] According to the order of the SQEs in the SQ queue, parse each SQE to obtain a corresponding command and execute it to obtain a corresponding command execution result;

[0011] Recording all command execution results in the total CQE;

[0012] The total CQE is returned to the host side and written into the CQ queue; the CQ queue is used to store the single CQE or total CQE generated by the NVMe device processing the SQE, and the CQ queue corresponds to the SQ queue.

[0013] Optionally, at least two SQEs are obtained from the SQ queue of the host as the aggregated SQEs to be processed this time, including:

[0014] Determine the total number of SQEs included in the aggregated SQE group to which the SQE belongs according to the SQE at the current read position in the SQ queue;

[0015] Compare the total number of the aggregated SQEs with a first threshold; if the total number of the aggregated SQEs is less than or equal to the first threshold, use the aggregated SQE group as the SQE to be processed this time;

[0016] When the total number of the aggregated SQEs is greater than the first threshold, starting from the SQE at the current read position, the aggregated SQEs of the first threshold are used as the SQEs to be processed this time.

[0017] Optionally, based on the SQE to be processed this time, create a total CQE, including:

[0018] Create a total CQE based on the total number of SQEs to be processed this time;

[0019] The total CQE records: the total CQE identifier, the total number of SQEs read this time, the queue identifier of the SQ queue to which the SQE read this time belongs, the submission identifier, and the starting address of the first SQE read this time.

[0020] Optionally, the method for the NVMe device to communicate with the host further includes:

[0021] After each command is executed, determine whether the current command execution result is successful or failed;

[0022] If the current command execution result is successful, perform the following steps: determine whether all commands corresponding to the SQEs have been executed; if there are unexecuted commands, continue to execute the next command; if all commands corresponding to the SQEs have been executed and all command execution results are successful, set the failure identifier of the total CQE to null; return the total CQE to the host end and write it into the CQ queue;

[0023] When the current command execution result is a failure, perform the following steps: stop executing the next command; obtain the aggregate identifier of the SQE corresponding to the command that currently failed to execute; based on the aggregate identifier, record the corresponding failure identifier in the total CQE; based on the SQE corresponding to the command that currently failed to execute, create a corresponding single CQE; record in the single CQE: error association information, the queue identifier of the SQ queue to which the SQE belongs, the starting address of the SQE, the error code, the submission identifier and the SQE identifier; return the total CQE and the single CQE to the host side, and write them into the CQ queue.

[0024] According to a second aspect of an embodiment of the present application, a method for communicating between an NVMe device and a host is provided, the method being applied to a host side, comprising:

[0025] Create an SQ queue and a corresponding CQ queue; the SQ queue is used to store a single SQE or aggregate SQE that the NVMe device controller needs to process; the CQ queue is used to store a single CQE or total CQE generated by the NVMe device processing SQE;

[0026] Based on at least one command that needs to be executed by the NVMe device controller, a corresponding SQE is generated, and all SQEs are written into the SQ queue in the execution order of the corresponding commands; wherein any SQE is a single SQE or an aggregate SQE in an aggregate SQE group;

[0027] The CQE written by the NVMe device controller is read from the CQ queue, and the CQE is parsed to obtain a command execution result corresponding to at least one SQE; the CQE is a total CQE or a single CQE.

[0028] Optionally, based on at least one command that needs to be executed by the NVMe device controller, a corresponding SQE is generated, including:

[0029] In a case where the plurality of commands have a relative order, generating at least one aggregated SQE group based on the plurality of commands;

[0030] Record in each aggregate SQE: an SQE identifier and an aggregate identifier; the SQE identifier is used to uniquely indicate a command corresponding to the aggregate SQE; the aggregate identifier is used to indicate the sequence number of the aggregate SQE in the aggregate SQE group to which it belongs;

[0031] All aggregated SQEs are written to the SQ queue in the relative order.

[0032] Optionally, generating at least one aggregated SQE group based on the multiple commands includes:

[0033] comparing the number of the plurality of commands to a second threshold;

[0034] If the number of the plurality of commands is less than or equal to the second threshold, generating an aggregate SQE group based on all commands;

[0035] In the case that the number of the plurality of commands is greater than the second threshold, a plurality of aggregated SQE groups are generated based on all the commands; wherein the total number of aggregated SQEs in each aggregated SQE group is not greater than the second threshold.

[0036] According to a third aspect of an embodiment of the present application, a device for communicating between an NVMe device and a host is provided, for implementing the method for communicating between an NVMe device and a host provided in the first aspect of the embodiment of the present application, the device comprising:

[0037] The first reading module is configured to obtain at least two SQEs from the SQ queue on the host side as the aggregate SQE to be processed this time; the SQ queue is used to store the single SQE or aggregate SQE that the NVMe device controller needs to process; the aggregate SQE is at least two SQEs that need to be executed together with a relative order;

[0038] A first recording module is configured to create a total CQE based on the SQE to be processed this time; the total CQE is used to record the command execution results corresponding to each SQE;

[0039] The first processing module parses each SQE according to the order of the SQEs in the SQ queue to obtain a corresponding command and executes it to obtain a corresponding command execution result;

[0040] The first recording module is further configured to record all command execution results in the total CQE;

[0041] The first writing module is configured to return the total CQE to the host side and write it into a CQ queue; the CQ queue is used to store the single CQE or total CQE generated by the NVMe device processing the SQE, and the CQ queue corresponds to the SQ queue.

[0042] According to a fourth aspect of an embodiment of the present application, a device for communicating between an NVMe device and a host is provided, for implementing the method for communicating between an NVMe device and a host provided in the second aspect of the embodiment of the present application, the device comprising:

[0043] A queue creation module is configured to create an SQ queue and a corresponding CQ queue; the SQ queue is used to store a single SQE or an aggregate SQE that the NVMe device controller needs to process; the CQ queue is used to store a single CQE or a total CQE generated by the NVMe device processing the SQE;

[0044] The second writing module is configured to generate a corresponding SQE based on at least one command that needs to be executed by the NVMe device controller, and write all SQEs into the SQ queue in the execution order of the corresponding commands; wherein any SQE is a single SQE or an aggregate SQE in an aggregate SQE group;

[0045] The second reading module is configured to read the CQE written by the NVMe device controller from the CQ queue, parse the CQE to obtain a command execution result corresponding to at least one SQE; the CQE is a total CQE or a single CQE.

[0046] According to a fifth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the method for communication between an NVMe device and a host as described in the first aspect or the second aspect of the embodiment of the present application are implemented.

[0047] According to a sixth aspect of an embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps in the method for communication between an NVMe device and a host as described in the first aspect or the second aspect of the embodiment of the present application are implemented.

[0048] The method for communicating between an NVMe device and a host provided in this application is adopted, and the NVMe device controller obtains multiple SQEs from the SQ queue of the host side as SQEs to be processed, and creates a total CQE to record the processing results of each SQE. The read SQE is parsed to obtain the corresponding command and executed, and the command execution result is obtained after the command execution is completed, and recorded in the total CQE, and the total CQE is returned to the host side and written into the CQ queue for the host side to read for subsequent processing.

[0049] In this application, when the NVMe device controller processes the SQE in the SQ queue, multiple SQEs are read out at one time for processing, and a total CQE is recorded according to the command execution results of all commands processed this time, and the total CQE is returned to the host side. Compared with the existing command processing process, which requires reading SQE execution one by one and returning single CQE one by one, this application can process multiple SQEs at one time, improves the command processing efficiency, and returns the processing results of multiple SQEs at one time in the form of a total CQE when returning CQE, reduces the frequency and amount of data of transmitting and reading CQE, thereby saving system computing resources, reducing data operation latency, and improving the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0051] Figure 1 This is one of the flow charts of the method for communication between an NVMe device and a host proposed in one embodiment of the present application;

[0052] Figure 2 is a flowchart of processing a host command in one embodiment of the present application;

[0053] Figure 3 This is the second flowchart of the method for communication between an NVMe device and a host proposed in one embodiment of the present application;

[0054] Figure 4 It is one of the schematic diagrams of the apparatus for communicating between an NVMe device and a host proposed in one embodiment of the present application;

[0055] Figure 5 This is a second schematic diagram of an apparatus for communicating between an NVMe device and a host proposed in an embodiment of the present application;

[0056] Figure 6 It is a schematic diagram of an electronic device proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0059] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0060] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects as detailed in the present application.

[0061] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0062] In the NVMe protocol, SQ is divided into ASQ (Admin Submission Queue) and IOSQ (I / O Submission queue). ASQ is a queue used to process management commands, which are usually used to configure and manage various operations of NVMe devices, such as obtaining device information, configuring namespaces, setting queue depth, etc. The host puts management commands into ASQ, and the NVMe device processes these commands. SQE is a data structure that the host submits commands or operations to the NVMe device. Each SQE contains a command description and related parameters that are used to specify the type of operation to be performed, relevant information for data transmission, and other control and configuration options. The host submits commands to the NVMe device by writing the SQE into the SQ queue.

[0063] IOSQ is a queue for storing and queuing I / O commands. The host puts I / O commands into IOSQ, and the NVMe device processes these commands. Each I / O command contains some metadata and operation parameters to indicate the data range to be read or written, the type of transfer, access rights, etc. SQ is divided into ACQ (Admin Completion Queue) and IOCQ (I / O Completion Queue). Among them, ACQ is a queue for managing the completion status and results of commands and operations, which appears in pairs with ASQ. IOCQ is a queue for managing the completion status and results of I / O commands. IOSQ and IOCQ can be one-to-one or many-to-one. CQE is a data structure that the NVMe device reports the completion status and results of each command to the host. When the host submits a command to the NVMe device for execution, the device generates a corresponding CQE after completing the operation and writes it to the CQ queue.

[0064] In this embodiment, a communication method between an NVMe device and a host is proposed. On the basis of not changing the existing NVMe protocol, the reserved fields in the CQE structure are used to realize batch reply of command execution results to the host.

[0065] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0066] Figure 1 1 is one of the flow charts of the method for NVMe device and host communication proposed in one embodiment of the present application. The method is applied to the NVMe device controller, such as Figure 1 As shown, the method includes:

[0067] S11: Obtain at least two SQEs from the SQ queue on the host side as the aggregate SQE to be processed this time; the SQ queue is used to store single SQEs or aggregate SQEs that the NVMe device controller needs to process; the aggregate SQE is at least two SQEs that need to be executed together with a relative order;

[0068] S12: Based on the SQE to be processed this time, a total CQE is created; the total CQE is used to record the command execution results corresponding to each SQE;

[0069] S13: According to the order of the SQEs in the SQ queue, parse each SQE to obtain a corresponding command and execute it to obtain a corresponding command execution result;

[0070] S14: Record all command execution results in the total CQE;

[0071] S15: Return the total CQE to the host side and write it into a CQ queue; the CQ queue is used to store the single CQE or total CQE generated by the NVMe device processing the SQE, and the CQ queue corresponds to the SQ queue.

[0072] When the host writes an SQE to be executed by the NVMe device to the SQ queue, there are two situations: one is a single SQE executed, and the other is a series of SQEs with a sequential execution relationship. For example, a complete data processing operation needs to be completed by multiple SQE commands. In the existing solution, the NVMe device controller reads and executes an SQE from the SQ queue each time, then records a single CQE and returns it to the host, writes it to the CQ queue, and then reads the next SQE for processing.

[0073] In this embodiment, in order to speed up the command processing efficiency, the SQEs that need to be executed together with a relative order are used as aggregated SQEs. When the NVMe device controller reads the aggregated SQE from the SQ queue of the host side, it adopts a one-time reading method of multiple aggregated SQEs, processes multiple aggregated SQEs together, and creates a total CQE based on all the aggregated SQEs read this time. According to the reading order of each SQE, the SQE is parsed to obtain the corresponding command, and each command is executed in the order of reading to obtain the corresponding command execution result, which is recorded in the total CQE. Finally, the total CQE is returned to the host side and written to the CQ queue. The host side reads the total CQE in the CQ queue, so as to view the execution results of multiple SQE commands at one time.

[0074] In this embodiment, the command processing efficiency is improved by reading multiple CQEs at one time and executing them sequentially. A CQE is uniformly returned to the host side for each read of multiple SQEs, thereby reducing the frequency and data volume of CQEs returned to the host side. Correspondingly, the frequency and data volume of CQEs read by the host side from the CQ queue are also reduced accordingly, thereby saving the system's computing resources, improving data processing efficiency, and enhancing the overall performance of the system.

[0075] Based on the same inventive concept, an embodiment of the present application provides a method for an NVMe device to communicate with a host. Figure 3 This is the second flow chart of the method for NVMe device and host communication proposed in one embodiment of the present application. Figure 3 As shown, the method is applied to the host side, including:

[0076] S21: Create an SQ queue and a corresponding CQ queue; the SQ queue is used to store a single SQE or aggregate SQE that the NVMe device controller needs to process; the CQ queue is used to store a single CQE or total CQE generated by the NVMe device processing SQE;

[0077] S22: Generate a corresponding SQE based on at least one command that needs to be executed by the NVMe device controller, and write all SQEs into the SQ queue in the execution order of the corresponding commands; wherein any SQE is a single SQE or an aggregate SQE in an aggregate SQE group;

[0078] S23: Read the CQE written by the NVMe device controller from the CQ queue, parse the CQE to obtain a command execution result corresponding to at least one SQE; the CQE is a total CQE or a single CQE.

[0079] In this embodiment, when the host creates an SQ queue and a CQ queue, it is created in a corresponding manner, that is, one SQ queue corresponds to one CQ queue, or multiple SQ queues correspond to one CQ queue. When creating an SQE that needs to be processed by the NVMe device controller, a single SQE or an aggregated SQE is created as needed, and multiple aggregated SQEs that need to be executed together in one operation are generated into an aggregated SQE group. The created SQE is written into the SQ queue, waiting for the NVMe device controller to read and process it. After writing the SQ queue, the SQ Tail Doorbell register in the NVMe device controller is updated to point to the end position of the SQ queue to be processed by the current NVMe device controller.

[0080] After the NVMe device controller completes the processing, it generates a corresponding single CQE or total CQE, returns it to the host, writes it to the CQ queue corresponding to the SQ queue, and waits for the host to read it. For the processing result of a single SQE, the NVMe device controller will generate a single CQE and return it accordingly. For the processing result of an aggregate SQE, the NVMe device controller will generate a total CQE and return it according to the multiple aggregate SQEs executed in one processing.

[0081] In order to distinguish between a single SQE and an aggregate SQE, the data structure of the SQE is modified in this embodiment. The bit width occupied by the Fuse field is expanded based on the original SQE data structure. The data structure of the aggregate SQE is shown in Table 1 below.

[0082] Table 1

[0083]

[0084] In the SQE structure, the Command Identifier field is used to uniquely identify an SQE command in an SQ queue;

[0085] The Fuse (aggregate identifier) ​​field occupies 2 bits in the cause data structure, specifically DW0: bit9-bit8. In this embodiment, the length of the Fuse field is expanded, and the number of bits of the Fuse field is expanded to 6 bits, specifically DW0: bit13-bit8. An aggregate identifier is used to represent an aggregate SQE or a single SQE. 000000 is used to represent a non-aggregate command (single SQE), 000001 represents an aggregate SQE command 1, 000010 represents an aggregate SQE command 2, and so on. For example, 010000 represents an aggregate SQE command 16. By expanding the length of the aggregate identifier, the number of aggregate SQEs that the NVMe device controller can read at one time is increased;

[0086] Reserved is a reserved field, that is, an empty field;

[0087] The Command Specific field is a command-related field. The definition of this field is different for each different command.

[0088] In view of the fact that the existing CQE data structure cannot record the execution results of multiple SQE commands, in this embodiment, the existing single CQE data structure is modified to obtain the data structure of the total CQE. The modification is as follows:

[0089] (1) Compared with the original CQE structure, the Command Specific field, Status Field field and Command Identifier field are cancelled. The Command Specific field is used to record the error-related information of the failed command execution, and the Status Field (error code) field is used to mark the error type of the command;

[0090] (2) The SQ Identifier (queue identifier) ​​field, the SQ Head Pointer field, and the P (submission identifier) ​​field are retained;

[0091] (3) The Total Flag field and the Total Number field are added to record the number of SQEs corresponding to the CQE and to distinguish between the total CQE and the single CQE.

[0092] In this embodiment, the data structure of the total CQE is shown in Table 2 below.

[0093] Table 2

[0094]

[0095] The Total Flag (total CQE identifier) ​​field occupies 31 bits of DW1 and is used to mark whether the CQE is a total CQE or a single CQE. In this embodiment, 0 is used to represent the total CQE and 1 is used to represent the single CQE. In the total CQE, this field is 0;

[0096] The Total Number field is used to mark the total number of SQEs to be processed in this read, and this field occupies 23bit-16bit of DW1. For example, 00001000 means that the total number of SQE commands processed this time is 8.

[0097] The Fail Command (failure identifier) ​​field occupies 8 bits, specifically occupies 15bit-8bit of DW1, and is used to mark the command number of the SQE command that fails when the command fails to execute. For example, 00000100 means that the command fails when the 4th command is executed;

[0098] The SQ Identifier field is used to mark the SQ queues to which the multiple single SQEs or aggregated SQEs read this time belong. When there are multiple SQ queues corresponding to one CQ queue, this field is used to determine which specific SQ queue the command comes from;

[0099] The SQ Head Pointer field is used to inform the host side of the position of the SQE in the current SQ queue that has been processed, that is, the starting address of the first SQE read this time. Through the Total Number field and the SQ Head Pointer, the value of the SQ Head Pointer in the next total CQE or single CQE can be calculated. Since the size of each SQE is 64 bytes, the starting address sq_head_next of the next SQE read is calculated as:

[0100] sq_head_next=total_number*64+sq_head;

[0101] The P (submission identifier) ​​field is used to mark whether the CQE is newly submitted and whether it has been processed by the host. Through this field, the host can obtain the location of the Tail Doorbell register in the CQ;

[0102] Reserved is a reserved field, that is, an empty field.

[0103] As an implementation mode of the present application, based on the SQE to be processed this time, a total CQE is created, including:

[0104] Create a total CQE based on the total number of SQEs to be processed this time;

[0105] The total CQE records: the total CQE identifier, the total number of SQEs read this time, the queue identifier of the SQ queue to which the SQE read this time belongs, the submission identifier, and the starting address of the first SQE read this time.

[0106] In one embodiment, after the NVMe device controller reads multiple aggregate SQEs to be executed this time, it creates a corresponding total CQE to record the command execution results of the multiple aggregate SQE commands executed this time. When creating the total CQE, the Total Flag is set to 0, the Total Number field is set to the total number of aggregate SQEs to be executed this time, and the P field is set to an unprocessed state according to the SQ Identifier field corresponding to the currently read SQ queue record, and the current SQ HeadPointer field is calculated and recorded according to the starting address of the first SQE of the last read SQE and the total number of SQEs processed last time.

[0107] In addition, after reading multiple SQEs this time, the NVMe device controller also updates its own SQ HeadDoorbell register to point to the read position of the next SQE.

[0108] As an implementation manner of the present application, obtaining at least two SQEs from the SQ queue on the host side as the aggregated SQE to be processed this time includes:

[0109] Determine the total number of SQEs included in the aggregated SQE group to which the SQE belongs according to the SQE at the current read position in the SQ queue;

[0110] Compare the total number of the aggregated SQEs with a first threshold; if the total number of the aggregated SQEs is less than or equal to the first threshold, use the aggregated SQE group as the SQE to be processed this time;

[0111] When the total number of the aggregated SQEs is greater than the first threshold, starting from the SQE at the current read position, the aggregated SQEs of the first threshold are used as the SQEs to be processed this time.

[0112] In one embodiment, when reading an aggregate SQE in an SQ queue, the NVMe device controller needs to determine how many SQE commands are included in the aggregate SQE group to which the SQE belongs. In this application, each aggregate SQE in a process is marked by a Fuse field in the data structure of the aggregate SQE. Limited by the length of the Fuse field, the number of aggregate commands read by the NVMe device controller at one time cannot exceed the number range that can be represented by the Fuse field.

[0113] In this embodiment, a first threshold is set to limit the total number of aggregated SQEs read by the NVMe device controller at one time. According to the length setting of the Fuse field in this embodiment, the first threshold can be set to a maximum of no more than 32. . When reading an aggregated SQE, determine the total number of aggregated SQEs contained in the aggregated SQE group to which the aggregated SQE at the current read position belongs. If the total number of aggregated SQEs contained in the aggregated SQE group does not exceed the first threshold, all aggregated SQEs are read as the aggregated SQEs to be processed this time. For example, if the total number of aggregated SQEs contained in the aggregated SQE group is 12, which does not exceed the first threshold of 16, 12 aggregated SQEs are read as the SQEs to be processed this time.

[0114] Optionally, the Fuse field can be further extended to enable the NVMe device controller to support complex data operations containing more aggregation commands at one time. Using the reserved field of DW2 or DW3 in the SQE data structure as the Fuse field can greatly increase the number of aggregation commands processed at one time, further saving system resources.

[0115] If the total number of aggregate SQEs contained in the aggregate SQE group exceeds the first threshold, starting from the current read position, the aggregate SQEs of the first threshold are read as the aggregate SQEs to be processed this time. For example, the total number of aggregate SQEs contained in the aggregate SQE group is 20, which exceeds the first threshold of 16, then 16 unique SQEs are read for processing this time, and the remaining 4 aggregate SQEs are read for processing next time. It is worth noting that when reading SQE, the aggregate SQE and the single SQE are not read at the same time, so as to avoid the existence of the command execution results of the aggregate SQE command and the single SQE command in the total CQE returned to the host side at one time, which makes it difficult for the host side to distinguish and reduces the processing efficiency of the host side. That is, ensure that each time an SQE is processed, only the aggregate SQE is processed, or only the single SQE is processed.

[0116] In this embodiment, a corresponding first threshold is set based on the bit width of the Fuse field, and the number of SQEs read each time is limited by the first threshold, thereby ensuring that after each execution of the SQE command to be processed, a total CQE with a unified format is generated, which is convenient for host-side reading and processing.

[0117] As an implementation mode of the present application, based on at least one command that needs to be executed by the NVMe device controller, a corresponding SQE is generated, including:

[0118] In a case where the plurality of commands have a relative order, generating at least one aggregated SQE group based on the plurality of commands;

[0119] Record in each aggregate SQE: an SQE identifier and an aggregate identifier; the SQE identifier is used to uniquely indicate a command corresponding to the aggregate SQE; the aggregate identifier is used to indicate the sequence number of the aggregate SQE in the aggregate SQE group to which it belongs;

[0120] All aggregated SQEs are written to the SQ queue in the relative order.

[0121] As an implementation manner of the present application, generating at least one aggregated SQE group based on the multiple commands includes:

[0122] comparing the number of the plurality of commands to a second threshold;

[0123] If the number of the plurality of commands is less than or equal to the second threshold, generating an aggregate SQE group based on all commands;

[0124] In the case that the number of the plurality of commands is greater than the second threshold, a plurality of aggregated SQE groups are generated based on all the commands; wherein the total number of aggregated SQEs in each aggregated SQE group is not greater than the second threshold.

[0125] In one embodiment, when creating an SQE, the host creates multiple aggregate SQEs for multiple commands with relative order. When creating an aggregate SQE group, the host limits the number of aggregate SQEs that can be created at one time, that is, the number of aggregate SQEs included in an aggregate SQE group, by a second threshold. In practical applications, the second threshold can be set according to the number of commands included in a certain type of high-frequency data operation on the host. When the number of commands exceeds the second threshold, multiple aggregate SQE groups need to be created accordingly.

[0126] In this embodiment, the second threshold value may be the same as the first threshold value, or may be different from the first threshold value. When the second threshold value is less than or equal to the first threshold value, the number of aggregated SQEs contained in the aggregated SQE group pre-created by the host side satisfies the number range of command execution results that can be recorded in the total CQE, so that the NVMe device controller does not need to be divided again when reading the aggregated SQE, and can quickly process all SQE commands in an aggregated SQE group, thereby speeding up the data processing efficiency of the NVMe device controller. When the second threshold value is greater than the first threshold value, the NVMe device controller also needs to perform a secondary division of the group of aggregated SQE groups according to the first threshold value when reading the aggregated SQE, so as to meet the range of the number of commands that can be recorded in a total CQE.

[0127] As an implementation mode of the present application, it also includes:

[0128] After each command is executed, determine whether the current command execution result is successful or failed;

[0129] If the current command execution result is successful, perform the following steps: determine whether all commands corresponding to the SQEs have been executed; if there are unexecuted commands, continue to execute the next command; if all commands corresponding to the SQEs have been executed and all command execution results are successful, set the failure identifier of the total CQE to null; return the total CQE to the host end and write it into the CQ queue;

[0130] When the current command execution result is a failure, perform the following steps: stop executing the next command; obtain the aggregate identifier of the SQE corresponding to the command that currently failed to execute; based on the aggregate identifier, record the corresponding failure identifier in the total CQE; based on the SQE corresponding to the command that currently failed to execute, create a corresponding single CQE; record in the single CQE: error association information, the queue identifier of the SQ queue to which the SQE belongs, the starting address of the SQE, the error code, the submission identifier and the SQE identifier; return the total CQE and the single CQE to the host side, and write them into the CQ queue.

[0131] In one embodiment, when processing all SQEs read this time, each time an SQE command is executed, the execution result of the command is detected to determine whether the current command execution result is successful or failed. According to the current command execution result, subsequent operations are determined to record the total CQE of this processing.

[0132] Figure 2 FIG. 1 is a flowchart of processing host commands in one embodiment of the present application. Figure 2 As shown, the NVMe device controller obtains multiple aggregated SQEs from the SQ queue on the host side, and then creates a corresponding total CQE. The multiple aggregated SQEs obtained this time are parsed to obtain the corresponding SQE commands, and then executed in sequence. In the process of executing SQE commands, after each command is executed, the current command execution result is checked. If the current command execution result is successful, it is further determined whether all SQE commands have been executed. If there are unexecuted SQE commands, the next command will be executed until all commands are executed.

[0133] During the execution process, if the current command execution result is detected as a failure, the execution of the next command will be stopped. Since the SQE command is aggregated with multiple commands in a relative order, if any of the commands fails to execute, there is no need to execute subsequent commands.

[0134] In this embodiment, when all SQE commands are executed and the command execution results are all successful, the Failed Command (failure identifier) ​​field in the main CQE is set to empty, and the total CQE is returned to the host side. In the case of an SQE command execution interruption, the Fuse (aggregate identifier) ​​field in the SQE that currently fails to execute is recorded, that is, the sequence number of the command that is currently interrupted is marked. Get the value of the Fuse (aggregate identifier) ​​field (for example, 001000) and fill it in the FailCommand (failure identifier) ​​field in the total CQE. In addition, since the command execution result is a failed command, the host side needs to obtain more specific information, so for the command that is currently interrupted, a single CQE must be created accordingly. In this embodiment, the data structure of the single CQE is shown in Table 3 below.

[0135] Table 3

[0136]

[0137] In this embodiment, in a single CQE structure, the Command Specific (error association information) field is a command-associated field, and the definition of this field is different for each different command;

[0138] The Total Flag (total CQE identifier) ​​field occupies 31 bits of DW1 and is used to mark whether the CQE is a total CQE or a single CQE. In this embodiment, 0 is used to represent the total CQE and 1 is used to represent the single CQE.

[0139] In single CQE, this field is 1;

[0140] The SQ Identifier field is used to mark the SQ queues to which the multiple single SQEs or aggregated SQEs read this time belong;

[0141] The SQ Head Pointer (SQE starting address) field is used to inform the host of the SQE starting address;

[0142] The Status Field (error code) field is used to identify the command execution result. When this field is 0x00h, it means that the command execution result is successful and the host does not need to perform additional processing. In this embodiment, when a single CQE is generated for an SQE whose command execution result is a failure, this field is the error code corresponding to the specific error cause;

[0143] The P field is used to mark whether the CQE is newly submitted and whether the host has processed it. Through this field, the host can obtain the location of the Tail Doorbell in the CQ;

[0144] The Command Identifier field is used to uniquely identify an SQE command in an SQ queue. The host can determine the source of the currently executed command by reading the Command Identifier field and combining it with the SQ Identifier field in the CQE.

[0145] Reserved is a reserved field, that is, an empty field.

[0146] In the case where the execution of commands corresponding to the multiple SQEs read this time is interrupted, the data packet returned to the host side consists of a total CQE and a single CQE corresponding to the command that failed to execute. After the NVMe device controller stops executing the next SQE command, it records the total CQE and generates the single CQE that failed to execute currently, then returns the total CQE and the single CQE to the host side and writes them into the CQ queue.

[0147] In addition, after writing to the CQ queue, the NVMe device controller updates the CQ Tail Doorbell register. The host updates the CQ Head Doorbell register after reading the total CQE or single CQE in the CQ queue.

[0148] In this embodiment, when the command corresponding to any SQE among the multiple aggregated SQEs processed this time fails to execute, the corresponding total CQE is recorded and a single CQE corresponding to the failed command is additionally generated, thereby informing the host side of detailed processing information, which facilitates the host side to troubleshoot the fault.

[0149] In one embodiment, when there are multiple consecutive single SQEs in the SQ queue, the multiple consecutive single SQEs in the SQ queue are read according to the first threshold, and a corresponding second total CQE is generated. In one embodiment, the multiple consecutive single SQEs are regarded as an aggregated CQE, and the command execution results of all single SQEs are recorded in the second total CQE.

[0150] In this embodiment, when multiple consecutive single SQEs are read as the SQEs to be executed this time, each SQE is parsed to obtain the corresponding command, and the commands of all single SQEs are executed in the order of reading the SQ queue, and the corresponding command execution results are obtained. Different from the processing process of multiple aggregated SQEs, in the process of executing multiple single SQE commands, no matter whether the current command execution result is successful or failed, the next command will continue to be executed until all the single SQEs read this time are processed. The command execution results (successful or failed) of all single SQEs are recorded in the second total CQE.

[0151] The data structure of the second total CQE for multiple single SQEs is different from the data structure of the total CQE for multiple aggregated SQEs in that the Fail Command (failure identifier) ​​in the data structure of the second total CQE is empty, and a new field (such as Command Result) is used at the DW0 position to mark the command execution results of each single SQE. Specifically, each bit in the new field is marked with 0 or 1 to mark the command execution result of a corresponding single SQE. In actual applications, the marking method can be set as needed. For example, setting 0 indicates success and 1 indicates failure.

[0152] Optionally, in this embodiment, the bit width of DW0 is determined according to the size of the first threshold. For example, when the first threshold is 16, bit31-bit16 in DW0 are occupied to record the command execution results of each single SQE.

[0153] In addition, for each single SQE whose command execution result is failed in the multiple single SQEs executed this time, a single CQE is generated accordingly, and its data structure is consistent with the above Table 3. The second total CQE and the multiple single CQEs are returned to the host side, and the multiple single CQEs are written into the CQ queue according to the command execution order.

[0154] In this embodiment, by reading multiple consecutive single SQEs and recording a corresponding second total CQE, the processing flow of consecutive single SQEs is optimized, the frequency and amount of transmission data of generating a single CQE corresponding to each single SQE and returning to the host end are reduced, the system computing resources are further saved, and the data processing efficiency is improved.

[0155] Based on the same inventive concept, an embodiment of the present application provides a device for communicating between an NVMe device and a host. Figure 4 , Figure 4 FIG. 1 is one of the schematic diagrams of the apparatus for communicating between an NVMe device and a host proposed in one embodiment of the present application. Figure 4 As shown, the device 100 includes:

[0156] The first reading module 101 is configured to obtain at least two SQEs from the SQ queue on the host side as the aggregated SQE to be processed this time; the SQ queue is used to store the single SQE or aggregated SQE that the NVMe device controller needs to process; the aggregated SQE is at least two SQEs that need to be executed together with a relative order;

[0157] The first recording module 102 is configured to create a total CQE based on the SQE to be processed this time; the total CQE is used to record the command execution results corresponding to each SQE;

[0158] The first processing module 103 parses each SQE according to the order of the SQEs in the SQ queue to obtain a corresponding command and executes the command to obtain a corresponding command execution result;

[0159] The first recording module 102 is further configured to record all command execution results in the total CQE;

[0160] The first writing module 104 is configured to return the total CQE to the host side and write it into a CQ queue; the CQ queue is used to store the single CQE or total CQE generated by the NVMe device processing the SQE, and the CQ queue corresponds to the SQ queue.

[0161] As an implementation manner of the present application, the first reading module 101 is configured to obtain at least two SQEs from the SQ queue of the host side as the aggregated SQE to be processed this time, specifically including:

[0162] Determine the total number of SQEs included in the aggregated SQE group to which the SQE belongs according to the SQE at the current read position in the SQ queue;

[0163] Compare the total number of the aggregated SQEs with a first threshold; if the total number of the aggregated SQEs is less than or equal to the first threshold, use the aggregated SQE group as the SQE to be processed this time;

[0164] When the total number of the aggregated SQEs is greater than the first threshold, starting from the SQE at the current read position, the aggregated SQEs of the first threshold are used as the SQEs to be processed this time.

[0165] As an implementation manner of the present application, the first recording module 102 is configured to create a total CQE based on the SQE to be processed this time, specifically including:

[0166] Create a total CQE based on the total number of SQEs to be processed this time;

[0167] The total CQE records: the total CQE identifier, the total number of SQEs read this time, the queue identifier of the SQ queue to which the SQE read this time belongs, the submission identifier, and the starting address of the first SQE read this time.

[0168] As an implementation manner of the present application, the first processing module is further configured to determine whether the current command execution result is successful or failed after each command is executed;

[0169] In the case where the current command execution result is successful, the first processing module 103 is further configured to determine whether all commands corresponding to the SQEs are executed; if there are unexecuted commands, continue to execute the next command; the first recording module 102 is further configured to set the failure identifier of the total CQE to null when all commands corresponding to the SQEs are executed and all command execution results are successful; the first writing module 104 is further configured to return the total CQE to the host end and write it into the CQ queue;

[0170] When the current command execution result is a failure, the first processing module 103 is also configured to stop executing the next command; the first recording module 102 is also configured to obtain the aggregate identifier of the SQE corresponding to the command that currently failed to execute; according to the aggregate identifier, the corresponding failure identifier is recorded in the total CQE; according to the SQE corresponding to the command that currently failed to execute, a corresponding single CQE is created; the single CQE records: error association information, the queue identifier of the SQ queue to which the SQE belongs, the starting address of the SQE, the error code, the submission identifier and the SQE identifier; the first writing module 104 is also configured to return the total CQE and the single CQE to the host end, and write them into the CQ queue.

[0171] Based on the same inventive concept, an embodiment of the present application provides a device for communicating between an NVMe device and a host. Figure 5 , Figure 5 This is a second schematic diagram of a device for communicating between an NVMe device and a host proposed in an embodiment of the present application. Figure 5 As shown, the device 200 includes:

[0172] The queue creation module 201 is configured to create an SQ queue and a corresponding CQ queue; the SQ queue is used to store a single SQE or an aggregate SQE that the NVMe device controller needs to process; the CQ queue is used to store a single CQE or a total CQE generated by the NVMe device processing the SQE;

[0173] The second writing module 202 is configured to generate a corresponding SQE based on at least one command that needs to be executed by the NVMe device controller, and write all SQEs into the SQ queue in the execution order of the corresponding commands; wherein any SQE is a single SQE or an aggregate SQE in an aggregate SQE group;

[0174] The second reading module 203 is configured to read the CQE written by the NVMe device controller from the CQ queue, parse the CQE to obtain a command execution result corresponding to at least one SQE; the CQE is a total CQE or a single CQE.

[0175] As an implementation manner of the present application, the second writing module 202 is configured to generate a corresponding SQE based on at least one command that needs to be executed by the NVMe device controller, specifically including:

[0176] In a case where the plurality of commands have a relative order, generating at least one aggregated SQE group based on the plurality of commands;

[0177] Record in each aggregate SQE: an SQE identifier and an aggregate identifier; the SQE identifier is used to uniquely indicate a command corresponding to the aggregate SQE; the aggregate identifier is used to indicate the sequence number of the aggregate SQE in the aggregate SQE group to which it belongs;

[0178] All aggregated SQEs are written to the SQ queue in the relative order.

[0179] As an implementation manner of the present application, the second writing module 202 is configured to generate at least one aggregated SQE group based on the multiple commands, specifically including:

[0180] comparing the number of the plurality of commands to a second threshold;

[0181] If the number of the plurality of commands is less than or equal to the second threshold, generating an aggregate SQE group based on all commands;

[0182] In the case that the number of the plurality of commands is greater than the second threshold, a plurality of aggregated SQE groups are generated based on all the commands; wherein the total number of aggregated SQEs in each aggregated SQE group is not greater than the second threshold.

[0183] Based on the same inventive concept, an embodiment of the present application provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps in the method of communication between an NVMe device and a host as described in any of the above embodiments of the present application are implemented.

[0184] Based on the same inventive concept, an embodiment of the present application provides a readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the method of communication between an NVMe device and a host as described in any of the above embodiments of the present application are implemented.

[0185] Based on the same inventive concept, an embodiment of the present application provides an electronic device. Figure 6 is a schematic diagram of an electronic device proposed in an embodiment of the present application, such as Figure 6As shown, the electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps in the method for communication between the NVMe device and the host as described in any of the above embodiments of the present application are implemented.

[0186] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0187] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

[0188] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and components involved are not necessarily required by the present application.

[0189] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0190] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0191] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0192] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0193] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the present application is interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0194] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0195] The method, apparatus, device and storage medium for communicating between the NVMe device and the host provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for NVMe device to communicate with a host, characterized in that: Applicable to NVMe device controllers, including: Obtain at least two SQEs from the SQ queue on the host side as the aggregate SQE to be processed this time; the SQ queue is used to store the single SQE or aggregate SQE that the NVMe device controller needs to process; the aggregate SQE is at least two SQEs that need to be executed together with a relative order; Based on the SQE to be processed this time, a total CQE is created; the total CQE is used to record the command execution results corresponding to each SQE; According to the order of the SQEs in the SQ queue, parse each SQE to obtain a corresponding command and execute it to obtain a corresponding command execution result; Recording all command execution results in the total CQE; The total CQE is returned to the host side and written into the CQ queue; the CQ queue is used to store the single CQE or total CQE generated by the NVMe device processing the SQE, and the CQ queue corresponds to the SQ queue.

2. The method for NVMe device to communicate with a host according to claim 1, characterized in that: Get at least two SQEs from the host-side SQ queue as the aggregated SQEs to be processed this time, including: Determine the total number of SQEs included in the aggregated SQE group to which the SQE belongs according to the SQE at the current read position in the SQ queue; Compare the total number of the aggregated SQEs with a first threshold; if the total number of the aggregated SQEs is less than or equal to the first threshold, use the aggregated SQE group as the SQE to be processed this time; When the total number of the aggregated SQEs is greater than the first threshold, starting from the SQE at the current read position, the aggregated SQEs of the first threshold are used as the SQEs to be processed this time.

3. The method for NVMe device to communicate with a host according to claim 1, characterized in that: Based on the SQE to be processed this time, create a total CQE, including: Create a total CQE based on the total number of SQEs to be processed this time; The total CQE records: the total CQE identifier, the total number of SQEs read this time, the queue identifier of the SQ queue to which the SQE read this time belongs, the submission identifier, and the starting address of the first SQE read this time.

4. The method for NVMe device to communicate with a host according to claim 1, wherein: Also includes: After each command is executed, determine whether the current command execution result is successful or failed; If the current command execution result is successful, perform the following steps: determine whether all commands corresponding to the SQEs have been executed; if there are unexecuted commands, continue to execute the next command; if all commands corresponding to the SQEs have been executed and all command execution results are successful, set the failure identifier of the total CQE to null; return the total CQE to the host end and write it into the CQ queue; When the current command execution result is a failure, perform the following steps: stop executing the next command; obtain the aggregate identifier of the SQE corresponding to the command that currently failed to execute; based on the aggregate identifier, record the corresponding failure identifier in the total CQE; based on the SQE corresponding to the command that currently failed to execute, create a corresponding single CQE; record in the single CQE: error association information, the queue identifier of the SQ queue to which the SQE belongs, the starting address of the SQE, the error code, the submission identifier and the SQE identifier; return the total CQE and the single CQE to the host side, and write them into the CQ queue.

5. A method for NVMe device to communicate with a host, characterized in that: Applied to the host side, including: Create an SQ queue and a corresponding CQ queue; the SQ queue is used to store a single SQE or aggregate SQE that the NVMe device controller needs to process; the CQ queue is used to store a single CQE or total CQE generated by the NVMe device processing SQE; Based on at least one command that needs to be executed by the NVMe device controller, a corresponding SQE is generated, and all SQEs are written into the SQ queue in the execution order of the corresponding commands; wherein any SQE is a single SQE or an aggregate SQE in an aggregate SQE group; The CQE written by the NVMe device controller is read from the CQ queue, and the CQE is parsed to obtain a command execution result corresponding to at least one SQE; the CQE is a total CQE or a single CQE.

6. The method for NVMe device to communicate with a host according to claim 5, characterized in that: Based on at least one command that needs to be executed by the NVMe device controller, a corresponding SQE is generated, including: In a case where the plurality of commands have a relative order, generating at least one aggregated SQE group based on the plurality of commands; Record in each aggregate SQE: an SQE identifier and an aggregate identifier; the SQE identifier is used to uniquely indicate a command corresponding to the aggregate SQE; the aggregate identifier is used to indicate the sequence number of the aggregate SQE in the aggregate SQE group to which it belongs; All aggregated SQEs are written to the SQ queue in the relative order.

7. The method for NVMe device to communicate with a host according to claim 6, characterized in that: Generating at least one aggregated SQE group based on the plurality of commands includes: comparing the number of the plurality of commands to a second threshold; If the number of the plurality of commands is less than or equal to the second threshold, generating an aggregate SQE group based on all commands; In the case that the number of the plurality of commands is greater than the second threshold, a plurality of aggregated SQE groups are generated based on all the commands; wherein the total number of aggregated SQEs in each aggregated SQE group is not greater than the second threshold.

8. An apparatus for communicating between an NVMe device and a host, characterized in that: The method for implementing any one of claims 1 to 4 comprises: The first reading module is configured to obtain at least two SQEs from the SQ queue on the host side as the aggregate SQE to be processed this time; the SQ queue is used to store the single SQE or aggregate SQE that the NVMe device controller needs to process; the aggregate SQE is at least two SQEs that need to be executed together with a relative order; A first recording module is configured to create a total CQE based on the SQE to be processed this time; the total CQE is used to record the command execution results corresponding to each SQE; The first processing module parses each SQE according to the order of the SQEs in the SQ queue to obtain a corresponding command and executes it to obtain a corresponding command execution result; The first recording module is further configured to record all command execution results in the total CQE; The first writing module is configured to return the total CQE to the host side and write it into a CQ queue; the CQ queue is used to store the single CQE or total CQE generated by the NVMe device processing the SQE, and the CQ queue corresponds to the SQ queue.

9. An apparatus for communicating between an NVMe device and a host, characterized in that: The method for implementing any one of claims 5 to 7 comprises: A queue creation module is configured to create an SQ queue and a corresponding CQ queue; the SQ queue is used to store a single SQE or an aggregate SQE that the NVMe device controller needs to process; the CQ queue is used to store a single CQE or a total CQE generated by the NVMe device processing the SQE; The second writing module is configured to generate a corresponding SQE based on at least one command that needs to be executed by the NVMe device controller, and write all SQEs into the SQ queue in the execution order of the corresponding commands; wherein any SQE is a single SQE or an aggregate SQE in an aggregate SQE group; The second reading module is configured to read the CQE written by the NVMe device controller from the CQ queue, parse the CQE to obtain a command execution result corresponding to at least one SQE; the CQE is a total CQE or a single CQE.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method described in any one of claims 1 to 4 or the steps in the method described in any one of claims 5 to 7 are implemented.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements the method according to any one of claims 1 to 4, or the steps in the method according to any one of claims 5 to 7.

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