Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device which comprises a substrate, a semiconductor channel layer and a first dielectric layer which are sequentially arranged from bottom to top, the semiconductor device further comprises a source electrode, a drain electrode and a gate electrode, and the source electrode and the drain electrode are arranged at intervals, penetrate through the first dielectric layer and are in contact connection with the semiconductor channel layer; a second dielectric layer is further arranged on the first dielectric layer, the gate electrode penetrates through the second dielectric layer and is in contact connection with the first dielectric layer, the gate electrode is in a closed ring shape, and the projection of the gate electrode in the vertical direction surrounds the projection of the source electrode or the drain electrode in the vertical direction. The semiconductor device does not need to be manufactured by adopting an ion implantation process, the cost is lower, in addition, the gate electrode is designed to be in a closed ring shape, and the projection of the gate electrode in the vertical direction surrounds the projection of the source electrode or the drain electrode in the vertical direction, so that the source electrode or the drain electrode in the gate electrode is prevented from leaking current, and the reliability of the semiconductor device is improved. And the performance of the semiconductor device is better.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The third-generation semiconductor materials represented by gallium nitride (GaN) and its alloys are new semiconductor materials that have received much attention internationally in the past decade. They have many excellent properties such as large bandgap, high electron saturation drift velocity, small dielectric constant, good thermal conductivity, stable structure, etc., and have great application prospects in the field of power devices.

[0003] Power devices usually include one or more field-effect transistors. The process of manufacturing transistors on third-generation semiconductors is more difficult than on traditional semiconductor materials, especially the ion implantation process is complex and costly. How to form power devices on third-generation semiconductors at a relatively acceptable cost is currently at the forefront of industry exploration.

[0004] Ion implantation is a process that accelerates an ion beam with a certain energy and then injects it into the surface of a solid material (such as a semiconductor) to change the physical properties of the surface of the material. In the manufacture of field effect transistors, ion implantation is an important means to achieve precise doping and form channel functional areas.

[0005] Ion implantation requires the use of dedicated ion implantation equipment in the manufacture of field effect transistors. The ion implantation equipment is expensive, and the ion target materials used are also expensive, accounting for a large share of the cost in the manufacture of field effect transistors.

[0006] How to realize the function of field effect transistor by using general process is disclosed by the present invention. Summary of the invention

[0007] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem in the prior art that the semiconductor device manufacturing requires an ion implantation process resulting in high cost and the problem that the source electrode and the drain electrode are prone to current leakage.

[0008] In order to achieve the above-mentioned purpose, the present invention provides a semiconductor device, comprising a substrate, a semiconductor channel layer and a first dielectric layer arranged in sequence from bottom to top, the semiconductor device also comprising a source electrode, a drain electrode and a gate electrode, the source electrode and the drain electrode are arranged at intervals and both pass through the first dielectric layer and are in contact with and connected to the semiconductor channel layer; a second dielectric layer is also provided on the first dielectric layer, the gate electrode passes through the second dielectric layer and is in contact with and connected to the first dielectric layer, the gate electrode is in a closed ring shape, and the projection of the gate electrode in the up and down directions surrounds the projection of the source electrode or the drain electrode in the up and down directions.

[0009] Preferably, a first opening and a second opening arranged at intervals are provided on the first dielectric layer, the first opening and the second opening extend downward to the upper surface of the semiconductor channel layer, the first opening is filled with one of the source electrode and the drain electrode and one of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer, and the second opening is filled with the other of the source electrode and the drain electrode and the other of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer.

[0010] Preferably, the first opening is a T-shaped structure, the second opening is a long strip structure, the first opening is arranged on at least one side of the second opening and the first opening includes a first opening extending toward the second opening and a second opening connected to the first opening, and the second opening is connected to a side of the first opening away from the second opening.

[0011] Preferably, there are two first openings, and the two first openings are respectively arranged on both sides of the second opening and the two first openings are arranged opposite to each other.

[0012] Preferably, a first groove is provided on the second dielectric layer, the first groove extends downward to the upper surface of the first dielectric layer, a second groove is provided on the first dielectric layer corresponding to the first groove, the second groove extends to the interior of the first dielectric layer and does not penetrate the first dielectric layer, the second groove is spaced apart from the first opening and the second opening, the horizontal dimension of the second groove is smaller than the horizontal dimension of the first groove so that the first groove and the second groove form a step groove, the step groove is filled with the gate electrode, and the gate electrode extends to the upper surface of the second dielectric layer.

[0013] Preferably, the first groove is a closed ring shape, the projection of the first groove in the vertical direction surrounds the projection of the second opening in the vertical direction and the projection of the first groove in the vertical direction is located between the projections of the two first openings in the vertical direction; the second groove is a closed ring shape, and the projection of the second groove in the vertical direction is located in the projection of the first groove in the vertical direction.

[0014] Preferably, the first groove includes a first U-shaped groove and a first annular groove, the first annular groove is disconnected from the first U-shaped groove on one side to be connected to the two ends of the first U-shaped groove, the projection of the first U-shaped groove in the up and down directions surrounds the projection of the second opening in the up and down directions and the projection of the first U-shaped groove in the up and down directions is located between the projections of the two first openings in the up and down directions; the second groove includes a second U-shaped groove and a second annular groove, the second annular groove is disconnected from the second U-shaped groove on one side to be connected to the two ends of the second U-shaped groove.

[0015] Preferably, a third opening is further provided on the second dielectric layer, the third opening is connected to the first U-shaped groove, the third opening is arranged opposite to the first annular groove and is respectively located on both sides of the first U-shaped groove, the third opening is filled with a gate pad, and the gate pad is electrically connected to the gate electrode.

[0016] Preferably, a third dielectric layer is further provided on the second dielectric layer, and an opening is provided on the third dielectric layer corresponding to the gate pad to expose the gate pad.

[0017] Preferably, a fourth opening is provided on the third dielectric layer corresponding to the source electrode and a fifth opening is provided on the third dielectric layer corresponding to the drain electrode, the fourth opening is filled with a source pad, the source pad is electrically connected to the source electrode, the fifth opening is filled with a drain pad, the drain pad is electrically connected to the drain electrode, and the tops of the source pad and the drain pad are both higher than the top of the gate pad.

[0018] Preferably, the third dielectric layer is provided with a sixth opening corresponding to the source electrode and the third dielectric layer is provided with a seventh opening corresponding to the drain electrode, the sixth opening is filled with a source pad, the source pad is electrically connected to the source electrode, the seventh opening is filled with a first drain sub-pad, the first drain sub-pad is electrically connected to the drain electrode, a fourth dielectric layer is further provided on the third dielectric layer, an eighth opening is provided on the fourth dielectric layer corresponding to the first drain sub-pad, the eighth opening is filled with a second drain sub-pad, the first drain sub-pad and the second drain sub-pad are stacked and form the drain pad, the drain pad is electrically connected to the drain electrode, the source pad and the drain pad have tops higher than the top of the gate pad, and the drain pad has a top higher than the source pad.

[0019] Preferably, when the source electrode is filled in the second opening, the projection of the source pad in the up and down directions is located inside the first annular groove; when the drain electrode is filled in the second opening, the projection of the drain pad in the up and down directions is located inside the first annular groove.

[0020] Preferably, when the drain electrode is filled in the first opening, the drain pad is arranged corresponding to the drain electrode and there are four drain pads; when the source electrode is filled in the first opening, the source pad is arranged corresponding to the source electrode and there are four source pads.

[0021] Preferably, the substrate is a silicon-based substrate, a sapphire substrate, a gallium nitride single crystal substrate or a gallium nitride composite substrate, the semiconductor channel layer includes a gallium nitride layer and an aluminum gallium nitride layer, and the connection interface between the gallium nitride layer and the aluminum gallium nitride layer forms a two-dimensional electron gas layer.

[0022] Preferably, the first dielectric layer is made of silicon nitride, the source electrode and the drain electrode are both a stacked composite structure of four metal layers of titanium / aluminum / nickel / gold, and the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all made of silicon dioxide.

[0023] Preferably, a passivation layer is further provided on the fourth dielectric layer, and openings are respectively provided on the passivation layer corresponding to the source pad, the drain pad and the gate pad to expose the source pad, the drain pad and the gate pad.

[0024] The present invention also provides a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate; growing a semiconductor channel layer on the substrate; forming a first dielectric layer on the semiconductor channel layer, and patterning the first dielectric layer to form a plurality of opening areas; forming a first metal layer in the first dielectric layer and the plurality of opening areas, the first metal layer being used to form a source electrode and a drain electrode that are spaced apart and in contact with the semiconductor channel layer; forming a second dielectric layer on the first dielectric layer, the source electrode, and the drain electrode, and patterning the second dielectric layer to form a groove; forming a second metal layer in the second dielectric layer and the groove, the second metal layer being used to form a gate electrode, the gate electrode being in a closed ring shape, the projection of the gate electrode in the up and down directions surrounding the projection of the source electrode or the drain electrode in the up and down directions.

[0025] Preferably, the plurality of opening areas include a first opening and a second opening that are spaced apart, the first opening and the second opening extending downward to the upper surface of the semiconductor channel layer, the first metal layer at the first opening forming one of the source electrode and the drain electrode, and the first metal layer at the second opening forming the other of the source electrode and the drain electrode.

[0026] Preferably, the first opening is a T-shaped structure, the second opening is a long strip structure, the first opening is arranged on at least one side of the second opening and the first opening includes a first opening extending toward the second opening and a second opening connected to the first opening, and the second opening is connected to a side of the first opening away from the second opening.

[0027] Preferably, there are two first openings, and the two first openings are respectively arranged on both sides of the second opening and the two first openings are arranged opposite to each other.

[0028] Preferably, a first metal layer is formed in the first dielectric layer and the plurality of opening regions, and the first metal layer is used to form source electrodes and drain electrodes that are spaced apart and in contact with the semiconductor channel layer. The steps include: sputtering a first metal in the first dielectric layer, the first opening, and the second opening to form the first metal layer; etching the first metal layer by photolithography and etching processes to form source electrodes and drain electrodes that are spaced apart and in contact with the semiconductor channel layer, one of the source electrode and the drain electrode extending to the upper surface of the first dielectric layer, and the other of the source electrode and the drain electrode extending to the upper surface of the first dielectric layer; or, A first metal layer is formed in the dielectric layer and a plurality of opening areas, and the first metal layer forms source electrodes and drain electrodes that are spaced apart and in contact with the semiconductor channel layer, the steps comprising: using a first blocking layer to cover the area on the first dielectric layer where the source electrode and the drain electrode are not required to be set; sputtering a first metal in the first dielectric layer, the first opening, and the second opening where the first blocking layer is not set to form source electrodes and drain electrodes that are spaced apart and in contact with the semiconductor channel layer, one of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer, and the other of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer; and removing the first blocking layer.

[0029] Preferably, the groove includes a first groove, the first groove extends downward to the upper surface of the first dielectric layer, a second groove is also provided on the first dielectric layer corresponding to the first groove, the second groove extends to the interior of the first dielectric layer and does not penetrate the first dielectric layer, the second groove is spaced apart from the first opening and the second opening, the horizontal dimension of the second groove is smaller than the horizontal dimension of the first groove so that the first groove and the second groove form a step groove, the step groove is filled with the gate electrode, and the gate electrode extends to the upper surface of the second dielectric layer.

[0030] Preferably, the first groove is a closed ring shape, the projection of the first groove in the vertical direction surrounds the projection of the second opening in the vertical direction and the projection of the first groove in the vertical direction is located between the projections of the two first openings in the vertical direction; the second groove is a closed ring shape, and the projection of the second groove in the vertical direction is located in the projection of the first groove in the vertical direction.

[0031] Preferably, the first groove includes a first U-shaped groove and a first annular groove, the first annular groove is disconnected from the first U-shaped groove on one side to be connected to the two ends of the first U-shaped groove, the projection of the first U-shaped groove in the up and down directions surrounds the projection of the second opening in the up and down directions and the projection of the first U-shaped groove in the up and down directions is located between the projections of the two first openings in the up and down directions; the second groove includes a second U-shaped groove and a second annular groove, the second annular groove is disconnected from the second U-shaped groove on one side to be connected to the two ends of the second U-shaped groove.

[0032] Preferably, the step of patterning the second dielectric layer to form a groove includes: patterning the second dielectric layer to form a groove and a third opening, the third opening is connected to the first U-shaped groove, and the third opening is arranged opposite to the first annular groove and is respectively located on both sides of the first U-shaped groove.

[0033] Preferably, a second metal layer is formed in the second dielectric layer and the groove, and the second metal layer is used to form a gate electrode. The step includes: forming a second metal layer in the second dielectric layer, the groove and the third opening, and the second metal layer is used to form the gate electrode and the gate pad.

[0034] Preferably, a second metal layer is formed in the second dielectric layer, the groove and the third opening, and the second metal layer is used to form the gate electrode and the gate pad, including: sputtering a second metal in the second dielectric layer, the groove and the third opening to form a second metal layer, and etching the second metal layer through a photolithography or etching process to form the electrically connected gate electrode and the gate pad; or, a second metal layer is formed in the second dielectric layer, the groove and the third opening, and the second metal layer is used to form the gate electrode and the gate pad, including: using a second shielding layer to shield the area on the second dielectric layer where the gate electrode and the gate pad are not required; sputtering a second metal in the second dielectric layer, the groove and the third opening where the second shielding layer is not set to form the electrically connected gate electrode and the gate pad; removing the second shielding layer.

[0035] Preferably, a second metal layer is formed in the second dielectric layer, the groove and the third opening, and after the second metal layer is used to form the gate electrode and the gate pad, it also includes: forming a third dielectric layer on the second dielectric layer, the third dielectric layer covers the second dielectric layer and the gate electrode and the third dielectric layer does not cover the gate pad.

[0036] Preferably, after the step of forming a third dielectric layer on the second dielectric layer, it also includes: etching the third dielectric layer corresponding to the source electrode and the drain electrode to form a fourth opening and a fifth opening respectively; forming a third metal layer on the fourth opening, the fifth opening and the third dielectric layer; etching the third metal layer to form a source pad in the fourth opening and a drain pad in the fifth opening, the source pad is electrically connected to the source electrode, the drain pad is electrically connected to the drain electrode, and the tops of the source pad and the drain pad are both higher than the top of the gate pad.

[0037] Preferably, after the step of forming a third dielectric layer on the second dielectric layer, the method further includes: etching the third dielectric layer corresponding to the source electrode and the drain electrode to form a sixth opening and a seventh opening respectively; forming a third metal layer on the sixth opening, the seventh opening and the third dielectric layer; etching the third metal layer to form a source pad in the sixth opening and a first drain sub-pad in the seventh opening, the source pad being electrically connected to the source electrode, and the first drain sub-pad being electrically connected to the drain electrode; A fourth dielectric layer is formed on the fourth dielectric layer, an eighth opening is provided on the fourth dielectric layer corresponding to the first drain sub-pad; a fourth metal layer is formed in the fourth dielectric layer and the eighth opening; the fourth metal layer is etched to form a second drain sub-pad in the eighth opening, the first drain sub-pad and the second drain sub-pad are stacked and form the drain pad, the drain pad is electrically connected to the drain electrode, the source pad and the top of the drain pad are both higher than the top of the gate pad, and the top of the drain pad is higher than the top of the source pad.

[0038] Preferably, when the source electrode is filled in the second opening, the projection of the source pad in the up and down directions is located inside the first annular groove; when the drain electrode is filled in the second opening, the projection of the drain pad in the up and down directions is located inside the first annular groove.

[0039] Preferably, when the drain electrode is filled in the first opening, the drain pad is arranged corresponding to the drain electrode and there are four drain pads; when the source electrode is filled in the first opening, the source pad is arranged corresponding to the source electrode and there are four source pads.

[0040] Preferably, the fourth metal layer is etched to form a second drain sub-pad in the eighth opening, and after the first drain sub-pad and the second drain sub-pad are stacked and formed into the drain pad, a passivation layer is formed on the fourth dielectric layer, and openings are respectively provided on the passivation layer corresponding to the source pad, the drain pad and the gate pad to expose the source pad, the drain pad and the gate pad.

[0041] Compared with the prior art, the present invention does not need to adopt ion implantation process to manufacture semiconductor devices, and the cost is lower. In addition, by designing the gate electrode to be a closed ring, and the projection of the gate electrode in the vertical direction surrounds the projection of the source electrode or the drain electrode in the vertical direction, the electric field of the gate electrode affects the semiconductor channel switch. When the gate electrode is given an appropriate voltage, the semiconductor channel is opened or closed. On the other hand, the source electrode or the drain electrode located in the gate electrode is prevented from leaking current, and the performance of the semiconductor device is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic structural diagram of a substrate provided with a semiconductor channel layer according to the present invention.

[0043] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along line a.

[0044] Figure 3 It is a schematic diagram of the structure after the first opening and the second opening are arranged on the first dielectric layer of the present invention.

[0045] Figure 4 for Figure 3 Schematic diagram of the cross-sectional structure along line b.

[0046] Figure 5 It is a schematic diagram of the structure after the source electrode and the drain electrode are arranged at the first opening and the second opening of the present invention.

[0047] Figure 6 for Figure 5 Schematic diagram of the cross-sectional structure along line c.

[0048] Figure 7 This is a schematic diagram of the structure after the first groove is set in the second dielectric layer of the present invention.

[0049] Figure 8 for Figure 7 Schematic diagram of the cross-sectional structure along line d.

[0050] Fig. 9 For Figure 8 A schematic diagram of the structure after a second groove is set on the first dielectric layer based on the present invention.

[0051] Fig.10 It is a schematic diagram of the structure of providing gate electrodes at the first trench and the second trench of the present invention.

[0052] Fig.11 It is a schematic diagram of the structure after the sixth opening and the seventh opening are opened on the third dielectric layer according to the present invention.

[0053] Fig.12 It is a schematic structural diagram of forming a source electrode and a first drain sub-electrode at the sixth opening and the seventh opening of the present invention.

[0054] Fig.13 It is a schematic structural diagram of the present invention after the eighth opening is formed on the fourth dielectric layer.

[0055] Fig.14 It is a schematic structural diagram of forming a second drain sub-electrode at the eighth opening according to the present invention.

[0056] Fig.15 It is a schematic diagram of the structure after a passivation layer is provided on the fourth dielectric layer according to the present invention.

[0057] Fig.16 It is a schematic structural diagram of the semiconductor device of the present invention. DETAILED DESCRIPTION

[0058] In order to explain the technical content, structural features and achieved effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0059] like Figures 1 to 16As shown, an embodiment of the present invention provides a semiconductor device, including a substrate 1, a semiconductor channel layer 2 and a first dielectric layer 3 arranged in sequence from bottom to top, the semiconductor device also includes a source electrode 41, a drain electrode 42 and a gate electrode 61, the source electrode 41 and the drain electrode 42 are arranged at intervals and both pass through the first dielectric layer 3 and are in contact with and connected to the semiconductor channel layer 2; a second dielectric layer 5 is also provided on the first dielectric layer 3, the gate electrode 61 passes through the second dielectric layer 5 and is in contact with and connected to the first dielectric layer 3, the gate electrode 61 is in a closed ring shape, and the projection of the gate electrode 61 in the up and down directions surrounds the projection of the source electrode 41 or the drain electrode 42 in the up and down directions. Specifically, the semiconductor device of the embodiment of the present invention can be a D-Mode semiconductor device, the substrate 1 can be a silicon-based substrate, a sapphire substrate, a gallium nitride single crystal substrate, etc., the semiconductor channel layer 2 includes a gallium nitride layer 21 and an aluminum gallium nitride layer 22, the gallium nitride layer 21 is arranged below the aluminum gallium nitride layer 22, and the connection interface between the gallium nitride layer 21 and the aluminum gallium nitride layer 22 forms a two-dimensional electron gas layer. The function of the first dielectric layer 3 is to better transmit the electric field to the semiconductor channel layer 2 and isolate the current of the gate electrode 61, and play the role of a gate dielectric layer. In some other embodiments, the substrate 1 can also be a gallium nitride composite substrate, such as a composite substrate of sapphire and gallium nitride, that is, gallium nitride is deposited on a sapphire substrate to form a composite substrate. The specific type of the substrate 1 can be selected according to actual needs. In addition, in some other embodiments, the semiconductor device of the embodiment of the present invention can also be designed as an E-Mode semiconductor device.

[0060] In the embodiment of the present invention, the gate electrode 61 is designed to be a closed ring, and the projection of the gate electrode 61 in the vertical direction surrounds the projection of the source electrode 41 or the drain electrode 42 in the vertical direction, so that the electric field of the gate electrode 61 affects the switching of the semiconductor channel. When the gate electrode 61 is given an appropriate voltage, the semiconductor channel is opened or closed. On the other hand, the source electrode 41 or the drain electrode 42 located in the gate electrode 61 is prevented from leaking current, and the performance of the semiconductor device is better.

[0061] In the embodiment of the present invention, Figures 3 to 6As shown, the first dielectric layer 3 is provided with a first opening 31 and a second opening 32 which are spaced apart from each other. The first opening 31 and the second opening 32 extend downward to the upper surface of the semiconductor channel layer 2. The first opening 31 is filled with one of the source electrode 41 and the drain electrode 42, and one of the source electrode 41 and the drain electrode 42 extends to the upper surface of the first dielectric layer 3. The second opening 32 is filled with the other of the source electrode 41 and the drain electrode 42, and the other of the source electrode 41 and the drain electrode 42 extends to the upper surface of the first dielectric layer 3. Specifically, a first opening 31 and a second opening 32 are opened in an area where the source electrode 41 and the drain electrode 42 are to be made. The first opening 31 and the second opening 32 penetrate the first dielectric layer 3 so that the first opening 31 and the second opening 32 extend to the upper surface of the semiconductor channel layer 2, so that the source electrode 41 and the drain electrode 42 are respectively in contact with and connected to the aluminum gallium nitride layer 22 of the semiconductor channel layer 2. In the embodiment of the present invention, the source electrode 41 is filled in the first opening 31 and the drain electrode 42 is filled in the second opening 32. In some other specific embodiments, the drain electrode 42 can be filled in the first opening 31 and the source electrode 41 is correspondingly filled in the second opening 32. The material of the first dielectric layer 3 can be silicon nitride. The source electrode 41 and the drain electrode 42 are both a stacked composite structure of four metal layers of titanium / aluminum / nickel / gold. The stacked composite structure of four metal layers of titanium / aluminum / nickel / gold can fully contact and connect with the semiconductor channel layer 2, which can improve carrier diffusion, form a good ohmic contact, and effectively reduce contact resistance.

[0062] In the embodiment of the present invention, the first opening 31 is in a T-shaped structure, the second opening 32 is in a strip-shaped structure, the first opening 31 is provided on at least one side of the second opening 32, and the first opening 31 includes a first opening portion 311 extending toward the second opening 32 and a second opening portion 312 connected to the first opening portion 311, and the second opening portion 312 is connected to a side of the first opening portion 311 away from the second opening 32. Specifically, as Figure 3 As shown, there are two first openings 31 , which are respectively arranged on both sides of the second opening 32 and the two first openings 311 are arranged opposite to each other, so that the structure of the semiconductor device is very compact and the performance is better.

[0063] In the embodiment of the present invention, a first groove 51 is provided on the second dielectric layer 5, and the first groove 51 extends downward to the upper surface of the first dielectric layer 3. A second groove 33 is provided on the first dielectric layer 3 corresponding to the first groove 51, and the second groove 33 extends to the inside of the first dielectric layer 3 and does not penetrate the first dielectric layer 3. The second groove 33 is spaced from the first opening 31 and the second opening 32. The horizontal dimension of the second groove 33 is smaller than the horizontal dimension of the first groove 51 so that the first groove 51 and the second groove 33 form a step groove, and the step groove is filled with a gate electrode 61, and the gate electrode 61 extends to the upper surface of the second dielectric layer 5. Specifically, as Figure 3 as well as Figures 7 to 10 As shown, the first groove 51 is in a closed ring shape, and the projection of the first groove 51 in the vertical direction surrounds the projection of the second opening 32 in the vertical direction and the projection of the first groove 51 in the vertical direction is located between the projections of the two first openings 311 in the vertical direction; the second groove 33 is in a closed ring shape, and the projection of the second groove 33 in the vertical direction is located in the projection of the first groove 51 in the vertical direction. The step groove is more conducive to the attachment of the gate electrode 61, and the connection is more reliable. The material of the second dielectric layer 5 can be silicon dioxide. By setting the gate electrode 61 as a closed ring-shaped closed electrode, the closed ring-shaped electrode will not form an electric field when it is not powered. The semiconductor channel layer 2 forms a current-conducting channel due to the structure of the two-dimensional electron gas. At this time, the source and the drain are connected. When the gate electrode 61 is powered, the electric field of the gate electrode 61 destroys the conductive channel formed by the two-dimensional electron gas on the semiconductor channel layer 2, so that the source and the drain are cut off. Of course, in some other embodiments, the second groove 33 may not be provided, that is, only the first groove 51 is provided, and the function of the semiconductor device of the present invention can also be achieved.

[0064] In the embodiment of the present invention, the first groove 51 includes a first U-shaped groove 511 and a first annular groove 512. The first annular groove 512 is disconnected from the first U-shaped groove 511 on one side to connect with the two ends of the first U-shaped groove 511. The projection of the first U-shaped groove 511 in the vertical direction surrounds the projection of the second opening 32 in the vertical direction, and the projection of the first U-shaped groove 511 in the vertical direction is located between the projections of the two first openings 311 in the vertical direction. The second groove 33 includes a second U-shaped groove and a second annular groove. The second annular groove is disconnected from the second U-shaped groove on one side to connect with the two ends of the second U-shaped groove. Specifically, as Figures 7 and 8 As shown, by designing the first trench 51 to include a first U-shaped trench 511 and a first annular trench 512 , and designing the second trench 33 to include a second U-shaped trench and a second annular trench, the structure of the semiconductor device is made more compact.

[0065] In the embodiment of the present invention, a third opening is further provided on the second dielectric layer 5, the third opening is communicated with the first U-shaped groove 511, the third opening is arranged opposite to the first annular groove 512 and is respectively located at the front and rear sides of the first U-shaped groove 511, and the gate pad 62 is filled in the third opening, and the gate pad 62 is electrically connected to the gate electrode 61. Specifically, as Figures 7 to 10 As shown, the third opening can be connected to the first U-shaped groove 511 through the connecting groove, and the gate pad 62 and the gate electrode 61 can be electrically connected through the conductive metal in the connecting groove. By arranging the third opening and the first annular groove 512 on both sides of the first U-shaped groove 511, that is, the third opening and the first annular groove 512 are arranged in the front and rear directions of the first U-shaped groove 511, the third opening can be arranged behind the first U-shaped groove 511 and the first annular groove 512 is arranged in front of the first U-shaped groove 511, or the third opening can be arranged in front of the first U-shaped groove 511 and the first annular groove 512 is arranged behind the first U-shaped groove 511. In addition, the two first openings 31 are located below the left and right sides of the first U-shaped groove 511. By arranging the third opening and the first annular groove 512 relative to each other and respectively located on the front and rear sides of the first U-shaped groove 511, the size of the semiconductor device is further optimized, making the structure of the semiconductor device more compact.

[0066] In the embodiment of the present invention, a third dielectric layer 7 is further disposed on the second dielectric layer 5, and an opening is disposed on the third dielectric layer 7 corresponding to the gate pad 62 to expose the gate pad 62. Specifically, the third dielectric layer 7 may be made of silicon dioxide.

[0067] Furthermore, if Figures 11 to 14As shown, the third dielectric layer 7 is provided with a sixth opening 71 corresponding to the source electrode 41 and the third dielectric layer 7 is provided with a seventh opening 72 corresponding to the drain electrode 42, the sixth opening 71 is filled with a source pad 81, and the source pad 81 is electrically connected to the source electrode 41, the seventh opening 72 is filled with a first drain sub-pad 82, and the first drain sub-pad 82 is electrically connected to the drain electrode 42, a fourth dielectric layer 9 is further provided on the third dielectric layer 7, an eighth opening 91 is provided on the fourth dielectric layer 9 corresponding to the first drain sub-pad 82, and the eighth opening 91 is filled with a second drain sub-pad 101, the first drain sub-pad 82 and the second drain sub-pad 101 are stacked and form a drain pad 83, and the drain pad 83 is electrically connected to the drain electrode 42, the tops of the source pad 81 and the drain pad 83 are both higher than the top of the gate pad 62, and the top of the drain pad 83 is higher than the top of the source pad 81. Specifically, the fourth dielectric layer 9 is made of silicon dioxide, and the top of the source pad 81 is set higher than the top of the gate pad 62, and the top of the drain pad 83 is set higher than the top of the source pad 81, so as to stabilize the electric field of the semiconductor device. Of course, in some other specific implementations, the top of the source pad 81 can also be set higher than the top of the drain pad 83, as long as there is a height difference between the source pad 81 and the drain pad 83, the electric field of the semiconductor device can be more stable.

[0068] In some other specific embodiments of the present invention, a fourth opening is provided on the third dielectric layer 7 corresponding to the source electrode 41 and a fifth opening is provided on the third dielectric layer 7 corresponding to the drain electrode 42, the fourth opening is filled with a source pad 81, the source pad 81 is electrically connected to the source electrode 41, the fifth opening is filled with a drain pad 83, the drain pad 83 is electrically connected to the drain electrode 42, and the tops of the source pad 81 and the drain pad 83 are both higher than the top of the gate pad 62. At this time, the source pad 81 and the drain pad 83 have the same height, and the function of the semiconductor device can also be realized.

[0069] In the embodiment of the present invention, Figure 3 , Figure 7 and Fig.16 As shown, when the drain electrode 42 is filled in the second opening 32, the projection of the drain pad 83 in the vertical direction is located inside the first annular groove 512. In some other specific embodiments, when the source electrode 41 is filled in the second opening 32, the projection of the source pad 81 in the vertical direction is located inside the first annular groove 512, and the source pad 81 or the drain pad 83 is arranged just above the area surrounded by the first annular groove 512, which ensures the better performance of the semiconductor device while making the structure more compact.

[0070] In the embodiment of the present invention, when the source electrode 41 is filled in the first opening 31, the source pad 81 is arranged corresponding to the source electrode 41 and there are four source pads 81. Fig.16 As shown, when the source electrode 41 is filled in the first opening 31, a source pad 81 is respectively arranged at the front and rear ends of each source electrode 41; when the drain electrode 42 is filled in the first opening 31, a drain pad 83 is arranged corresponding to the drain electrode 42 and there are four drain pads 83, and a drain pad 83 is respectively arranged at the front and rear ends of each drain electrode 42. The arrangement of multiple drain pads 83 or multiple source pads 81 facilitates the stability and reliability of electrical connection.

[0071] In the embodiment of the present invention, Fig.15 As shown, a passivation layer 110 is further provided on the fourth dielectric layer 9, and openings are respectively provided on the passivation layer 110 corresponding to the source pad 81, the drain pad 83 and the gate pad 62 to expose the source pad 81, the drain pad 83 and the gate pad 62. Specifically, the passivation layer 110 is used to protect the semiconductor device and ensure the electrical performance of the semiconductor device.

[0072] The embodiment of the present invention further provides a method for manufacturing a semiconductor device, which is used to manufacture the above-mentioned semiconductor device, and comprises the following steps:

[0073] S1. Provide a substrate 1. Specifically, the substrate 1 may be a silicon-based substrate, a sapphire substrate, a gallium nitride single crystal substrate, or a gallium nitride composite substrate.

[0074] S2, growing a semiconductor channel layer 2 on the substrate 1; specifically, the semiconductor channel layer 2 includes a gallium nitride layer 21 and an aluminum gallium nitride layer 22, and the connection interface between the gallium nitride layer 21 and the aluminum gallium nitride layer 22 forms a two-dimensional electron gas layer, specifically, as Figure 1 to Figure 2 shown.

[0075] S3, forming a first dielectric layer 3 on the semiconductor channel layer 2, and patterning the first dielectric layer 3 to form a plurality of opening areas; specifically, Figure 3 to Figure 4 As shown, the material of the first dielectric layer 3 may be silicon nitride, and the first dielectric layer 3 is patterned in the area where the drain electrode 42 and the source electrode 41 are to be formed to obtain an opening area.

[0076] S4, forming a first metal layer 4 in the first dielectric layer 3 and a plurality of opening regions, the first metal layer 4 being used to form a source electrode 41 and a drain electrode 42 which are spaced apart and in contact with the semiconductor channel layer 2; specifically, Figures 5 and 6 As shown, the first metal layer 4 is a stacked composite structure of four metal layers of titanium / aluminum / nickel / gold. The first metal layer 4 is etched to form a spaced source electrode 41 and a drain electrode 42. The lower portions of the source electrode 41 and the drain electrode 42 are fully contacted and connected to the semiconductor channel layer 2, which can improve carrier diffusion, form a good ohmic contact, and effectively reduce contact resistance.

[0077] S5, forming a second dielectric layer 5 on the first dielectric layer 3, the source electrode 41 and the drain electrode 42, and patterning the second dielectric layer 5 to form a groove; specifically, as Figures 7 to 9 As shown, the second dielectric layer 5 can be silicon dioxide. The second dielectric layer 5 first covers the first dielectric layer 3, the source electrode 41 and the drain electrode 42, and then the second dielectric layer 5 is patterned to form a groove of the required structure, and the second dielectric layer 5 is used to protect the drain electrode 42 and the source electrode 41.

[0078] S6, forming a second metal layer 6 in the second dielectric layer 5 and the trench, the second metal layer 6 is used to form a gate electrode 61, the gate electrode 61 is a closed ring, and the projection of the gate electrode 61 in the vertical direction surrounds the projection of the source electrode 41 or the drain electrode 42 in the vertical direction. Specifically, as Fig.10 As shown, the second metal layer 6 may be a stacked composite structure of three metal layers of titanium / aluminum / titanium, and the gate electrode 61 of a desired structure is formed by etching the second metal layer 6 .

[0079] The embodiment of the present invention does not need to use an ion implantation process to manufacture semiconductor devices, which has lower costs. In addition, by designing the gate electrode 61 to be a closed ring, and the projection of the gate electrode 61 in the vertical direction surrounds the projection of the source electrode 41 or the drain electrode 42 in the vertical direction, the source electrode 41 or the drain electrode 42 located in the gate electrode 61 is prevented from leaking current, and the performance of the semiconductor device is better.

[0080] In an embodiment of the present invention, a plurality of opening regions include a first opening 31 and a second opening 32 that are spaced apart from each other. The first opening 31 and the second opening 32 extend downward to the upper surface of the semiconductor channel layer 2. The first metal layer 4 at the first opening 31 forms one of the source electrode 41 and the drain electrode 42. The first metal layer 4 at the second opening 32 forms the other of the source electrode 41 and the drain electrode 42.

[0081] In the embodiment of the present invention, the first opening 31 is in a T-shaped structure, the second opening 32 is in a strip-shaped structure, the first opening 31 is provided on at least one side of the second opening 32, and the first opening 31 includes a first opening portion 311 extending toward the second opening 32 and a second opening portion 312 connected to the first opening portion 311, and the second opening portion 312 is connected to a side of the first opening portion 311 away from the second opening 32. Specifically, there are two first openings 31, the two first openings 31 are respectively provided on both sides of the second opening 32, and the two first opening portions 311 are arranged opposite to each other, so that the structure of the semiconductor device is very compact and the performance is better.

[0082] In the embodiment of the present invention, step S4, forming a first metal layer 4 in the first dielectric layer 3 and the plurality of opening regions, wherein the first metal layer 4 is used to form a source electrode 41 and a drain electrode 42 which are spaced apart and in contact with the semiconductor channel layer 2, comprises:

[0083] S41 , sputtering a first metal in the first dielectric layer 3 , the first opening 31 , and the second opening 32 to form a first metal layer 4 .

[0084] S42. The first metal layer 4 is etched by photolithography and etching process to form a source electrode 41 and a drain electrode 42 which are spaced apart and in contact with the semiconductor channel layer 2, one of the source electrode 41 and the drain electrode 42 extends to the upper surface of the first dielectric layer 3, and the other of the source electrode 41 and the drain electrode 42 extends to the upper surface of the first dielectric layer 3.

[0085] In some other specific embodiments, step S4, forming a first metal layer 4 in the first dielectric layer 3 and the plurality of opening regions, and forming a source electrode 41 and a drain electrode 42 spaced apart and in contact with the semiconductor channel layer 2 on the first metal layer 4, comprises:

[0086] S401, using a first shielding layer to shield the areas on the first dielectric layer 3 where no source electrode 41 and drain electrode 42 are required. The first shielding layer shields the areas on the first dielectric layer 3 where no source electrode 41 and drain electrode 42 are required, thereby preventing these areas from being sputtered with the first metal.

[0087] S402, sputtering the first metal in the first dielectric layer 3, the first opening 31 and the second opening 32 without the first shielding layer to form a source electrode 41 and a drain electrode 42 that are spaced apart and in contact with the semiconductor channel layer 2, one of the source electrode 41 and the drain electrode 42 extending to the upper surface of the first dielectric layer 3, and the other of the source electrode 41 and the drain electrode 42 extending to the upper surface of the first dielectric layer 3. This method does not require etching of the first metal layer 4.

[0088] S403, removing the first shielding layer. After the source electrode 41 and the drain electrode 42 are manufactured, the first shielding layer can be removed to facilitate subsequent processes.

[0089] In the embodiment of the present invention, the groove includes a first groove 51, the first groove 51 extends downward to the upper surface of the first dielectric layer 3, and a second groove 33 is further provided on the first dielectric layer 3 corresponding to the first groove 51, the second groove 33 extends to the inside of the first dielectric layer 3 and does not penetrate the first dielectric layer 3, the second groove 33 is spaced from the first opening 31 and the second opening 32, the horizontal dimension of the second groove 33 is smaller than the horizontal dimension of the first groove 51 so that the first groove 51 and the second groove 33 form a step groove, the step groove is filled with a gate electrode 61, and the gate electrode 61 extends to the upper surface of the second dielectric layer 5. Specifically, as Figures 7 to 9 As shown, the first groove 51 is in a closed ring shape, and the projection of the first groove 51 in the vertical direction surrounds the projection of the second opening 32 in the vertical direction and the projection of the first groove 51 in the vertical direction is located between the projections of the two first openings 311 in the vertical direction; the second groove 33 is in a closed ring shape, and the projection of the second groove 33 in the vertical direction is located in the projection of the first groove 51 in the vertical direction. The step groove is more conducive to the attachment of the gate electrode 61, and the connection is more reliable. The material of the second dielectric layer 5 can be silicon dioxide. By setting the gate electrode 61 as a closed ring-shaped closed electrode, the closed ring-shaped electrode will not form an electric field when it is not powered. The semiconductor channel layer 2 forms a current-conducting channel due to the structure of the two-dimensional electron gas. At this time, the source and the drain are connected. When the gate electrode 61 is powered, the electric field of the gate electrode 61 destroys the conductive channel formed by the two-dimensional electron gas on the semiconductor channel layer 2, so that the source and the drain are cut off. Of course, in some other embodiments, the second groove 33 may not be provided, that is, only the first groove 51 is provided, and the function of the semiconductor device of the present invention can also be achieved.

[0090] In the embodiment of the present invention, the first groove 51 includes a first U-shaped groove 511 and a first annular groove 512. The first annular groove 512 is disconnected from the first U-shaped groove 511 on one side to connect with the two ends of the first U-shaped groove 511. The projection of the first U-shaped groove 511 in the vertical direction surrounds the projection of the second opening 32 in the vertical direction, and the projection of the first U-shaped groove 511 in the vertical direction is located between the projections of the two first openings 311 in the vertical direction. The second groove 33 includes a second U-shaped groove and a second annular groove. The second annular groove is disconnected from the second U-shaped groove on one side to connect with the two ends of the second U-shaped groove. Specifically, as Figures 7 and 8 As shown, by designing the first trench 51 to include a first U-shaped trench 511 and a first annular trench 512 , and designing the second trench 33 to include a second U-shaped trench and a second annular trench, the structure of the semiconductor device is made more compact.

[0091] In the embodiment of the present invention, in step S5, the step of patterning the second dielectric layer 5 to form a groove includes:

[0092] S51, patterning the second dielectric layer 5 to form a groove and a third opening, the third opening is connected to the first U-shaped groove 511, and the third opening is arranged opposite to the first annular groove 512 and is respectively located on both sides of the first U-shaped groove 511. Figures 7 to 10 As shown, a groove for forming a gate electrode 61 and a third opening of a gate pad 62 are simultaneously formed on the second dielectric layer 5, the process is simpler, the third opening can be connected to the first U-shaped groove 511 through a connecting groove, and the gate pad 62 and the gate electrode 61 can be electrically connected through the conductive metal in the connecting groove. By arranging the third opening and the first annular groove 512 on both sides of the first U-shaped groove 511, that is, the third opening and the first annular groove 512 are arranged in the front and rear directions of the first U-shaped groove 511, the third opening can be arranged in the first A U-shaped groove 511 is arranged behind the first annular groove 512 and in front of the first U-shaped groove 511, or the third opening can be arranged in front of the first U-shaped groove 511 and the first annular groove 512 is arranged behind the first U-shaped groove 511. In addition, the two first openings 31 are located below the left and right sides of the first U-shaped groove 511. By arranging the third opening and the first annular groove 512 opposite to each other and respectively located on the front and back sides of the first U-shaped groove 511, the size of the semiconductor device is further optimized, making the structure of the semiconductor device more compact.

[0093] In the embodiment of the present invention, in step S6, a second metal layer 6 is formed in the second dielectric layer 5 and the trench, and the second metal layer 6 is used to form a gate electrode 61, including:

[0094] S61 , forming a second metal layer 6 in the second dielectric layer 5 , the trench and the third opening, wherein the second metal layer 6 is used to form a gate electrode 61 and a gate pad 62 .

[0095] Step S61, forming a second metal layer 6 in the second dielectric layer 5, the trench and the third opening, wherein the second metal layer 6 is used to form a gate electrode 61 and a gate pad 62, including:

[0096] S611 , sputtering a second metal in the second dielectric layer 5 , the trench and the third opening to form a second metal layer 6 , and etching the second metal layer 6 by photolithography or etching process to form an electrically connected gate electrode 61 and a gate pad 62 .

[0097] In some other specific embodiments, step S61, forming a second metal layer 6 in the second dielectric layer 5, the trench and the third opening, wherein the second metal layer 6 is used to form the gate electrode 61 and the gate pad 62, comprises:

[0098] S6101, using a second shielding layer to shield areas on the second dielectric layer 5 where no gate electrode 61 and gate pad 62 are required. The second shielding layer shields areas on the second dielectric layer 5 where no gate electrode 61 and gate pad 62 are required, thereby preventing these areas from being sputtered with the second metal.

[0099] S6102 , sputtering a second metal in the second dielectric layer 5 , the trench and the third opening where the second shielding layer is not provided, to form an electrically connected gate electrode 61 and a gate pad 62 , thereby eliminating the need to etch the second metal layer 6 .

[0100] S6103, removing the second shielding layer. After the gate electrode 61 and the gate pad 62 are manufactured, the second shielding layer can be removed to facilitate subsequent processes.

[0101] In the embodiment of the present invention, step S61, after forming a second metal layer 6 in the second dielectric layer 5, the trench and the third opening, and the second metal layer 6 is used to form a gate electrode 61 and a gate pad 62, further includes:

[0102] S7, forming a third dielectric layer 7 on the second dielectric layer 5, wherein the third dielectric layer 7 covers the second dielectric layer 5 and the gate electrode 61 and does not cover the gate pad 62. Specifically, the third dielectric layer 7 may be made of silicon dioxide.

[0103] After step S7, after the step of forming the third dielectric layer 7 on the second dielectric layer 5, the method further includes:

[0104] S81, etching the third dielectric layer 7 corresponding to the source electrode 41 and the drain electrode 42 to form a sixth opening 71 and a seventh opening 72 respectively. Fig.11 shown.

[0105] S82 , forming a third metal layer 8 on the sixth opening 71 , the seventh opening 72 and the third dielectric layer 7 .

[0106] S83, etching the third metal layer 8 to form a source pad 81 in the sixth opening 71 and a first drain sub-pad 82 in the seventh opening 72, the source pad 81 is electrically connected to the source electrode 41, and the first drain sub-pad 82 is electrically connected to the drain electrode 42, as shown in detail. Fig.12 As shown, the third metal layer 8 may be a laminated composite structure of three metal layers of titanium / aluminum / titanium.

[0107] S84, such as Fig.13 As shown, a fourth dielectric layer 9 is formed on the third dielectric layer 7, and an eighth opening 91 is provided on the fourth dielectric layer 9 corresponding to the first drain sub-pad 82. Specifically, the fourth dielectric layer 9 is made of silicon dioxide.

[0108] S85, forming a fourth metal layer 10 in the fourth dielectric layer 9 and the eighth opening 91. Specifically, the fourth metal layer 9 may be a stacked composite structure of three metal layers of titanium / aluminum / titanium.

[0109] S86, etching the fourth metal layer 10 to form a second drain sub-pad 101 in the eighth opening 91, the first drain sub-pad 82 and the second drain sub-pad 101 are stacked and form a drain pad 83, the drain pad 83 is electrically connected to the drain electrode 42, the tops of the source pad 81 and the drain pad 83 are higher than the top of the gate pad 62, and the top of the drain pad 83 is higher than the top of the source pad 81. Specifically, as Fig.14 As shown, by setting the first drain sub-pad 82 and the second drain sub-pad 101, the top of the drain pad 83 is higher than the top of the source pad 81, which is convenient for stabilizing the electric field of the semiconductor device. Of course, in some other specific embodiments, the top of the source pad 81 can also be set higher than the top of the drain pad 83, as long as there is a height difference between the source pad 81 and the drain pad 83, the electric field of the semiconductor device can be more stable.

[0110] In some other specific implementations of the embodiments of the present invention, after step S7, after the step of forming the third dielectric layer 7 on the second dielectric layer 5, the following steps are further included:

[0111] S801 , etching the third dielectric layer 7 corresponding to the source electrode 41 and the drain electrode 42 to form a fourth opening and a fifth opening respectively.

[0112] S802 , forming a third metal layer 8 on the fourth opening, the fifth opening and the third dielectric layer 7 .

[0113] S803, etching the third metal layer 8 to form a source pad 81 in the fourth opening and a drain pad 83 in the fifth opening, the source pad 81 is electrically connected to the source electrode 41, the drain pad 83 is electrically connected to the drain electrode 42, and the tops of the source pad 81 and the drain pad 83 are both higher than the top of the gate pad 62. At this time, the source pad 81 and the drain pad 83 have the same height, and the function of the semiconductor device can also be realized.

[0114] In the embodiment of the present invention, Figure 3 , Figure 7 as well as Fig.16As shown, when the drain electrode 42 is filled in the second opening 32, the projection of the drain pad 83 in the up-down direction is located inside the first annular groove 512. In some other embodiments of the present invention. When the source electrode 41 is filled in the second opening 32, the projection of the source pad 81 in the up-down direction is located inside the first annular groove 512. Specifically, the source pad 81 or the drain pad 83 is arranged directly above the area surrounded by the first annular groove 512, so that the source pad 81 or the drain pad 83 can be prevented from leaking electricity, ensuring the better performance of the semiconductor device while making the structure more compact.

[0115] In the embodiment of the present invention, when the source electrode 41 is filled in the first opening 31, the source pad 81 is set corresponding to the source electrode 41 and there are four source pads 81. Specifically, when the drain electrode 42 is filled in the first opening 31, a drain pad 83 is set at the front and rear ends of each drain electrode 42. In other embodiments of the present invention, when the drain electrode 42 is filled in the first opening 31, the drain pad 83 is set corresponding to the drain electrode 42 and there are four drain pads 83; a source pad 81 is set at the front and rear ends of each source electrode 41. The setting of multiple drain pads 83 or multiple source pads 81 facilitates stable and reliable electrical connection.

[0116] In the embodiment of the present invention, in step S86, the fourth metal layer 10 is etched to form a second drain sub-pad 101 in the eighth opening 91, and after the first drain sub-pad 82 and the second drain sub-pad 101 are stacked and arranged to form a drain pad 83, the following steps are also included:

[0117] S9, forming a passivation layer 110 on the fourth dielectric layer 9, and the passivation layer 110 is provided with openings corresponding to the source pad 81, the drain pad 83 and the gate pad 62 to expose the source pad 81, the drain pad 83 and the gate pad 62. The passivation layer 110 is used to protect the semiconductor device and ensure the electrical performance of the semiconductor device.

[0118] The embodiment of the present invention can manufacture semiconductor devices only through sputtering, photolithography, etching and other processes, without the need to use expensive equipment such as ion implantation equipment, which can greatly reduce costs and has a clever design.

[0119] The above disclosure is only a preferred embodiment of the present invention, and certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention still fall within the scope covered by the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises a substrate, a semiconductor channel layer and a first dielectric layer arranged in sequence from bottom to top, and the semiconductor device further comprises a source electrode, a drain electrode and a gate electrode, the source electrode and the drain electrode are arranged at intervals and both pass through the first dielectric layer and are in contact with and connected to the semiconductor channel layer; A second dielectric layer is also provided on the first dielectric layer, the gate electrode passes through the second dielectric layer and is in contact with the first dielectric layer, the gate electrode is in a closed ring shape, and the projection of the gate electrode in the vertical direction surrounds the projection of the source electrode or the drain electrode in the vertical direction.

2. The semiconductor device according to claim 1, wherein The first dielectric layer is provided with a first opening and a second opening which are spaced apart from each other. The first opening and the second opening extend downward to the upper surface of the semiconductor channel layer. The first opening is filled with one of the source electrode and the drain electrode, and one of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer. The second opening is filled with the other of the source electrode and the drain electrode, and the other of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer.

3. The semiconductor device according to claim 2, wherein: The first opening is a T-shaped structure, the second opening is a long strip structure, the first opening is arranged on at least one side of the second opening and the first opening includes a first opening extending toward the second opening and a second opening connected to the first opening, and the second opening is connected to a side of the first opening away from the second opening.

4. The semiconductor device according to claim 3, characterized in that There are two first openings, and the two first openings are respectively arranged on both sides of the second opening and the two first openings are arranged opposite to each other.

5. The semiconductor device according to claim 4, wherein: A first groove is provided on the second dielectric layer, and the first groove extends downward to the upper surface of the first dielectric layer. A second groove is provided on the first dielectric layer corresponding to the first groove, and the second groove extends to the interior of the first dielectric layer and does not penetrate the first dielectric layer. The second groove is spaced apart from the first opening and the second opening. The horizontal dimension of the second groove is smaller than the horizontal dimension of the first groove so that the first groove and the second groove form a step groove. The gate electrode is filled in the step groove, and the gate electrode extends to the upper surface of the second dielectric layer.

6. The semiconductor device according to claim 5, characterized in that The first groove is in the shape of a closed ring, the projection of the first groove in the vertical direction surrounds the projection of the second opening in the vertical direction and the projection of the first groove in the vertical direction is located between the projections of the two first openings in the vertical direction; the second groove is in the shape of a closed ring, the projection of the second groove in the vertical direction is located in the projection of the first groove in the vertical direction.

7. The semiconductor device according to claim 6, wherein: The first groove includes a first U-shaped groove and a first annular groove, the first annular groove is disconnected from the first U-shaped groove on one side so as to be connected to the two ends of the first U-shaped groove, the projection of the first U-shaped groove in the up-down direction surrounds the projection of the second opening in the up-down direction and the projection of the first U-shaped groove in the up-down direction is located between the projections of the two first openings in the up-down direction; the second groove includes a second U-shaped groove and a second annular groove, the second annular groove is disconnected from the second U-shaped groove on one side so as to be connected to the two ends of the second U-shaped groove.

8. The semiconductor device according to claim 7, wherein: A third opening is also provided on the second dielectric layer, the third opening is connected to the first U-shaped groove, the third opening is arranged opposite to the first annular groove and is respectively located on both sides of the first U-shaped groove, the third opening is filled with a gate pad, and the gate pad is electrically connected to the gate electrode.

9. The semiconductor device according to claim 8, characterized in that A third dielectric layer is further disposed on the second dielectric layer, and an opening is disposed on the third dielectric layer corresponding to the gate pad to expose the gate pad.

10. The semiconductor device according to claim 9, wherein: A fourth opening is provided on the third dielectric layer corresponding to the source electrode, and a fifth opening is provided on the third dielectric layer corresponding to the drain electrode, the fourth opening is filled with a source pad, the source pad is electrically connected to the source electrode, the fifth opening is filled with a drain pad, the drain pad is electrically connected to the drain electrode, and the tops of the source pad and the drain pad are both higher than the top of the gate pad.

11. The semiconductor device according to claim 9, wherein The third dielectric layer is provided with a sixth opening corresponding to the source electrode and the third dielectric layer is provided with a seventh opening corresponding to the drain electrode, the sixth opening is filled with a source pad, the source pad is electrically connected to the source electrode, the seventh opening is filled with a first drain sub-pad, the first drain sub-pad is electrically connected to the drain electrode, a fourth dielectric layer is further provided on the third dielectric layer, an eighth opening is provided on the fourth dielectric layer corresponding to the first drain sub-pad, the eighth opening is filled with a second drain sub-pad, the first drain sub-pad and the second drain sub-pad are stacked and form the drain pad, the drain pad is electrically connected to the drain electrode, the tops of the source pad and the drain pad are both higher than the top of the gate pad, and the top of the drain pad is higher than the top of the source pad.

12. The semiconductor device according to claim 10 or 11, characterized in that When the source electrode is filled in the second opening, the projection of the source pad in the vertical direction is located inside the first annular groove; when the drain electrode is filled in the second opening, the projection of the drain pad in the vertical direction is located inside the first annular groove.

13. The semiconductor device according to claim 12, wherein: When the drain electrode is filled in the first opening, the drain pad is arranged corresponding to the drain electrode and there are four drain pads; when the source electrode is filled in the first opening, the source pad is arranged corresponding to the source electrode and there are four source pads.

14. The semiconductor device according to claim 1, wherein: The substrate is a silicon-based substrate, a sapphire substrate, a gallium nitride single crystal substrate or a gallium nitride composite substrate, the semiconductor channel layer includes a gallium nitride layer and an aluminum gallium nitride layer, and the connection interface between the gallium nitride layer and the aluminum gallium nitride layer forms a two-dimensional electron gas layer.

15. The semiconductor device according to claim 11, wherein The first dielectric layer is made of silicon nitride, the source electrode and the drain electrode are both a laminated composite structure of four metal layers of titanium / aluminum / nickel / gold, and the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all made of silicon dioxide.

16. The semiconductor device according to claim 11, wherein A passivation layer is further disposed on the fourth dielectric layer, and openings are respectively disposed on the passivation layer corresponding to the source pad, the drain pad and the gate pad to expose the source pad, the drain pad and the gate pad.

17. A method for manufacturing a semiconductor device, characterized in that: The steps include: providing a substrate; growing a semiconductor channel layer on the substrate; forming a first dielectric layer on the semiconductor channel layer, and patterning the first dielectric layer to form a plurality of opening areas; Forming a first metal layer in the first dielectric layer and the plurality of opening areas, the first metal layer being used to form a source electrode and a drain electrode which are spaced apart and in contact with the semiconductor channel layer; forming a second dielectric layer on the first dielectric layer, the source electrode and the drain electrode, and patterning the second dielectric layer to form a groove; A second metal layer is formed in the second dielectric layer and the groove, and the second metal layer is used to form a gate electrode. The gate electrode is in a closed ring shape, and the projection of the gate electrode in the vertical direction surrounds the projection of the source electrode or the drain electrode in the vertical direction.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The plurality of opening areas include a first opening and a second opening that are spaced apart from each other, the first opening and the second opening extending downward to the upper surface of the semiconductor channel layer, the first metal layer at the first opening forming one of the source electrode and the drain electrode, and the first metal layer at the second opening forming the other of the source electrode and the drain electrode.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The first opening is a T-shaped structure, the second opening is a long strip structure, the first opening is arranged on at least one side of the second opening and the first opening includes a first opening extending toward the second opening and a second opening connected to the first opening, and the second opening is connected to a side of the first opening away from the second opening.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: There are two first openings, and the two first openings are respectively arranged on both sides of the second opening and the two first openings are arranged opposite to each other.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: The steps of forming a first metal layer in the first dielectric layer and the plurality of opening areas, wherein the first metal layer is used to form a source electrode and a drain electrode which are spaced apart and in contact with the semiconductor channel layer include: sputtering a first metal in the first dielectric layer, the first opening, and the second opening to form a first metal layer; The first metal layer is etched by photolithography and etching process to form a source electrode and a drain electrode which are spaced apart and in contact with the semiconductor channel layer, one of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer, and the other of the source electrode and the drain electrode extends to the upper surface of the first dielectric layer; or, The steps of forming a first metal layer in the first dielectric layer and the plurality of opening areas, wherein the first metal layer forms a source electrode and a drain electrode which are spaced apart and in contact with the semiconductor channel layer include: Using a first shielding layer to cover the area on the first dielectric layer where the source electrode and the drain electrode are not required; Sputtering a first metal in a first dielectric layer without a first shielding layer, the first opening, and the second opening to form a source electrode and a drain electrode that are spaced apart and in contact with the semiconductor channel layer, one of the source electrode and the drain electrode extending to the upper surface of the first dielectric layer, and the other of the source electrode and the drain electrode extending to the upper surface of the first dielectric layer; The first shielding layer is removed.

22. The method for manufacturing a semiconductor device according to claim 21, wherein: The groove includes a first groove, the first groove extends downward to the upper surface of the first dielectric layer, a second groove is provided on the first dielectric layer corresponding to the first groove, the second groove extends to the interior of the first dielectric layer and does not penetrate the first dielectric layer, the second groove is spaced from the first opening and the second opening, the horizontal dimension of the second groove is smaller than the horizontal dimension of the first groove so that the first groove and the second groove form a step groove, the gate electrode is filled in the step groove, and the gate electrode extends to the upper surface of the second dielectric layer.

23. The method for manufacturing a semiconductor device according to claim 22, wherein: The first groove is in the shape of a closed ring, the projection of the first groove in the vertical direction surrounds the projection of the second opening in the vertical direction and the projection of the first groove in the vertical direction is located between the projections of the two first openings in the vertical direction; the second groove is in the shape of a closed ring, the projection of the second groove in the vertical direction is located in the projection of the first groove in the vertical direction.

24. The method for manufacturing a semiconductor device according to claim 22, wherein: The first groove includes a first U-shaped groove and a first annular groove, the first annular groove is disconnected from the first U-shaped groove on one side so as to be connected to the two ends of the first U-shaped groove, the projection of the first U-shaped groove in the up-down direction surrounds the projection of the second opening in the up-down direction and the projection of the first U-shaped groove in the up-down direction is located between the projections of the two first openings in the up-down direction; the second groove includes a second U-shaped groove and a second annular groove, the second annular groove is disconnected from the second U-shaped groove on one side so as to be connected to the two ends of the second U-shaped groove.

25. The method for manufacturing a semiconductor device according to claim 24, wherein: The step of patterning the second dielectric layer to form a groove comprises: The second dielectric layer is patterned to form a groove and a third opening, wherein the third opening is connected to the first U-shaped groove, and the third opening is arranged opposite to the first annular groove and is respectively located on both sides of the first U-shaped groove.

26. The method for manufacturing a semiconductor device according to claim 25, wherein: The second metal layer is formed in the second dielectric layer and the trench, and the second metal layer is used to form a gate electrode, comprising: A second metal layer is formed in the second dielectric layer, the trench and the third opening, and the second metal layer is used to form the gate electrode and the gate pad.

27. The method for manufacturing a semiconductor device according to claim 26, wherein: A second metal layer is formed in the second dielectric layer, the trench and the third opening, wherein the second metal layer is used to form the gate electrode and the gate pad, and includes: Sputtering a second metal in the second dielectric layer, the trench and the third opening to form a second metal layer, and etching the second metal layer by photolithography or etching to form the electrically connected gate electrode and the gate pad; or, A second metal layer is formed in the second dielectric layer, the trench and the third opening, wherein the second metal layer is used to form the gate electrode and the gate pad, and includes: Using a second shielding layer to shield an area on the second dielectric layer where a gate electrode and a gate pad are not required; Sputtering a second metal in the second dielectric layer, the trench, and the third opening where the second shielding layer is not provided to form the gate electrode and the gate pad that are electrically connected; The second shielding layer is removed.

28. The method for manufacturing a semiconductor device according to claim 27, wherein: After forming a second metal layer in the second dielectric layer, the trench and the third opening, wherein the second metal layer is used to form the gate electrode and the gate pad, the method further includes: A third dielectric layer is formed on the second dielectric layer, wherein the third dielectric layer covers the second dielectric layer and the gate electrode and does not cover the gate pad.

29. The method for manufacturing a semiconductor device according to claim 28, wherein: After the step of forming a third dielectric layer on the second dielectric layer, the method further comprises: Etching the third dielectric layer corresponding to the source electrode and the drain electrode to form a fourth opening and a fifth opening respectively; forming a third metal layer on the fourth opening, the fifth opening and the third dielectric layer; The third metal layer is etched to form a source pad in the fourth opening and a drain pad in the fifth opening, wherein the source pad is electrically connected to the source electrode, and the drain pad is electrically connected to the drain electrode, and the tops of the source pad and the drain pad are both higher than the top of the gate pad.

30. The method for manufacturing a semiconductor device according to claim 28, wherein: After the step of forming a third dielectric layer on the second dielectric layer, the method further comprises: Etching the third dielectric layer corresponding to the source electrode and the drain electrode to form a sixth opening and a seventh opening respectively; forming a third metal layer on the sixth opening, the seventh opening and the third dielectric layer; Etching the third metal layer to form a source pad in the sixth opening and a first drain sub-pad in the seventh opening, wherein the source pad is electrically connected to the source electrode, and the first drain sub-pad is electrically connected to the drain electrode; forming a fourth dielectric layer on the third dielectric layer, wherein an eighth opening is provided on the fourth dielectric layer corresponding to the first drain sub-pad; forming a fourth metal layer in the fourth dielectric layer and the eighth opening; The fourth metal layer is etched to form a second drain sub-pad in the eighth opening, the first drain sub-pad and the second drain sub-pad are stacked and form the drain pad, the drain pad is electrically connected to the drain electrode, the source pad and the top of the drain pad are both higher than the top of the gate pad, and the top of the drain pad is higher than the top of the source pad.

31. The method for manufacturing a semiconductor device according to claim 29 or 30, characterized in that: When the source electrode is filled in the second opening, the projection of the source pad in the vertical direction is located inside the first annular groove; when the drain electrode is filled in the second opening, the projection of the drain pad in the vertical direction is located inside the first annular groove.

32. The method for manufacturing a semiconductor device according to claim 31, wherein: When the drain electrode is filled in the first opening, the drain pad is arranged corresponding to the drain electrode and there are four drain pads; when the source electrode is filled in the first opening, the source pad is arranged corresponding to the source electrode and there are four source pads.

33. The method for manufacturing a semiconductor device according to claim 30, wherein: The fourth metal layer is etched to form a second drain sub-pad in the eighth opening, and after the first drain sub-pad and the second drain sub-pad are stacked and formed into the drain pad, the method further includes: A passivation layer is formed on the fourth dielectric layer, and openings are respectively provided on the passivation layer corresponding to the source pad, the drain pad and the gate pad to expose the source pad, the drain pad and the gate pad.

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