A low power consumption control method and system for power chip

Abstract

The present invention provides a low-power consumption control method and system for a power chip, and relates to the technical field of power device control. The method comprises: collecting load power, power device temperature and power chip response time through a multi-modal detection module; inputting them into a control module; estimating a real-time parasitic parameter disturbance term through an adaptive disturbance observer according to the response time of the power device; determining a first constraint on a PWM signal duty cycle of an internal voltage source with the goal of reducing heat loss of the power device; determining a second constraint on an output voltage of a driving voltage source with the goal of reducing the response time of the power device; determining a target PWM signal duty cycle of an output voltage source and a target output voltage of a driving voltage source under the first constraint and the second constraint respectively in combination with the real-time parasitic parameter disturbance term; and controlling the power chip according to the target PWM signal duty cycle and the target output voltage. The control power consumption is reduced and the control efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power device control, and in particular to a low-power consumption control method and system for a power chip. Background Art

[0002] A power chip is an integrated circuit chip used for the conversion, distribution and management of electrical energy. It usually contains various power devices (such as MOSFET, IGBT, etc.) to achieve the control of current and voltage. The power devices in the power chip undertake the switching and transmission tasks of large currents, which directly determines the energy loss and heat generation of the chip. Power chips (PowerICs) are mainly responsible for providing power management and power control. They are used to control the conversion, regulation and distribution of current and voltage, such as power management integrated circuits (PMIC), voltage regulators, charging management chips, etc. The design focus of the power chip is to ensure stable and efficient power supply and provide the necessary power support for the system.

[0003] As the integration and power density of devices increase, power consumption and heat dissipation management of power chips become key issues. Low power consumption control can reduce the heat loss of power devices, extend chip life, improve efficiency, and meet the needs of portable devices and high-density power systems for low energy consumption and high reliability.

[0004] However, the existing power chip control method often uses a fixed on-time during the control process, and a long on-state will cause heat accumulation, resulting in device overheating, increased on-resistance, and thus increased power consumption of the power chip. In addition, the existing power chip does not consider the parasitic disturbance terms in the circuit, further increasing the uncertainty and instability of the control. The constant drive voltage used as the gate voltage of the power device is prone to on-off delays, reducing the sensitivity of the power chip, and the constant drive voltage will also waste unnecessary power consumption under low load conditions. Summary of the invention

[0005] In order to solve the problem that the power chip control method often uses a fixed on-time in the control process, and the long-term on-state will cause heat accumulation, resulting in device overheating, increased on-resistance, and thus increased power consumption of the power chip. In addition, the existing power chip does not consider the parasitic disturbance term in the circuit, which further increases the uncertainty and instability of the control. The constant driving voltage used as the gate voltage of the power device is prone to on-off delay, which reduces the sensitivity of the power chip, and the constant driving voltage will also waste unnecessary power consumption under low load conditions. The present invention provides a low-power control method and system for a power chip.

[0006] The technical solution provided by the embodiment of the present invention is as follows:

[0007] First aspect:

[0008] A low-power consumption control method for a power chip provided by an embodiment of the present invention is applied to a low-power consumption control circuit of a power chip, wherein the low-power consumption control circuit of the power chip comprises an output driver, a driving voltage source, a decoupling capacitor, a gate resistor, an N-groove discharge transistor, a power device, a multi-modal detection module and a control module; the output driver comprises an internal voltage source, a first output, a second output and a ground node; the output driver is used to control the level signals of the first output and the second output, and the internal voltage source, the driving voltage source, the decoupling capacitor and the ground node are sequentially connected in series to form a closed loop connected in parallel to the output driver; the first output is sequentially connected to the ground through the gate resistor, the drain of the N-groove discharge transistor, the gate of the power device and the source of the power device; the drain of the power device is connected in series to the load circuit; the second output is grounded through the gate of the N-groove discharge crystal and the source of the N-groove discharge transistor; the multi-modal detection module is connected to the load circuit, and the control module is respectively connected to the internal voltage source, the driving voltage source and the multi-modal detection module; wherein the first output and the second output are mutually inverted outputs; the method comprises:

[0009] S1: Collect load power, power device temperature and power chip response time through the multi-modal detection module;

[0010] S2: inputting load power, power device temperature and power device response time into the control module;

[0011] S3: Estimate the real-time parasitic parameter disturbance term through an adaptive disturbance observer according to the response time of the power device;

[0012] S4: with the goal of reducing heat loss of the power device, determining a first constraint on a duty cycle of a PWM signal of an internal voltage source;

[0013] S5: determining a second constraint on the output voltage of the driving voltage source with the goal of reducing the response time of the power device;

[0014] S6: Determine the target PWM signal duty cycle of the output voltage source and the target output voltage of the driving voltage source under the first constraint and the second constraint respectively in combination with the real-time parasitic parameter disturbance term;

[0015] S7: Control the power chip according to the target PWM signal duty cycle and the target output voltage.

[0016] Second aspect:

[0017] An embodiment of the present invention provides a low power consumption control system for a power chip, comprising:

[0018] processor;

[0019] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the low power consumption control method for the power chip as described in the first aspect is implemented.

[0020] The third aspect:

[0021] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the low power consumption control method of the power chip as described in the first aspect is implemented.

[0022] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0023] In the present invention, by setting a power chip low-power control circuit with two output terminals with mutually inverted outputs, one of which is connected to an N-groove discharge transistor, the gate charge can be quickly charged and discharged to complete the rapid on-off of the power device, reducing the on-time, thereby avoiding the problem of increased on-resistance caused by heat accumulation, maintaining the on-resistance in a low on-resistance state, and saving the power chip on-power consumption. In addition, the setting of the gate resistance can suppress the transient current generated during the switching process, reduce the generation of peak current, reduce the electromagnetic interference of the power device switching process, and further reduce the loss caused by the instantaneous current mutation of the switch. In addition, in the control circuit, through the multi-modal detection module and the control module, according to the detected power device data, an adaptive disturbance observer is introduced to estimate the real-time disturbance, and then the on-voltage and PWM signal duty cycle applied to the gate are adaptively compensated, so that the power device can enable the power device to quickly enter the saturated on-state, further improve the switching speed, reduce heat accumulation, and reduce control power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic flow chart of a low power consumption control method for a power chip provided by an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the structure of a power chip low power consumption control circuit provided by an embodiment of the present invention;

[0027] Figure 3 A schematic structural diagram of a low power consumption control system of a power chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0029] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0030] In the embodiments of the present invention, "image" and "picture" can sometimes be used interchangeably. It should be noted that when the difference between them is not emphasized, the meanings they intend to express are the same. "of", "corresponding, relevant" and "corresponding" can sometimes be used interchangeably. It should be noted that when the difference between them is not emphasized, the meanings they intend to express are the same.

[0031] In the embodiments of the present invention, sometimes the subscripts such as W 1 It may be written in non-subscript form such as W1. When the difference is not emphasized, the meaning is the same.

[0032] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0033] Reference Manual Attached Figure 1 , shows a flow chart of a low power consumption control method of a power chip provided in an embodiment of the present invention.

[0034] Reference Manual Attached Figure 2 , showing a schematic structural diagram of a power chip low power consumption control circuit provided by an embodiment of the present invention.

[0035] Figure 2 In the figure, 1 represents the power device, which can be N-channel MOSFET, and 2 represents the N-channel discharge transistor. The control module is the core control part of the system, which is used to receive the data of the multi-modal detection module (such as the load circuit power and temperature) and control the output signal of the driver according to these data. The multi-modal detection module is used to monitor the power of the load circuit and the temperature of the power device in real time, and provide them to the control module for dynamic adjustment. VCC represents the power supply of the logic circuit of the driver, that is, the internal voltage source, which provides the basic working voltage to ensure the normal operation of the driver. V DRV It is the voltage source of the driver output stage, i.e. the driving voltage source, which provides the voltage amplitude of the driving signal. GATEis the gate resistor. OUT and The first output and the second output are mutually inverted outputs. GND represents grounding.

[0036] The embodiment of the present invention provides a low-power control method for a power chip, which is applied to a low-power control circuit of a power chip. The low-power control circuit of the power chip includes an output driver, a driving voltage source, a decoupling capacitor, a gate resistor, an N-groove discharge transistor, a power device, a multi-modal detection module and a control module. The output driver includes an internal voltage source, a first output, a second output and a ground node. The output driver is used to control the level signal of the first output and the second output, and the internal voltage source, the driving voltage source, the decoupling capacitor and the ground node are connected in series in sequence to form a closed loop connected in parallel to the output driver. The first output is connected to the ground through the gate resistor, the drain of the N-groove discharge transistor, the gate of the power device and the source of the power device in sequence. The drain of the power device is connected in series to the load circuit. The second output is grounded through the gate of the N-groove discharge crystal and the source of the N-groove discharge transistor. The multi-modal detection module is connected to the load circuit, and the control module is connected to the internal voltage source, the driving voltage source and the multi-modal detection module respectively. Among them, the first output and the second output are mutually inverted outputs.

[0037] Among them, the control module is used to receive data (such as load power and power device temperature) from the multi-modal detection module, and control the output signal of the driver according to these real-time data. The control module will dynamically adjust the PWM signal duty cycle and drive voltage to optimize the operating state of the power device and achieve the purpose of low power consumption. The multi-modal detection module is used to monitor the real-time data of the load circuit. The power of the load circuit and the temperature of the power device are detected in real time, and this information is fed back to the control module. The control module can dynamically adjust the drive signal according to the actual power demand and temperature conditions to ensure that the power device operates under low power consumption conditions. The internal voltage source provides the basic operating voltage of the driver to ensure the normal operation of the internal logic circuit of the driver. VCC belongs to the internal power supply of the driver and is used to generate the driver control signal. The drive voltage source provides the voltage amplitude of the drive signal, which directly affects the level signal strength of the driver output. The voltage of the drive voltage source determines the drive voltage of the gate of the main power device, ensuring that the gate voltage is high enough so that the power device can quickly and stably enter the on state. The gate resistor controls the charging and discharging speed of the gate, suppresses the transient current generated during the switching process, thereby reducing the loss caused by electromagnetic interference (EMI) and peak current, ensuring that the power device does not generate excessive transient current during the switching process, and reducing the switching loss. The first output and the second output are output signals that are inverted from each other. The first output is connected to the gate of the main power device to control its on and off. The second output is connected to the gate of the N-groove discharge transistor to assist in the rapid discharge of the gate charge of the main power device. The design of the inverted output ensures that when the main power device is turned on, the N-groove discharge transistor is turned off. When the main power device is turned off, the N-groove discharge transistor is turned on, quickly discharges the gate charge of the main power device, and achieves rapid shutdown. The power device is controlled to turn on or off by the gate voltage provided by the first output. When the power device is turned on, current flows in the load circuit. When the power device is turned off, the current is cut off. The working state of the power device determines the power consumption of the entire circuit, so accurately controlling its switching state helps to reduce power consumption. The N-channel discharge transistor is turned on when the main power device is turned off, and the gate charge of the power device is quickly discharged to the ground to achieve rapid shutdown of the power device. By controlling the main power device in reverse phase, it ensures that the gate is quickly discharged during the turn-on and turn-off process, thereby reducing heat accumulation and further reducing power consumption. The decoupling capacitor is connected between the driving voltage source and the ground to filter out high-frequency noise in the driving power supply, ensure the stability of the driving voltage source, and avoid the power supply voltage fluctuation affecting the stability of the driving signal. It helps the driving signal remain stable, thereby ensuring the reliability of the gate drive.

[0038] It should be noted that the circuit achieves precise control of power devices through the collaboration of the multi-modal detection module and the control module, combined with a dual-output drive structure that is inverted from each other. The functions of each component complement each other, and by dynamically adjusting the drive signal, suppressing transient current and rapid discharge, it effectively reduces power consumption and improves the operating efficiency and reliability of the power chip.

[0039] The processing flow of the low power consumption control method of the power chip may include the following steps:

[0040] S1: Collect load power, power device temperature and power chip response time through the multi-modal detection module.

[0041] It should be noted that the load power, power device temperature and response time of the power chip are collected through the multi-modal detection module. These real-time data provide an important basis for subsequent control decisions, ensuring dynamic adjustments under different working conditions to optimize the low-power operation effect of the power chip.

[0042] S2: Input the load power, the power device temperature and the power device response time into the control module.

[0043] S3: Estimate the real-time parasitic parameter disturbance term through an adaptive disturbance observer according to the response time of the power device.

[0044] Among them, the adaptive disturbance observer is a control algorithm that can monitor and estimate the disturbances introduced by external factors or changes in component characteristics in the system in real time. Its core function is to adaptively adjust its own parameters according to the real-time feedback of the system state to accurately track and estimate the disturbances that may exist in the system. Parasitic parameter disturbance terms refer to changes in parasitic resistance, parasitic capacitance and parasitic inductance caused by factors such as environmental and load changes. These disturbance terms may cause fluctuations in the switching speed, power consumption and stability of power devices, so real-time monitoring and compensation are required to ensure the normal operation of power chips. Parasitic resistance disturbances will increase switching losses and affect the conduction efficiency of power devices. Parasitic capacitance disturbances will affect the response time and switching speed of the device and increase delays. Parasitic inductance disturbances will generate voltage spikes during switching, causing electromagnetic interference. Through the adaptive disturbance observer, the real-time parasitic parameter disturbance terms (such as fluctuations in parasitic resistance, capacitance and inductance) are estimated based on the response time of the power device to ensure accurate estimation of these parasitic effects, thereby improving the accuracy and stability of control and reducing power losses caused by parasitic factors. The adaptive disturbance observer estimates these parasitic parameter disturbance terms to help the power chip control system compensate for parasitic effects in real time, reduce power loss, and ensure that the chip works stably under low power consumption and high efficiency conditions.

[0045] In a possible implementation manner, the real-time parasitic parameter disturbance term includes a real-time parasitic resistance disturbance term, a real-time parasitic capacitance disturbance term, and a real-time parasitic inductance disturbance term.

[0046] It should be noted that the estimation methods of these disturbance terms can all be estimated in the same way, that is, through an adaptive disturbance observer.

[0047] In a possible implementation, S3 specifically includes:

[0048] S301: Establishing a correlation equation between the response time of the power device and the parasitic parameter disturbance term:

[0049]

[0050] in, Indicates the response time of the power device The rate of change over time t, represents the system input at time t representing the output voltage of the driving voltage source at time t, Indicates that the power chip is at a given and Down The value of It represents the parasitic parameter disturbance term at time t including parasitic resistance, parasitic capacitance and parasitic inductance.

[0051] S302: Based on the association relationship, determine the adaptive disturbance observer:

[0052]

[0053] in, and They represent the state estimation, The estimation and perturbation estimation of The estimate of K represents the observer gain matrix, express The rate of change over time t, express The rate of change over time t, Represents adaptive gain.

[0054] Among them, the observer gain matrix is ​​a parameter matrix of the observer system, which determines the response strength of the system to state errors and disturbances. The adaptive gain is a dynamic adjustment parameter used to change the sensitivity of the observer in real time to adapt to changes in disturbances.

[0055] In a possible implementation, the observer gain matrix is ​​specifically:

[0056]

[0057] Among them, K represents the observer gain matrix, Q represents the symmetric positive definite matrix of the identity matrix, T represents the transpose, and P is a positive definite matrix obtained by solving the Lyapunov stability theory. represents the inverse of P, A represents the state matrix of the dynamic relationship between state variables in the low-power control circuit of the power chip, and B represents the input matrix describing how the control input of the low-power control circuit of the power chip affects the state variables.

[0058] It should be noted that the observer gain matrix is ​​obtained by solving the Lyapunov stability theory. The advantage of this setting is that it can ensure the stability and rapid convergence of the system in dynamic changes. The positive definiteness of the gain matrix is ​​guaranteed, and the gain value is adjusted through the dynamic relationship between the state matrix and the input matrix, so that the observer has stronger robustness and control accuracy when tracking disturbance changes. It not only improves the response speed of the system, but also ensures the overall stability of the system.

[0059] The adaptive gain is specifically:

[0060]

[0061]

[0062] in, represents the adaptive gain, represents the state estimation error The norm of represents the initial adaptive gain based on Lyapunov stability theory.

[0063] Among them, the adaptive gain is used to control the convergence speed of the disturbance estimation to ensure that the disturbance estimation can quickly track the norm of the actual disturbance state estimation error, and is used to dynamically adjust the size of the adaptive gain. The larger the error, the larger the adaptive gain, thereby speeding up the response speed of the disturbance estimation. The adaptive gain is dynamically adjusted according to the norm of the state estimation error, and the gain can be automatically increased when the error is large, thereby speeding up the estimation speed of the disturbance term. When the error is small, the gain is reduced to prevent the system from over-adjusting. The setting of the initial adaptive gain is based on the Lyapunov stability theory to ensure that the initial state of the observer is stable. This adaptive adjustment enables the observer to flexibly respond to the estimation requirements under different disturbance conditions and achieve more accurate and efficient disturbance compensation.

[0064] S303: Obtain a real-time parasitic parameter disturbance term using the determined adaptive disturbance observer.

[0065] In the actual application process, the influence of parasitic resistance, capacitance and inductance on the system response is first described by establishing the correlation between the response time of the power device and the parasitic parameter disturbance term. Then, through this relationship, an adaptive disturbance observer is determined to ensure that the observer has good stability and convergence. The observer gain matrix and adaptive gain will be dynamically adjusted according to the system state, so that the observer can accurately estimate the disturbance term. Finally, the parasitic parameter disturbance term is obtained in real time through the adaptive disturbance observer, so as to accurately compensate for the fluctuation of these parameters. In this way, the uncertainty caused by parasitic effects is effectively suppressed, ensuring that the system can still accurately control the response under parasitic interference conditions, and improving the efficiency and stability of the power chip.

[0066] S4: With the goal of reducing heat loss of the power device, determine a first constraint on the duty cycle of the PWM signal of the internal voltage source.

[0067] Among them, the duty cycle of the PWM signal refers to the ratio of the time when the signal is high level to the total cycle in a PWM (pulse width modulation) cycle, usually expressed as a percentage. By optimizing the duty cycle, the control module can ensure that the conduction loss is minimized while meeting the working requirements of the power device, and reduce the heat accumulation problem caused by long-term high level. This method effectively balances the switching loss and conduction loss, ensuring that the power chip operates under the best thermal management conditions. In accordance with the physical characteristics of the power device, the duty cycle is adjusted so that the on-resistance is always in the best conduction state, that is, the on-resistance is minimum, and the goal of minimum on-resistance is converted to minimum total loss, so as to reduce the conduction loss in the global state, not limited to the minimum on-resistance. Ensure that the duty cycle of the PWM signal is neither too high nor too low, which can reduce heat accumulation, but will not be too high to cause unnecessary switching losses.

[0068] In a possible implementation, the first constraint is specifically:

[0069] & D new = arg min D∈[ D min , D max ] P total D min = 1 - ε D max = ε P total =α⋅ P conduction +β⋅ P switch P conduction = I D 2 ⋅ R on R on = f`(T, V gs , I D ) P switch = f sw ⋅( E on + E off )

[0070] in, arg min D∈[ D min , D max ] P total Represents the total conduction loss The minimum PWM signal duty cycle , Indicates the preset constant to avoid the PWM signal duty cycle being 0 or 100. and They represent the maximum duty cycle and the minimum duty cycle respectively, and α and β represent the conduction loss of the power device respectively. and switching losses The sensitivity weight of Indicates the relationship between power device temperature T and gate voltage V GS and drain current I D The related on-resistance, Indicates the power device specifications determined based on With T, ,I D The relationship between Indicates the switching frequency of the power device , open energy and turn-off energy Related switching losses.

[0071] It should be noted that those skilled in the art can set the size of the preset constant according to actual needs, and the present invention is not limited here.

[0072] Specifically, the sensitive weights can be set to 0.5 and 0.5, or different values ​​can be set according to actual needs. In this constraint, the total loss is minimized by setting the duty cycle of the PWM signal to reduce conduction loss and switching loss. The duty cycle of PWM is limited to a certain range to ensure that the signal does not approach the limit value to avoid unnecessary power consumption. The conduction loss and switching loss are combined in the loss calculation, and the duty cycle is dynamically adjusted in combination with factors such as temperature and gate voltage to optimize the working efficiency of the power chip.

[0073] S5: With the goal of reducing the response time of the power device, determine a second constraint on the output voltage of the driving voltage source.

[0074] It should be noted that the second constraint ensures that the driving signal (such as gate driving voltage) for the power device is high enough to quickly put the device into a saturated conduction state, but not too high to avoid unnecessary losses.

[0075] In a possible implementation, the second constraint is specifically:

[0076] & V gs,opt = arg min V gs ∈[ V gs,min , V gs,max ] t response ( V gs )+k⋅ P total ( V gs ) & t response ( V gs )= C lss ⋅ V gs,sat I drive (1- e - V gs - V th V gs,sat - V th ) & V gs , min = V th + Δ V m arg in & V gs , max = min( V gs , sat , V gs , max , spec )

[0077] in, represents the optimal output voltage, k=0.1 represents the correction coefficient between the response time and the total conduction loss, Indicates the current output voltage, i.e. the gate voltage The total conduction loss under V th It represents the minimum gate voltage that turns on the power device. It indicates the minimum gate voltage that ensures that the power device can enter the on state within the expected time. It indicates the maximum gate voltage that the power device can reach when the additional loss is less than the preset additional loss. Min indicates the minimum value. The saturation conduction voltage indicates that the power device enters the saturation conduction state. Representation and The relevant power device response time, Represents the total capacitance of the low-power control circuit of the power chip, Indicates the maximum gate voltage allowed by the power device, Indicates the gate voltage safety margin.

[0078] It should be noted that those skilled in the art can set the size of the preset additional loss according to actual needs, and the present invention is not limited here.

[0079] It should be noted that in this second constraint, the response speed and total conduction loss of the power device are balanced by optimizing the output voltage to achieve the best operating efficiency. The set minimum gate voltage and maximum gate voltage ensure that the power device strikes a balance between safety and efficiency, and can quickly enter the conduction state without generating too much additional loss. At the same time, the relationship between the response time and the gate voltage further controls the response speed, so that the power chip always maintains low power consumption under different workloads.

[0080] S6: Determine the target PWM signal duty cycle of the output voltage source and the target output voltage of the driving voltage source under the first constraint and the second constraint in combination with the real-time parasitic parameter disturbance term.

[0081] It should be noted that, combined with the parasitic parameter disturbance terms detected in real time, the target PWM duty cycle of the output voltage source and the target output voltage of the driving voltage source are determined under the conditions of the first constraint (PWM signal duty cycle) and the second constraint (driving voltage source output voltage), respectively, to ensure that while suppressing parasitic effects, heat accumulation is reduced, so that the power devices can operate efficiently under stable and low temperature conditions, further reducing unnecessary energy losses.

[0082] In a possible implementation, S6 specifically includes:

[0083] S601: Obtain parasitic resistance disturbance, parasitic capacitance disturbance and parasitic inductance disturbance based on real-time parasitic parameter disturbance items.

[0084] S602: Correcting the on-resistance of the power device based on the parasitic resistance disturbance:

[0085]

[0086] in, Indicates the combined parasitic resistance disturbance On-resistance The on-resistance obtained after correction.

[0087] S603: Correcting the response time of the power device based on the parasitic capacitance disturbance:

[0088]

[0089] in, Indicates the corrected power device response time, represents the parasitic capacitance disturbance, Represents the capacitance between the gate and source of the power device, express The drive current generated by applying to the gate of a power device.

[0090] S604: Based on the corrected on-resistance and parasitic inductance disturbance, determine the corrected total conduction loss:

[0091]

[0092] in, represents the corrected total conduction loss, represents the parasitic inductance disturbance, Represents the drain current flowing through the power device.

[0093] S605: Within the first constraint, determine a target PWM signal duty cycle that minimizes the corrected total conduction loss by using a table lookup method.

[0094] S606: Within the second constraint, determine the target output voltage that minimizes the corrected power device response time by using a table lookup method:

[0095] V gs , opt adj = arg min V gs ∈[ V gs , min , V gs , max ] t response adj ( V gs )+k⋅ P total ( V gs )

[0096] in, Indicates the target output voltage.

[0097] Specifically, in the process of S6, the disturbance items of parasitic resistance, parasitic capacitance and parasitic inductance are first obtained through real-time monitoring, and the key parameters of the power device are gradually corrected. The parasitic resistance disturbance will affect the on-resistance of the power device, so it is corrected in S602. The parasitic capacitance disturbance affects the response time, so the response time is corrected in S603. The parasitic inductance disturbance affects the total conduction loss, so the total loss is further corrected in S604. Then, under the first constraint (minimum total conduction loss), the corresponding optimal PWM duty cycle is found (S605). Under the second constraint (minimum response time), the corresponding optimal gate drive voltage is determined (S606). This process ensures that the power device can quickly enter the saturated conduction state to achieve an ideal state close to zero switching loss, thereby maximizing the system efficiency under high-frequency operation. Ensure that the drive signal (such as the gate drive voltage) to the power device is high enough to quickly put the device into the saturated conduction state. Increase the switching speed to reduce the transition time and switching loss. This means that at the moment of switching, current or voltage will not exist at the same time, and the energy loss during the switching process is very low. It works at a very high frequency without being restricted by the switching time, thereby improving the overall efficiency of the system.

[0098] S7: Control the power chip according to the target PWM signal duty cycle and the target output voltage.

[0099] In actual applications, by adjusting the PWM signal duty cycle, reducing the on-time and reducing heat accumulation, the power device can operate at a lower on-resistance and save power. In addition, the applied on-voltage can be automatically adjusted according to the real-time load power, so that the power device can execute the switching state with extremely low latency, which can greatly reduce the power loss of the power device.

[0100] In a possible implementation, S7 specifically includes:

[0101] S701: Generate a first instruction and a second instruction in a control module, wherein the first instruction is to adjust the duty cycle of a PWM signal to a target PWM signal duty cycle, and the second instruction is to adjust the output voltage to a target output voltage.

[0102] S702: Control the internal voltage source according to the first instruction, and control the driving voltage source according to the second instruction to complete the control of the power chip.

[0103] In actual application, during the entire low-power control process, the system collects data such as load power, temperature and response time of the power chip in real time through the multi-modal detection module, and inputs these data into the control module. Next, the control module estimates the disturbance terms of parasitic resistance, capacitance and inductance through the adaptive disturbance observer, and further adjusts the on-resistance, response time and total loss of the power chip according to these disturbance terms. By setting the duty cycle of the PWM signal and the constraints of the output voltage of the driving voltage source, the target PWM duty cycle and target output voltage of the power chip are finally determined to ensure fast switching under the condition of minimum loss, thereby optimizing the efficiency of the power chip. In S7, the control module adjusts the PWM duty cycle and driving voltage by generating instructions to ensure that the power device works in the best state and achieve the goal of energy saving and consumption reduction.

[0104] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0105] In the present invention, by setting a power chip low-power control circuit with two output terminals with mutually inverted outputs, one of which is connected to an N-groove discharge transistor, the gate charge can be quickly charged and discharged to complete the rapid on-off of the power device, reducing the on-time, thereby avoiding the problem of increased on-resistance caused by heat accumulation, maintaining the on-resistance in a low on-resistance state, and saving the power chip on-power consumption. In addition, the setting of the gate resistance can suppress the transient current generated during the switching process, reduce the generation of peak current, reduce the electromagnetic interference of the power device switching process, and further reduce the loss caused by the instantaneous current mutation of the switch. In addition, in the control circuit, through the multi-modal detection module and the control module, according to the detected power device data, an adaptive disturbance observer estimator is introduced to estimate the real-time disturbance, and then the on-voltage and PWM signal duty cycle applied to the gate are adaptively compensated, so that the power device can enable the power device to quickly enter the saturated on-state, further improve the switching speed, reduce heat accumulation, and reduce control power consumption.

[0106] Reference Manual Attached Figure 3 , showing a schematic structural diagram of a low power consumption control system of a power chip provided by the present invention.

[0107] The present invention further provides a low power consumption control system 20 for a power chip, which is applied to the low power consumption control method for the power chip, comprising:

[0108] Processor 201.

[0109] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201 , the low power consumption control method of the power chip according to the method embodiment is implemented.

[0110] The low power consumption control system 20 of the power chip provided by the present invention can execute the low power consumption control method of the power chip mentioned above and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate on them.

[0111] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0112] In the present invention, by setting a power chip low-power control circuit with two output terminals with mutually inverted outputs, one of which is connected to an N-groove discharge transistor, the gate charge can be quickly charged and discharged to complete the rapid on-off of the power device, reducing the on-time, thereby avoiding the problem of increased on-resistance caused by heat accumulation, maintaining the on-resistance in a low on-resistance state, and saving the power chip on-power consumption. In addition, the setting of the gate resistance can suppress the transient current generated during the switching process, reduce the generation of peak current, reduce the electromagnetic interference of the power device switching process, and further reduce the loss caused by the instantaneous current mutation of the switch. In addition, in the control circuit, through the multi-modal detection module and the control module, according to the detected power device data, an adaptive disturbance observer is introduced to estimate the real-time disturbance, and then the on-voltage and PWM signal duty cycle applied to the gate are adaptively compensated, so that the power device can enable the power device to quickly enter the saturated on-state, further improve the switching speed, reduce heat accumulation, and reduce control power consumption.

[0113] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0114] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0115] The above embodiments may be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or may be transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired means (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media sets. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium may be a solid-state hard disk.

[0116] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0117] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0118] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0119] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0120] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0121] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0122] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0123] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0124] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0125] An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the low power consumption control method of a power chip as described in the method embodiment is implemented.

[0126] A computer-readable storage medium provided by the present invention can implement the steps and effects of the low power consumption control method for a power chip of the above method embodiment. To avoid repetition, the present invention will not go into details.

[0127] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0128] In the present invention, by setting a power chip low-power control circuit with two output terminals with mutually inverted outputs, one of which is connected to an N-groove discharge transistor, the gate charge can be quickly charged and discharged to complete the rapid on-off of the power device, reducing the on-time, thereby avoiding the problem of increased on-resistance caused by heat accumulation, maintaining the on-resistance in a low on-resistance state, and saving the power chip on-power consumption. In addition, the setting of the gate resistance can suppress the transient current generated during the switching process, reduce the generation of peak current, reduce the electromagnetic interference of the power device switching process, and further reduce the loss caused by the instantaneous current mutation of the switch. In addition, in the control circuit, through the multi-modal detection module and the control module, according to the detected power device data, an adaptive disturbance observer is introduced to estimate the real-time disturbance, and then the on-voltage and PWM signal duty cycle applied to the gate are adaptively compensated, so that the power device can enable the power device to quickly enter the saturated on-state, further improve the switching speed, reduce heat accumulation, and reduce control power consumption.

[0129] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0130] There are a few points to note:

[0131] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0132] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0133] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0134] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A low power consumption control method for a power chip, characterized in that: Applicable to a low-power consumption control circuit of a power chip, the low-power consumption control circuit of the power chip includes an output driver, a driving voltage source, a decoupling capacitor, a gate resistor, an N-groove discharge transistor, a power device, a multi-modal detection module and a control module; The output driver comprises an internal voltage source, a first output, a second output and a ground node; the output driver is used to control the level signals of the first output and the second output, and the internal voltage source, the driving voltage source, the decoupling capacitor and the ground node are sequentially connected in series to form a closed loop connected in parallel to the output driver; The first output is connected to ground in sequence through the gate resistor, the drain of the N-channel discharge transistor, the gate of the power device and the source of the power device; the drain of the power device is connected in series to the load circuit; the second output is connected to ground through the gate of the N-channel discharge transistor and the source of the N-channel discharge transistor; the multi-modal detection module is connected to the load circuit, and the control module is connected to the internal voltage source, the driving voltage source and the multi-modal detection module respectively; wherein the first output and the second output are mutually inverted outputs; the method comprises: S1: collecting load power, power device temperature and power chip response time through the multi-modal detection module; S2: inputting the load power, the power device temperature and the power device response time into the control module; S3: estimating a real-time parasitic parameter disturbance term through an adaptive disturbance observer according to the response time of the power device; S4: with the goal of reducing the heat loss of the power device, determining a first constraint on the duty cycle of the PWM signal of the internal voltage source; S5: determining a second constraint on the output voltage of the driving voltage source with the goal of reducing the response time of the power device; S6: Determine, in combination with the real-time parasitic parameter disturbance term, a target PWM signal duty cycle of the output voltage source and a target output voltage of the driving voltage source under the first constraint and the second constraint respectively; S7: Controlling the power chip according to the target PWM signal duty cycle and the target output voltage.

2. The low power consumption control method of a power chip according to claim 1, characterized in that: The real-time parasitic parameter disturbance term includes a real-time parasitic resistance disturbance term, a real-time parasitic capacitance disturbance term and a real-time parasitic inductance disturbance term.

3. The low power consumption control method of a power chip according to claim 1, characterized in that: The S3 specifically includes: S301: Establishing a correlation equation between the response time of the power device and the parasitic parameter disturbance term: ， in, Indicates the response time of the power device The rate of change over time t, represents the system input at time t representing the output voltage of the driving voltage source at time t, Indicates that the power chip is at a given and Down The value of represents the parasitic parameter disturbance term at time t including parasitic resistance, parasitic capacitance and parasitic inductance; S302: Based on the association relationship, determine the adaptive disturbance observer: ， in, and They represent the state estimation, The estimation and perturbation estimation of The estimate of K represents the observer gain matrix, express The rate of change over time t, express The rate of change over time t, represents adaptive gain; S303: Obtain a real-time parasitic parameter disturbance term using the determined adaptive disturbance observer.

4. The low power consumption control method of a power chip according to claim 3, characterized in that: The observer gain matrix is ​​specifically: ， Among them, K represents the observer gain matrix, Q represents the symmetric positive definite matrix of the identity matrix, T represents the transpose, and P is a positive definite matrix obtained by solving the Lyapunov stability theory. represents the inverse of P, A represents the state matrix of the dynamic relationship between the state variables in the low power control circuit of the power chip, and B represents the input matrix describing how the control input of the low power control circuit of the power chip affects the state variables; The adaptive gain is specifically: ， ， in, represents the adaptive gain, represents the state estimation error The norm of represents the initial adaptive gain based on Lyapunov stability theory.

5. The low power consumption control method of a power chip according to claim 1, characterized in that: The first constraint is specifically: ， in, Represents the total conduction loss The minimum PWM signal duty cycle , Indicates the preset constant to avoid the PWM signal duty cycle being 0 or 100. and They represent the maximum duty cycle and the minimum duty cycle respectively, and α and β represent the conduction loss of the power device respectively. and switching losses The sensitivity weight of Indicates the relationship between power device temperature T and gate voltage V GS and drain current I D The related on-resistance, Indicates the power device specifications determined based on With T, ,I D The relationship between Indicates the switching frequency of the power device , open energy and turn-off energy Related switching losses.

6. The low power consumption control method of a power chip according to claim 5, characterized in that: The second constraint is specifically: ， in, represents the optimal output voltage, k=0.1 represents the correction coefficient between the response time and the total conduction loss, Indicates the current output voltage, i.e. the gate voltage The total conduction loss under V th It represents the minimum gate voltage that turns on the power device. It indicates the minimum gate voltage that ensures that the power device can enter the on state within the expected time. It indicates the maximum gate voltage that the power device can reach when the additional loss is less than the preset additional loss. Min indicates the minimum value. The saturation conduction voltage indicates that the power device enters the saturation conduction state. Representation and The relevant power device response time, Represents the total capacitance of the low-power control circuit of the power chip, Indicates the maximum gate voltage allowed by the power device, Indicates the gate voltage safety margin; express The drive current generated by applying to the gate of a power device.

7. The low power consumption control method of a power chip according to claim 6, characterized in that: The S6 specifically includes: S601: Obtaining parasitic resistance disturbance, parasitic capacitance disturbance and parasitic inductance disturbance based on the real-time parasitic parameter disturbance item; S602: Correcting the on-resistance of the power device based on the parasitic resistance disturbance: ， in, Indicates the combined parasitic resistance disturbance On-resistance The on-resistance obtained after correction; S603: Correcting the response time of the power device based on the parasitic capacitance disturbance: ， in, Indicates the corrected power device response time, represents the parasitic capacitance disturbance, Represents the capacitance between the gate and source of the power device, express The drive current generated by applying to the gate of the power device; S604: Determine a corrected total conduction loss based on the corrected on-resistance and the parasitic inductance disturbance: ， in, represents the corrected total conduction loss, represents the parasitic inductance disturbance, Represents the drain current flowing through the power device; S605: Determine, within the first constraint, by table lookup method, a target PWM signal duty cycle that minimizes the corrected total conduction loss; S606: Within the second constraint, determine the target output voltage that minimizes the corrected power device response time by using a table lookup method: ， in, Indicates the target output voltage.

8. The low power consumption control method of a power chip according to claim 1, characterized in that: The S7 specifically includes: S701: Generate a first instruction and a second instruction in the control module, wherein the first instruction is to adjust the duty cycle of the PWM signal to the target PWM signal duty cycle, and the second instruction is to adjust the output voltage to the target output voltage; S702: Control the internal voltage source according to the first instruction, and control the driving voltage source according to the second instruction to complete the control of the power chip.

9. A low power consumption control system for a power chip, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the low power consumption control method for a power chip according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the low power consumption control method of the power chip according to any one of claims 1 to 8 is implemented.

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