Re-timing circuit, multimode frequency divider and electronic equipment

Abstract

The invention discloses a retiming circuit, a multimode frequency divider and electronic equipment, and the retiming circuit comprises a second unit which comprises a plurality of transistors connected in series, and generates an intermediate signal according to a clock signal and a modulus signal; the third unit comprises a plurality of transistors connected in series, a second output signal is generated according to the intermediate signal, a reference signal and a clock signal, a reverse signal of the second output signal is a target output signal, the modulus signal and the reference signal have the same frequency, and the first output signal and the second output signal have the same frequency. The rising edge of the modulus signal determines the rising edge of the output signal, and the falling edge of the reference signal determines the falling edge of the output signal. According to the re-timing circuit, the multimode frequency divider and the electronic equipment provided by the invention, the output signal with the target frequency and the target duty ratio is generated through the new re-timing circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a re-timing circuit, a multi-mode frequency divider and an electronic device. Background Art

[0002] In the application of integrated circuits, the clock system is an important module in chip design. In order to meet the different clock requirements of the system, a phase-locked loop circuit (PLL) is used.

[0003] The phase-locked loop circuit includes a frequency detector, a charge pump, a filter, an oscillator, and a multi-mode divider connected in sequence; first, the oscillator generates an oscillation signal with a certain frequency through self-excited oscillation. After passing through the multi-mode divider, the signal enters the frequency detector, is compared with the reference signal, and generates a frequency difference and a phase difference signal to enter the charge pump; the charge pump determines the intake current or the pumped current according to the frequency difference and the phase difference, and converts this current into a voltage value; the voltage output by the charge pump is filtered by the filter and enters the oscillator, and the frequency of the oscillation signal is changed by adjusting the value of the variable capacitor in the oscillator.

[0004] The multi-mode divider divides the frequency of the input signal and provides an output signal with a frequency lower than the input signal. The traditional multi-mode divider (MMD) design for low phase noise phase-locked loops requires the function of a retimer circuit. Because a large number of divider logic gates contribute a lot of phase noise, the high-frequency signal input to the multi-mode divider is usually used for retime. However, in this case, the duty cycle of the output signal will be very short, which is not conducive to the operation of the subsequent digital logic.

[0005] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0006] In view of the above problems, an object of the present invention is to provide a re-timing circuit, a multi-mode frequency divider and an electronic device, so as to generate an output signal with a target frequency and a target duty cycle through the new re-timing circuit.

[0007] According to one aspect of the present invention, a retiming circuit is provided, which is connected to a multi-mode frequency division circuit and a logic circuit to receive a modulus signal with a target frequency provided by the multi-mode frequency division circuit and a reference signal provided by the logic circuit, and includes: a second unit, including a plurality of transistors connected in series, generating an intermediate signal according to a clock signal and the modulus signal; a third unit, including a plurality of transistors connected in series, generating a second output signal according to the intermediate signal, the reference signal and the clock signal, the inverse signal of the second output signal being the target output signal, wherein the modulus signal and the reference signal have the same frequency, the rising edge of the modulus signal determines the rising edge of the output signal, and the falling edge of the reference signal determines the falling edge of the output signal.

[0008] Optionally, the second unit includes: a third transistor, a first end of the third transistor is connected to the power supply voltage, and a control end is connected to the input end of the second unit; a fourth transistor, a first end of the fourth transistor is connected to the second end of the third transistor, a second end is connected to the output end of the second unit, and a control end receives the clock signal; a fifth transistor, a first end of the fifth transistor is connected to the second end of the fourth transistor, a second end is connected to the ground end, and a control end is connected to the control end of the third transistor.

[0009] Optionally, the third unit includes: a sixth transistor, a first end of the sixth transistor is connected to the power supply voltage, and a control end is connected to the output end of the second unit; a seventh transistor, a first end of the seventh transistor is connected to the second end of the sixth transistor, a second end is connected to the output end of the third unit, and a control end receives the reference signal; an eighth transistor, a first end of the eighth transistor is connected to the second end of the seventh transistor, and a control end receives the clock signal; a ninth transistor, a first end of the ninth transistor is connected to the second end of the eighth transistor, a second end is connected to the ground end, and a control end is connected to the control end of the sixth transistor.

[0010] Optionally, the input end of the second unit receives a reverse signal of the modulus signal.

[0011] Optionally, it also includes: a first unit, including a plurality of transistors connected in series, the output end of the first unit is connected to the input end of the second unit; a fourth unit, including a plurality of transistors connected in series, the input end of the fourth unit is connected to the output end of the third unit, wherein the input end of the first unit receives the modulus signal, and the output end of the fourth unit outputs the output signal.

[0012] Optionally, the first unit includes: a first transistor, a first end of the first transistor is connected to a power supply voltage, a second end is connected to an output end of the first unit, and a control end is connected to an input end of the first unit; a second transistor, a first end of the second transistor is connected to a second end of the first transistor, a second end is connected to a ground end, and a control end is connected to a control end of the first transistor.

[0013] Optionally, the fourth unit includes: a tenth transistor, a first end of the tenth transistor is connected to the power supply voltage, a second end is connected to the output end of the fourth unit, and a control end is connected to the output end of the third unit; an eleventh transistor, a first end of the eleventh transistor is connected to the second end of the tenth transistor, a second end is connected to the ground end, and a control end is connected to the control end of the tenth transistor.

[0014] Optionally, it further includes: a fifth unit, including a plurality of transistors connected in series, wherein the input end of the fifth unit is connected to the output end of the fourth unit, and the output end is connected to the input end of the fourth unit to latch the level of the output signal.

[0015] Optionally, the fifth unit includes: a twelfth transistor, a first end of the twelfth transistor is connected to the power supply voltage, and a control end is connected to the output end of the fourth unit; a thirteenth transistor, a first end of the thirteenth transistor is connected to the second end of the twelfth transistor, a second end is connected to the input end of the fourth unit, and a control end receives the reference signal; a fourteenth transistor, a first end of the fourteenth transistor is connected to the second end of the thirteenth transistor, and a control end receives the modulus signal; a fifteenth transistor, a first end of the fifteenth transistor is connected to the second end of the fourteenth transistor, a second end is connected to the ground end, and a control end is connected to the control end of the twelfth transistor.

[0016] Optionally, the first transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor and the tenth transistor are P-type transistors, and the second transistor, the fifth transistor, the eighth transistor, the ninth transistor and the eleventh transistor are N-type transistors; or the twelfth transistor and the thirteenth transistor are P-type transistors, and the fourteenth transistor and the fifteenth transistor are N-type transistors.

[0017] According to another aspect of the present invention, there is provided a multi-mode frequency divider, comprising: a multi-mode frequency division circuit, comprising a plurality of cascaded frequency division modules, for generating a plurality of frequency division signals having different frequencies and lower than the frequency of the clock signal, and at least one modulus signal according to a clock signal; a logic circuit, connected to at least two of the plurality of cascaded frequency division modules, for generating a reference signal according to the at least two frequency division signals; and a retiming circuit, connected to the multi-mode frequency division circuit and the logic circuit, for generating an output signal having a target frequency and a target duty cycle according to the clock signal, the modulus signal and the reference signal.

[0018] Optionally, the logic circuit comprises an OR logic gate, and the OR logic gate performs an OR logic operation on the at least two frequency-divided signals to generate the reference signal.

[0019] According to another aspect of the present invention, there is provided an electronic device comprising the above-mentioned multi-mode frequency divider.

[0020] The retiming circuit, multi-mode frequency divider and electronic device provided by the present invention divide the input oscillation signal through the multi-mode frequency division circuit to obtain multiple divided frequency signals, and the logic circuit generates a reference signal by performing logic operations on some of the divided frequency signals. The rising edge of the output signal of the retiming circuit is triggered according to the modulus signal output by any frequency division module in the multi-mode frequency divider, and the falling edge of the output signal of the retiming circuit is triggered according to the falling edge of the reference signal. By using different signals to redefine the rising edge and falling edge of the output signal, the retiming circuit of the present application can avoid the noise generated by the logic gates in a large number of frequency division circuits, achieve low phase noise, and can better define the duty cycle of the output signal of the retiming circuit to achieve efficient and accurate operation of the electronic device.

[0021] Furthermore, in actual applications, the retiming circuit, multi-mode divider and electronic device of the present application has three stages. In the first stage, the modulus signal is triggered by the input clock signal, so that the output signal of the retiming circuit is high level; in the second stage, the level of the output signal is locked at the output value to avoid changes in the output value due to leakage; in the third stage, the falling edge of the reference signal is triggered to make the output signal become low level, so that it will not be triggered by the clock signal. Therefore, the retiming circuit of the present application can well define the duty cycle of the output signal.

[0022] Furthermore, in the re-timing circuit, multi-mode frequency divider and electronic device of the present application, the re-timing circuit is implemented by using multiple transistors, so that the design of the circuit is simple and easy to implement, and has lower current and smaller area. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention is shown;

[0025] Figure 2 A schematic structural diagram of a multi-mode frequency divider according to an embodiment of the present invention is shown;

[0026] Figure 3 shows a detailed structural diagram of a multi-mode frequency divider according to an embodiment of the present invention;

[0027] Figure 4 shows a working waveform diagram of a multi-mode frequency divider according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of the structure of a re-timing circuit according to a first embodiment of the present invention is shown;

[0029] Figure 6 shows a working waveform diagram of the re-timing circuit according to the first embodiment of the present invention;

[0030] Figure 7 A schematic diagram of the structure of a re-timing circuit according to a second embodiment of the present invention is shown;

[0031] Figure 8 FIG. 4 is a schematic diagram showing the structure of a re-timing circuit according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0032] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0033] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0034] Figure 1 A schematic structural diagram of an electronic device according to an embodiment of the present invention is shown.

[0035] refer to Figure 1The electronic device 100 of the present application includes: a frequency detector 110, a charge pump 120, a filter 130, an oscillator 130, and a multi-mode frequency divider 150. The oscillator 140 generates an oscillation signal with a certain frequency through self-excited oscillation. After the oscillation signal passes through the multi-mode frequency divider 150, it enters the frequency detector 110, is compared with the reference signal, and generates a frequency difference and a phase difference signal to enter the charge pump 120; the charge pump 120 determines the intake current or the pumping current according to the frequency difference and the phase difference, and converts the current into a voltage value; the voltage output by the charge pump 120 enters the oscillator 140 after being filtered by the filter 130, and the frequency of the oscillation signal is changed by adjusting the value of the variable capacitor in the oscillator 140.

[0036] The multi-mode frequency divider 150 includes a re-timing circuit for redefining the timing of the rising edge and the falling edge of the output signal of the multi-mode frequency divider 150 so that the output signal has low phase noise and a good duty cycle.

[0037] Figure 2 A schematic structural diagram of a multi-mode frequency divider according to an embodiment of the present invention is shown.

[0038] refer to Figure 2 The multi-mode frequency divider 150 of the present application includes a multi-mode frequency division circuit 151, a logic circuit 152 and a re-timing circuit 153. The multi-mode frequency division circuit 151 divides the received clock signal CKIN to obtain a plurality of frequency-reduced frequency division signals and a modulus signal. The logic circuit 152 is connected to the multi-mode frequency division circuit 151 and generates a reference signal Falling according to at least two frequency division signals output by the multi-mode frequency division circuit 151. The re-timing circuit 153 is connected to the multi-mode frequency division circuit 151 and the logic circuit 152 and redefines the time of the rising edge and the falling edge of the modulus signal output by the multi-mode frequency division circuit 151 according to the clock signal CKIN and the reference signal Falling, so that the output signal CKOUT has a target frequency and a target duty cycle, and has the advantages of low phase noise and a good duty cycle.

[0039] refer to Figure 3 In the multi-mode frequency divider 150 of the present application, the multi-mode frequency division circuit 151 includes a plurality of frequency division modules. Figure 3 In the illustrated embodiment, the multi-mode frequency division circuit 151 is a five-stage frequency division circuit, including five cascaded frequency division modules, namely a first frequency division module 1511, a second frequency division module 1512, a third frequency division module 1513, a fourth frequency division module 1514 and a fifth frequency division module 1515.

[0040] Among them, the five cascaded frequency division modules are, for example, basic frequency division modules, and their frequency division ratio is, for example, 1 / 2 or 1 / 3 (DIV2 / 3). Each frequency division module includes a first input terminal, a first output terminal, a second input terminal, and a second output terminal. The first input terminal is used to receive an input signal, the first output terminal is used to output a frequency division signal, the second input terminal is used to receive a modulus signal, and the second output terminal is used to output a modulus signal. Specifically, among the five cascaded frequency division modules, the first input terminal of the first frequency division module 1511 receives a clock signal CKIN, and the first output terminal outputs a first frequency division signal f1. The first input terminal of the second frequency division module 1512 is connected to the first output terminal of the first frequency division module 1511 to divide the first frequency division signal f1 again; and so on, the first input terminal of the frequency division module is connected to the first output terminal of the frequency division module of the previous stage. In addition, the second output terminal of the fifth frequency division module 1515 outputs the fifth modulus signal m4; the second input terminal of the fourth frequency division module 1514 is connected to the second output terminal of the fifth frequency division module 1515, that is, the second input terminal of the frequency division module is connected to the second output terminal of the frequency division module of the next stage. The first output terminal of the frequency division module of the last stage outputs the corresponding frequency division signal, and since it does not have a frequency division module of the next stage, the second input terminal of the frequency division module of the last stage can be connected to a fixed signal, for example.

[0041] The logic circuit 152 includes, for example, an OR logic gate, the first input end of which is connected to the first output end of the third frequency division module 1513, the second input end of which is connected to the first output end of the fourth frequency division module 1514, and the output end outputs a reference signal, which is generated by the OR logic operation of the third frequency division signal f3 and the fourth frequency division signal f4. In other embodiments, the logic circuit 152 may also use other logic gates to achieve the purpose of controlling the falling edge time of the output signal of the re-timing circuit 153. At present, in other embodiments, technicians may also appropriately replace the frequency division signals received by the two input ends of the logic circuit 152 as needed to replace the falling edge time of the reference signal, thereby adjusting the falling edge time of the output signal of the re-timing circuit 153.

[0042] The retiming circuit 153 includes three input terminals and one output terminal, wherein the first input terminal is connected to the second output terminal of the first frequency division module 1511 to receive the first modulus signal m0, the second input terminal receives the clock signal CKIN, and the third input terminal is connected to the output terminal of the logic circuit 152 to receive the reference signal Falling. In the retiming circuit 153, the frequency of the output signal CKOUT is the same as the frequency of the first modulus signal m0 received by the first input terminal and the reference signal Falling received by the third input terminal, so that the duty cycle of the output signal CKOUT is consistent. The clock signal CKIN is used to trigger the rising edge of the first modulus signal m0 so that it is transmitted to the output terminal of the retiming circuit 153, and the reference signal Falling is used to define the falling edge time of the output signal, so that the retiming circuit 153 can generate an output signal with a good duty cycle. In other embodiments, the input terminal of the retiming circuit 153 can also be connected to the second output terminal of other frequency division modules to select an output signal with a suitable frequency.

[0043] Figure 4 Shows Figure 3 The working waveform of the multi-mode frequency divider in FIG. 1 shows how to adjust the duty cycle of the output signal CKOUT. The five frequency division modules in the multi-mode frequency division circuit 151 are, for example, frequency division modules of ÷2, and the frequency of the frequency division signal outputted by the frequency division module is 1 / 2 of the input signal.

[0044] refer to Figure 3 and Figure 4 After the high-frequency clock signal CKIN passes through the first frequency division module 1511, the frequency of the first frequency division signal f1 outputted is 1 / 2 of the frequency of the clock signal CKIN, and after the first frequency division signal f1 passes through the second frequency division module 1512, the frequency of the second frequency division signal f2 is 1 / 2 of the frequency of the first frequency division signal f1. Similarly, the frequency of the third frequency division signal f3 is 1 / 2 of the frequency of the second frequency division signal f2, and the frequency of the fourth frequency division signal f4 is 1 / 2 of the frequency of the third frequency division signal f3.

[0045] The logic circuit 152 performs an OR logic operation on the third frequency-divided signal f3 and the fourth frequency-divided signal f4. The rule of the OR logic operation is: as long as one operand is true, the result is true. Figure 4In the time period t1-t2 of one cycle, at least one of the third frequency-divided signal f3 and the fourth frequency-divided signal f4 is at a high level, so that the reference signal Falling output by the logic circuit 152 is at a high level in the time period t1-t2; in the time period t2-t3, the third frequency-divided signal f3 and the fourth frequency-divided signal f4 are both at a low level, so that the reference signal Falling output by the logic circuit 152 is at a low level in the time period t2-t3; and in the time period t3-t4, the third frequency-divided signal f3 and the fourth frequency-divided signal f4 are both at a high level, so that the reference signal Falling output by the logic circuit 152 is at a high level in the time period t3-t4.

[0046] The re-timing circuit 153 receives the clock signal CKIN, the first modulus signal m0 and the reference signal Falling. At time t1, the rising edge of the first modulus signal m0 is triggered by the clock signal CKIN, so that the signal output by the re-timing circuit 153 becomes a high level. At time t2, the falling edge of the reference signal Falling is triggered by the clock signal CKIN, so that the signal output by the re-timing circuit 153 becomes a low level. At time t4, the rising edge of the first modulus signal m0 is triggered by the clock signal CKIN again, so that the signal output by the re-timing circuit 153 becomes a high level again, and the next cycle begins. Therefore, in the re-timing circuit 153, the falling edge of the reference signal Falling is used as the falling edge trigger time of the output signal CKOUT to adjust the duty cycle of the output signal CKOUT.

[0047] Figure 5 A schematic diagram of the structure of a re-timing circuit according to a first embodiment of the present invention is shown; Figure 6 FIG. 15 shows an operation waveform diagram of the re-timing circuit according to the first embodiment of the present invention. The re-timing circuit 153 uses a plurality of transistors to realize its function.

[0048] refer to Figure 5 The re-timing circuit 153 of the present application includes a first unit 1531, a second unit 1532, a third unit 1533, a fourth unit 1534 and a fifth unit 1535 which are cascaded in sequence. The input end of the first unit 1531 receives the first modulus signal m0; the second unit 1532 generates an intermediate signal according to the clock signal CKIN and the first modulus signal m0; the third unit 1533 generates a second output signal according to the intermediate signal, the reference signal Falling and the clock signal CKIN; the fourth unit 1534 outputs the target output signal CKOUT according to the second output signal; the input end of the fifth unit 1535 is connected to the output end of the fourth unit 1534, and the output end is connected to the input end of the fourth unit 1534 to latch the level of the output signal CKOUT.

[0049] The first unit 1531 includes a first transistor T1 and a second transistor T2 connected in series. The first end of the first transistor T1 is connected to the power supply voltage VCC, the second end is connected to the output end of the first unit 1531, and the control end is connected to the first input end of the re-timing circuit 153 for receiving the first modulus signal m0. The first end of the second transistor T2 is connected to the second end of the first transistor T1, the second end is connected to the ground end GND, and the control end is connected to the control end of the first transistor T1. In this embodiment, the first transistor T1 is, for example, a P-type transistor, and the second transistor T2 is, for example, an N-type transistor.

[0050] The second unit 1532 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5 connected in series. The first end of the third transistor T3 is connected to the power supply voltage VCC, and the control end is connected to the output end of the first unit 1531; the first end of the fourth transistor T4 is connected to the second end of the third transistor T3, the second end is connected to the output end of the second unit 1532, and the control end is connected to the second input end of the re-timing circuit 153; the first end of the fifth transistor T5 is connected to the second end of the fourth transistor T4, the second end is connected to the ground end GND, and the control end is connected to the control end of the third transistor T3. In this embodiment, the third transistor T3 and the fourth transistor T4 are, for example, P-type transistors, and the fifth transistor T5 is, for example, an N-type transistor.

[0051] The third unit 1533 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9 connected in series. The first end of the sixth transistor T6 is connected to the power supply voltage VCC, and the control end is connected to the output end of the second unit 1532; the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, the second end is connected to the output end of the third unit 1533, and the control end is connected to the third input end of the retiming circuit 153; the first end of the eighth transistor T8 is connected to the second end of the seventh transistor T7, and the control end is connected to the second input end of the retiming circuit 153; the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, the second end is connected to the ground end GND, and the control end is connected to the control end of the sixth transistor T6. In this embodiment, the sixth transistor T6 and the seventh transistor T7 are, for example, P-type transistors, and the eighth transistor T8 and the ninth transistor T9 are, for example, N-type transistors.

[0052] The fourth unit 1534 includes a tenth transistor T10 and an eleventh transistor T11 connected in series, and the fourth unit 1534 can also be called an output unit of the re-timing circuit 153. The first end of the tenth transistor T10 is connected to the power supply voltage VCC, the second end is connected to the output end of the re-timing circuit 153, and the control end is connected to the output end of the third unit 1533; the first end of the eleventh transistor T11 is connected to the second end of the tenth transistor T10, the second end is connected to the ground end GND, and the control end is connected to the control end of the tenth transistor T10. In this embodiment, the tenth transistor T10 is, for example, a P-type transistor, and the eleventh transistor T11 is, for example, an N-type transistor.

[0053] The fifth unit 1535 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a fifteenth transistor T15 connected in series, and the fifth unit 1535 can also be called a latch unit of the re-timing circuit 153. The first end of the twelfth transistor T12 is connected to the power supply voltage VCC, and the control end is connected to the output end of the re-timing circuit 153; the first end of the thirteenth transistor T13 is connected to the second end of the twelfth transistor T12, the second end is connected to the output end of the third unit 1533, and the control end is connected to the first input end of the re-timing circuit 153; the first end of the fourteenth transistor T14 is connected to the die segment of the thirteenth transistor T13, and the control end is connected to the third input end of the re-timing circuit 153; the first end of the fifteenth transistor T15 is connected to the second end of the fourteenth transistor T14, the second end is connected to the ground end GND, and the control end is connected to the control end of the twelfth transistor T12. In this embodiment, the twelfth transistor T12 and the thirteenth transistor T13 are, for example, P-type transistors, and the fourteenth transistor T14 and the fifteenth transistor T15 are, for example, N-type transistors.

[0054] Furthermore, in the actual use of the re-timing circuit 153 of the first embodiment of the present application, a waveform diagram of one cycle can be divided into four stages and three modes, and the three modes are, for example, a trigger mode M1 (DFF mode), a latch module M2 (Latch mode) and a direct mode M3 (direct Mode). Figure 6 , in order to Figure 6 About the marking of time and Figure 4 The time mark in corresponds to Figure 6 The multiple time marks in the time sequence in a cycle should be t1, t5, t2, t3, and t4, respectively. According to the fact that the P-type transistor is turned on when the voltage at the control end is at a low level, and the N-type transistor is turned on when the voltage at the control end is at a high level, the working stages of the retiming circuit 153 include the following parts.

[0055] Before time t1, the first modulus signal m0 received by the first input terminal D of the retiming circuit 153 is at a low level, the clock signal CKIN received by the second input terminal is also at a low level, and the reference signal Falling received by the third input terminal is at a high level, so that before time t1, the first transistor T1 and the fourth transistor T4 are turned on; and since the first transistor T1 is turned on, the output terminal voltage of the first unit 1531 is at a high level; the third transistor T3 in the second unit 1532 is turned off, and the fifth transistor T5 is turned on, so that the output terminal of the second unit 1532 is at a low level; the sixth transistor T6 of the third unit 1533 is turned on, and the seventh transistor T7 is turned off, and the output terminal of the third unit 1533 is in a floating state (floating), which means that the port is not connected to any power supply or ground, so its voltage can float freely, and its level state is determined by the previous state, which is a high level; the eleventh transistor T11 in the fourth unit 1534 is turned on, and the output terminal of the fourth unit 1534 remains at a low level.

[0056] Then at time t1, since the input signal (first modulus signal m0) enters the retiming circuit 153, the first modulus signal m0 received at its first input terminal D changes from a low level to a high level. At this time, the second transistor T2 in the first unit 1531 is turned on, and the output terminal of the first unit 1531 becomes a low level; the third transistor T3 and the fourth transistor T4 in the second unit 1532 are turned on, and the output terminal of the second unit 1532 is a high level; the ninth transistor T9 in the third unit 1533 is turned on, but the eighth transistor T8 is turned off, so the output terminal of the third unit 1533 is in a floating state, maintaining the level of the previous state, which is a high level; the eleventh transistor T11 in the fourth unit 1534 is turned on, and the output terminal of the fourth unit 1534 maintains a low level.

[0057] After t1 and before t5, the first modulus signal m0 received by the first input terminal D of the re-timing circuit 153 is at a high level, and when the clock signal CKIN received by the second input terminal changes from a low level to a high level, the clock signal CKIN samples the first modulus signal m0, and the reference signal Falling received by the third input terminal is at a high level. Figure 5In the circuit shown, the second transistor T2 and the eighth transistor T8 are turned on first, and then the second transistor T2 is turned on so that the output terminal voltage of the first unit 1531 is the second terminal voltage GND of the second transistor T2, which is a low level; thus, the control terminal of the third transistor T3 in the second unit 1532 is a low level, the third transistor T3 is turned on, and the fourth transistor T4 is turned off in the first half of the clock signal CKIN cycle. At this time, the output terminal of the second unit 1532 is a floating state, maintaining the previous state, which is a high level. When the clock signal CKIN becomes a low level in the second half of the clock signal CKIN cycle, the fourth transistor T4 is also turned on. At this time, the output terminal voltage of the second unit 1532 is The voltage VCC at the first end of the third transistor T3 is high level; then in the third unit 1533, in the first half of the clock signal CKIN cycle, the eighth transistor T8 is turned on and the ninth transistor T9 is turned on, and the output end of the third unit 1533 is low level, and in the second half of the clock signal CKIN cycle, the eighth transistor T8 is turned off, and the output end of the third unit 1533 is floating state, and its level state is determined by the previous state, which is low level; then the control end of the tenth transistor T10 in the fourth unit 1534 is low voltage, the tenth transistor T10 is turned on, and the signal output by the output end of the re-timing circuit 153 is the first end voltage VCC of the tenth transistor T10, which is high level. And in the trigger mode M1 of the first stage t1-t5, the signal output by the output end of the re-timing circuit 153 has been kept at a high level since the first modulus signal m0 becomes high level. At the same time, in the fifth unit 1535 , the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and the output terminal level of the fifth unit 1535 is the same as the output terminal level of the third unit 1533 , which is a low level.

[0058] At time t5, the first modulus signal m0 received by the first input terminal D of the re-timing circuit 153 has changed from high level to low level, the clock signal CKIN received by the second input terminal has changed from low level to high level, the reference signal Falling received by the third input terminal is high level, and in the latch mode M2 ​​of the second stage from t5 to t2, the reference signal Falling of the re-timing circuit 153 is high level, and the first modulus signal m0 is low level. Figure 5In the circuit shown, the first transistor T1 is first turned on, so that the output voltage of the first unit 1531 becomes a high level; thus, in the second unit, the fifth transistor T5 is turned on, so that the output voltage of the second unit 1532 becomes a low level; then in the third unit, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, and the output voltage of the third unit 1533 is floating, and its level remains in the previous state, which is a low level; then the tenth transistor T10 in the fourth unit 1534 is turned on, and the output of the fourth unit 1534 (the output of the retiming circuit 153) remains at a high level. In addition, in the fifth unit 1535, the fifteenth transistor T15 is turned on under the control of the output signal (high level) of the fourth unit 1534, and the fourteenth transistor T14 is turned on under the control of the reference signal Falling, so that the output terminal voltage of the fifth unit 1535 is the second terminal voltage GND of the fifteenth transistor T15, which is a low level and is consistent with the output terminal level of the third unit 1535, so that in the fourth unit 1534, the control terminal of the tenth transistor T10 remains at a low level, the tenth transistor T10 remains turned on, and the signal output by the output terminal of the retiming circuit 153 remains at a high level.

[0059] At time t2, the first modulus signal m0 received by the first input terminal D of the re-timing circuit 153 is at a low level, the clock signal CKIN received by the second input terminal changes from a low level to a high level, and the reference signal Falling received by the third input terminal F changes from a high level to a low level, and in the direct mode M3 of the third stage from t2 to t3, the first modulus signal m0 and the reference signal Falling of the re-timing circuit 153 are both at a low level. Figure 5 In the circuit shown, the first transistor T1 and the seventh transistor T7 are turned on first, and then the first transistor T1 is turned on so that the output terminal voltage of the first unit 1531 is high level; thus, the fifth transistor T5 in the second unit 1532 is turned on, and the output terminal voltage of the second unit 1532 is low level; then, in the third unit 1533, the sixth transistor T6 and the seventh transistor T7 are turned on, and the output terminal voltage of the third unit 1533 changes from low level to high level; then, the eleventh transistor T11 in the fourth unit 1534 is turned on, and the output terminal voltage of the fourth unit 1534 changes from high level to low level; at this time, in the fifth unit 1535, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, so that the output terminal voltage of the fifth unit 1535 changes from low level to high level, which is consistent with the output terminal voltage of the third unit 1535, and the output terminal voltage of the retiming circuit 153 remains at a low level.

[0060] At time t3, the first modulus signal m0 received by the first input terminal D of the re-timing circuit 153 is at a low level, the clock signal CKIN received by the second input terminal changes from a low level to a high level, and the reference signal Falling received by the third input terminal changes from a low level to a high level, and in the latch mode M2 ​​of the fourth stage from t3 to t4, the reference signal Falling of the re-timing circuit 153 is at a high level, and the first modulus signal m0 is at a low level. Figure 5 In the circuit shown, the first transistor T1 is first turned on, so that the output voltage of the first unit 1531 is high level; thus, in the second unit 1532, the fifth transistor T5 is turned on, so that the output voltage of the second unit 1532 is low level; then in the third unit 1533, the sixth transistor T6 is turned on, but because the control end of the seventh transistor T7 is connected to the reference signal Falling at a high level, the seventh transistor T7 is turned off, and the output of the third unit 1533 is floating state, and its voltage remains in the previous state, which is high level; then in the fourth unit 1534, the eleventh transistor T11 is turned on, and the output voltage of the fourth unit 1534 is low level. At the same time, in the fifth unit 1535, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the output voltage of the fifth unit 1535 is high level, which is consistent with the output voltage of the third unit 1533, and the output signal of the output of the re-timing circuit 153 remains low level.

[0061] Further, at time t4, the first modulus signal m0 received by the first input terminal D of the re-timing circuit 153 may have two states, one is a low level and the other is a high level.

[0062] When the first modulus signal m0 at time t4 is at a low level, the reference signal Falling received at the second input terminal is at a high level, and the clock signal CKIN received at the second input terminal changes from a low level to a high level. The states of the transistors of the first unit 1531 to the fifth unit 1535 in the retiming circuit 153 can refer to the relevant description at the aforementioned time t5.

[0063] When the first modulus signal m0 at time t4 is high, the reference signal Falling received at the second input terminal is high, and the clock signal CKIN received at the second input terminal changes from low to high. The states of the transistors of the first unit 1531 to the fifth unit 1535 in the retiming circuit 153 can refer to the relevant description at the aforementioned time t1.

[0064] In addition, from time t1 to time t4, the output signal completes one cycle of output, and time t4 can be regarded as both the end of the previous cycle and the beginning of the next cycle.

[0065] In this embodiment, since the rising edge and falling edge of the output signal are defined by the level states of the first modulus signal m0 and the reference signal Falling being sampled by the clock signal CKIN. Therefore, the rising edge of the output signal is the first rising edge of the clock signal CKIN after the first modulus signal m0 becomes a high level, that is, the rising edge of the first modulus signal m0 may be earlier than the rising edge of the output signal, as described above; similarly, the falling edge of the output signal is the first rising edge of the clock signal CKIN after the reference signal Falling becomes a low level, that is, the falling edge of the reference signal Falling may be earlier than the falling edge of the output signal. In another embodiment, if the rising edge of the first modulus signal m0 and the falling edge of the reference signal Falling are both simultaneous with the rising edge of the clock signal CKIN, the rising edge and falling edge of the output signal are simultaneous with the rising edge of the first modulus signal m0 and the falling edge of the reference signal Falling.

[0066] When the output of the third unit 1533 is in a floating state, its voltage is easily affected by various factors, which may cause the output voltage of the fourth unit 1534 to change. However, due to the existence of the fifth unit 1535, it is in a mutually locked state with the fourth unit 1534, so that the voltage of the input of the fourth unit 1534 can always maintain a clear state and will not change due to the voltage change of the output of the third unit 1533, thereby improving the yield of the retiming circuit 153.

[0067] Further, Figure 7 FIG. 2 is a schematic diagram showing the structure of a re-timing circuit according to a second embodiment of the present invention. Compared with the first embodiment, the re-timing circuit of the second embodiment does not have the fifth unit 1535 .

[0068] refer to Figure 7 In the re-timing circuit of the second embodiment, a first unit 1531, a second unit 1532, a third unit 1533 and a fourth unit 1534 are sequentially cascaded.

[0069] The first unit 1531 includes a first transistor T1 and a second transistor T2 connected in series. The second unit 1532 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5 connected in series. The third unit 1533 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9 connected in series. The fourth unit 1534 includes a tenth transistor T10 and an eleventh transistor T11 connected in series. In this embodiment, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7 and the tenth transistor T10 are, for example, P-type transistors, and the second transistor T2, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are, for example, N-type transistors.

[0070] In the retiming circuit 153 of the second embodiment, the function of adjusting the duty cycle of the output signal can still be realized, but compared with the first embodiment, since there is no fifth unit 1535, the retiming circuit 153 does not have a latching mode, and thus leakage current may exist during circuit operation.

[0071] Figure 8 FIG. 2 is a schematic diagram showing the structure of a re-timing circuit according to a third embodiment of the present invention. Compared with the first embodiment, the structure of the re-timing circuit of the third embodiment is simpler.

[0072] refer to Figure 7 In the re-timing circuit of the second embodiment, a second unit 1532 and a third unit 1533 are cascaded in sequence. The second unit 1532 generates an intermediate signal according to the clock signal CKIN and the first modulus signal m0; the third unit 1533 generates a second output signal Qb according to the intermediate signal, the reference signal Falling and the clock signal CKIN, and the inverse signal of the second output signal Qb is the target output signal CKOUT.

[0073] The modulus signal and the reference signal have the same frequency, the rising edge of the modulus signal determines the rising edge of the output signal, and the falling edge of the reference signal determines the falling edge of the output signal.

[0074] The second unit 1532 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5 connected in series. The first end of the third transistor T3 is connected to the power supply voltage VCC, and the control end is connected to the input end of the second unit 1532, wherein the input end of the second unit 1532 receives the reverse signal of the first modulus signal m0, where the reverse means that the high level state is opposite to the low level state; the first end of the fourth transistor T4 is connected to the second end of the third transistor T3, the second end is connected to the output end of the second unit 1532, and the control end is connected to the second input end of the retiming circuit 153; the first end of the fifth transistor T5 is connected to the second end of the fourth transistor T4, the second end is connected to the ground end GND, and the control end is connected to the control end of the third transistor T3. In this embodiment, the third transistor T3 and the fourth transistor T4 are, for example, P-type transistors, and the fifth transistor T5 is, for example, an N-type transistor.

[0075] The third unit 1533 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9 connected in series. The first end of the sixth transistor T6 is connected to the power supply voltage VCC, and the control end is connected to the output end of the second unit 1532; the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, the second end is connected to the output end of the third unit 1533, and the control end is connected to the third input end of the retiming circuit 153, wherein the output signal of the third unit 1533 is a signal reverse to the output signal in the first embodiment and the second embodiment; the first end of the eighth transistor T8 is connected to the second end of the seventh transistor T7, and the control end is connected to the second input end of the retiming circuit 153; the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, the second end is connected to the ground end GND, and the control end is connected to the control end of the sixth transistor T6. In this embodiment, the sixth transistor T6 and the seventh transistor T7 are, for example, P-type transistors, and the eighth transistor T8 and the ninth transistor T9 are, for example, N-type transistors.

[0076] In this embodiment, if one wants to obtain the same output signal as that in the first and second embodiments, it is necessary to add an inverter at the output end of the retiming circuit 153 so that the phase and duty cycle of the signal output by the retiming circuit 153 of the third embodiment are the same as those of the signal output by the retiming circuit 153 of the first and second embodiments.

[0077] The retiming circuit, multi-mode frequency divider and electronic device provided by the present invention divide the input oscillation signal through the multi-mode frequency division circuit to obtain multiple divided frequency signals, and the logic circuit generates a reference signal by performing logic operations on some of the divided frequency signals. The rising edge of the output signal of the retiming circuit is triggered according to the modulus signal output by any frequency division module in the multi-mode frequency divider, and the falling edge of the output signal of the retiming circuit is triggered according to the falling edge of the reference signal. By using different signals to redefine the rising edge and falling edge of the output signal, the retiming circuit of the present application can avoid the noise generated by the logic gates in a large number of frequency division circuits, achieve low phase noise, and can better define the duty cycle of the output signal of the retiming circuit to achieve efficient and accurate operation of the electronic device.

[0078] Furthermore, in actual applications, the retiming circuit, multi-mode divider and electronic device of the present application has three stages. In the first stage, the modulus signal is triggered by the input clock signal, so that the output signal of the retiming circuit is high level; in the second stage, the level of the output signal is locked at the output value to avoid changes in the output value due to leakage; in the third stage, the falling edge of the reference signal is triggered to make the output signal become low level, so that it will not be triggered by the clock signal. Therefore, the retiming circuit of the present application can well define the duty cycle of the output signal.

[0079] Furthermore, in the re-timing circuit, multi-mode frequency divider and electronic device of the present application, the re-timing circuit is implemented by using multiple transistors, so that the design of the circuit is simple and easy to implement, and has lower current and smaller area.

[0080] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A re-timing circuit, connected to a multi-mode frequency division circuit and a logic circuit, to receive a modulus signal with a target frequency provided by the multi-mode frequency division circuit and a reference signal provided by the logic circuit, characterized in that: include: A second unit, comprising a plurality of transistors connected in series, generating an intermediate signal according to a clock signal and the modulus signal; The third unit includes a plurality of transistors connected in series, and generates a second output signal according to the intermediate signal, the reference signal and the clock signal, wherein the inverse signal of the second output signal is the target output signal. The modulus signal and the reference signal have the same frequency, the rising edge of the modulus signal determines the rising edge of the output signal, and the falling edge of the reference signal determines the falling edge of the output signal.

2. The re-timing circuit according to claim 1, characterized in that The second unit comprises: a third transistor, wherein a first terminal of the third transistor is connected to a power supply voltage, and a control terminal of the third transistor is connected to an input terminal of the second unit; a fourth transistor, wherein a first end of the fourth transistor is connected to the second end of the third transistor, a second end of the fourth transistor is connected to the output end of the second unit, and a control end thereof receives the clock signal; A fifth transistor, wherein a first end of the fifth transistor is connected to the second end of the fourth transistor, a second end of the fifth transistor is connected to the ground end, and a control end of the fifth transistor is connected to the control end of the third transistor.

3. The re-timing circuit according to claim 2, characterized in that: The third unit comprises: a sixth transistor, wherein a first terminal of the sixth transistor is connected to a power supply voltage, and a control terminal of the sixth transistor is connected to an output terminal of the second unit; a seventh transistor, wherein a first end of the seventh transistor is connected to the second end of the sixth transistor, a second end of the seventh transistor is connected to the output end of the third unit, and a control end thereof receives the reference signal; an eighth transistor, a first end of the eighth transistor being connected to the second end of the seventh transistor, and a control end thereof receiving the clock signal; A ninth transistor, wherein a first end of the ninth transistor is connected to the second end of the eighth transistor, a second end of the ninth transistor is connected to the ground end, and a control end of the ninth transistor is connected to the control end of the sixth transistor.

4. The re-timing circuit according to claim 2, characterized in that: An input terminal of the second unit receives an inverted signal of the modulus signal.

5. The re-timing circuit according to claim 3, characterized in that: Also includes: A first unit includes a plurality of transistors connected in series, wherein an output terminal of the first unit is connected to an input terminal of the second unit; a fourth unit, comprising a plurality of transistors connected in series, wherein an input terminal of the fourth unit is connected to an output terminal of the third unit, The input end of the first unit receives the modulus signal, and the output end of the fourth unit outputs the output signal.

6. The re-timing circuit according to claim 5, characterized in that The first unit comprises: a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage, a second terminal of the first transistor is connected to an output terminal of the first unit, and a control terminal of the first transistor is connected to an input terminal of the first unit; A second transistor, wherein a first end of the second transistor is connected to the second end of the first transistor, a second end of the second transistor is connected to the ground end, and a control end of the second transistor is connected to the control end of the first transistor.

7. The re-timing circuit according to claim 6, characterized in that: The fourth unit comprises: a tenth transistor, wherein a first terminal of the tenth transistor is connected to a power supply voltage, a second terminal of the tenth transistor is connected to an output terminal of the fourth unit, and a control terminal of the tenth transistor is connected to an output terminal of the third unit; An eleventh transistor, wherein a first end of the eleventh transistor is connected to the second end of the tenth transistor, a second end of the eleventh transistor is connected to the ground end, and a control end of the eleventh transistor is connected to the control end of the tenth transistor.

8. The re-timing circuit according to claim 5, characterized in that: Also includes: The fifth unit includes a plurality of transistors connected in series, the input end of the fifth unit is connected to the output end of the fourth unit, and the output end is connected to the input end of the fourth unit to latch the level of the output signal.

9. The re-timing circuit according to claim 8, characterized in that: The fifth unit comprises: a twelfth transistor, wherein a first terminal of the twelfth transistor is connected to a power supply voltage, and a control terminal of the twelfth transistor is connected to an output terminal of the fourth unit; a thirteenth transistor, wherein a first end of the thirteenth transistor is connected to the second end of the twelfth transistor, a second end of the thirteenth transistor is connected to the input end of the fourth unit, and a control end receives the reference signal; a fourteenth transistor, a first end of the fourteenth transistor being connected to the second end of the thirteenth transistor, and a control end thereof receiving the modulus signal; A fifteenth transistor, wherein a first end of the fifteenth transistor is connected to the second end of the fourteenth transistor, a second end of the fifteenth transistor is connected to the ground end, and a control end of the fifteenth transistor is connected to the control end of the twelfth transistor.

10. The re-timing circuit according to claim 7 or 9, characterized in that: The first transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor and the tenth transistor are P-type transistors, and the second transistor, the fifth transistor, the eighth transistor, the ninth transistor and the eleventh transistor are N-type transistors; or The twelfth transistor and the thirteenth transistor are P-type transistors, and the fourteenth transistor and the fifteenth transistor are N-type transistors.

11. A multi-mode frequency divider, characterized in that: include: A multi-mode frequency division circuit, comprising a plurality of cascaded frequency division modules, generating a plurality of frequency division signals with different frequencies and lower than the frequency of the clock signal, and at least one modulus signal according to a clock signal; a logic circuit connected to at least two frequency division modules of the plurality of cascaded frequency division modules to generate a reference signal according to the at least two frequency division signals; The retiming circuit is connected to the multi-mode frequency division circuit and the logic circuit, and generates an output signal with a target frequency and a target duty cycle according to the clock signal, the modulus signal and the reference signal.

12. The multi-mode frequency divider according to claim 11, characterized in that: The logic circuit includes an OR logic gate, and the OR logic gate performs an OR logic operation on the at least two frequency-divided signals to generate the reference signal.

13. An electronic device, characterized in that: It comprises the multi-mode frequency divider as claimed in any one of claims 11 to 12.

Images