Clock synchronization method and system based on FPGA

Abstract

The invention discloses a clock synchronization method and system based on an FPGA, and the method comprises the steps: obtaining the frequency of a synchronization signal and the period of a local clock signal, carrying out the first frequency division processing of the local clock signal through the first internal logic of the FPGA, and obtaining a first clock signal; calculating a phase difference and a frequency difference between the first clock signal and the synchronizing signal through a second internal logic of the FPGA; and according to the frequency difference and the phase difference, synchronous locking of the local clock signal and the synchronous signal is realized through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output, so that the cost of clock synchronization is reduced. Wherein the clock synchronization is realized by only depending on FPGA soft logic in a pure digital mode, and does not depend on an additional analog circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a clock synchronization method and system based on FPGA. Background Art

[0002] With the development of science and technology, clock synchronization processing has become a hard indicator for processing equipment. Existing processing equipment needs to use low-frequency time-stamp pulses (such as PPS1Hz pulses, 300Hz video synchronization pulses), time values ​​(such as 1588v2 nanosecond precision timestamps) or external synchronization signals such as the average rate on the data interface to synthesize a stable, relatively high-frequency reference clock (such as 10MHz) to control the operation of time-sensitive logic in the system. For example, the air interface frequency of 4G / 5G base stations relies on the synchronous Ethernet IEEE 1588v2 time synchronization protocol interconnected between base stations or the PPS signal output by GPS during mutual synchronization; and the Ao IP solution also relies on the two methods mentioned above to complete the synchronization of the sampling clocks of the ADC and DAC in the system to ensure that the system runs in unison.

[0003] In the prior art, in order to synchronize the local reference clock with the synchronization signal sent by the synchronization source, external analog PLL devices or tamed clock chips are generally used to achieve synchronization. However, the method of synthesizing the reference clock from the synchronization signal using an analog PLL device requires the loop filter to have a large time constant, which results in a slow PLL locking speed, and the frequency is too low and is easily disturbed and loses synchronization. At the same time, the PLL resources integrated in the FPGA are usually not equipped with a loop filter with a large time constant, resulting in the PLL resources integrated in the FPGA being unable to be directly applied to the clock recovery conditions of low-frequency time-stamp pulse input or timestamp input.

[0004] The method of synthesizing a reference clock from a synchronization signal using a tamed clock requires different synchronization processes based on the different local reference frequency sources used. When a fixed local reference frequency source is used, the tamed clock relies on devices such as a DSM-based fractional-N PLL or DDS to synthesize a variable clock, and the output reference clock has a relatively high output spurious value compared to an integer PLL. In addition, a high-speed DAC is required by DDS to convert digital codes into continuous analog voltage amplitudes, which results in a relatively high cost. When a variable local reference frequency source is used, the variable local reference frequency source has a narrow adjustable frequency range and cannot achieve a wide locking range. In addition, the variable local reference frequency source has a high cost, resulting in greater cost pressure. Summary of the invention

[0005] In order to solve the above technical problems, the present invention discloses a clock synchronization method and system based on FPGA, which are used to reduce the cost of clock synchronization.

[0006] In order to achieve the above object, the present invention discloses a clock synchronization method based on FPGA, comprising:

[0007] Acquire the frequency of the synchronization signal and the period of the local clock signal, and perform a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal;

[0008] Calculating a phase difference and a frequency difference between the first clock signal and the synchronization signal through a second internal logic of the FPGA;

[0009] According to the frequency difference and the phase difference, the local clock signal and the synchronization signal are synchronously locked through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output.

[0010] The FPGA-based clock synchronization method disclosed in the present invention can achieve the synchronization of the local clock signal according to the external input synchronization signal by only using the internal logic of the FPGA. Among them, the first internal logic in the FPGA is used to divide the frequency of the local clock signal so that the divided clock signal and the synchronization signal are synchronized and locked. Furthermore, the second internal logic in the FPGA is used to calculate the phase difference and frequency difference between the divided first clock signal and the synchronization signal, so as to complete the synchronization lock of the local clock signal and the synchronization signal according to the phase difference and frequency difference. In the present invention, the internal resources of the FPGA are used to track the external input synchronization signal in real time, and then the local clock signal is divided to complete the clock synchronization. The clock signal synchronization processing can be achieved without the need for an external PLL or a tamed clock chip, thereby reducing the cost of clock synchronization.

[0011] As a preferred example, the acquiring the frequency of the synchronization signal and the period of the local clock signal includes:

[0012] Acquire a synchronization signal input by a synchronization signal source and a local clock signal input by a local reference frequency source, and calculate a first frequency of the synchronization signal and a second frequency of the local clock signal;

[0013] Comparing the first frequency with a preset frequency range or comparing the synchronization signal with a preset code pattern, so as to determine whether the synchronization signal is a valid signal according to the comparison result;

[0014] When the synchronization signal is determined to be a valid signal, a frequency coarse adjustment value is calculated according to the first frequency and the second frequency, and a period of the local clock signal is calculated according to the second frequency.

[0015] The present invention determines the validity of the input synchronization signal according to the frequency of the synchronization signal, so as to avoid useless clock synchronization processing in the later stage, reduce the waste of resources on the FPGA, and realize the fail-safe function, that is, when the external synchronization signal is lost or invalid, the system can run freely without causing the other circuits to lose the clock. After monitoring the effective synchronization signal, the frequency of the synchronization signal is used to calculate the frequency coarse adjustment value, so that the first clock signal that is subsequently initialized and synthesized according to the frequency coarse adjustment value is close to the frequency required by the input synchronization signal, without slowly increasing the frequency until it is locked, and the rate of clock synchronization can be improved.

[0016] As a preferred example, performing a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal includes:

[0017] Accumulating and calculating the frequency coarse adjustment value in real time according to the cycle to obtain a first phase corresponding to each cycle;

[0018] According to the first phase and a preset phase threshold, the state of the clock register in the FPGA is adjusted in real time to output the first clock signal through the clock register.

[0019] The present invention utilizes the period of the local clock signal and the frequency coarse adjustment value to initialize the synthetic clock signal, so that the synthetic clock signal fits the frequency of the synchronization signal, improves the locking rate, and simultaneously saves the phase change according to the clock register to realize the frequency division of the local clock.

[0020] As a preferred example, adjusting the state of the clock register in the FPGA in real time according to the first phase and the preset phase threshold includes:

[0021] Compare the first phase with a preset first phase threshold, and when the first phase is greater than the first phase threshold, generate a first pulse signal to control the clock register to be reset;

[0022] Compare the first phase with a preset second phase threshold, and when the first phase is greater than the second phase threshold, calculate a first phase difference between the first phase and the second phase threshold and generate a trigger signal of a DTC circuit in the FPGA;

[0023] The delay line selection length in the DTC circuit is calculated according to the first phase difference value, so as to output a second pulse signal through the DTC circuit to control the clock register to be set according to the delay line selection length and the trigger signal.

[0024] The present invention utilizes the phase and the phase threshold to trigger the clock register to change its state, thereby completing the frequency division of the local clock signal.

[0025] As a preferred example, the step of outputting the second pulse signal through the DTC circuit to control the clock register to be set includes:

[0026] Decoding the delay line selection length into a one-hot code by a decoder in the DTC circuit;

[0027] The one-hot code is stored in the DTC data register in the DTC circuit to control the delay line connected to the DTC data register to carry according to the one-hot code so as to output the second pulse signal; wherein the delay line includes a carry chain composed of a plurality of lookup tables connected in series; each of the lookup tables is connected to a corresponding DTC data register.

[0028] When triggering the setting process of the register, the present invention utilizes a carry chain delay line composed of a carry chain formed by serially connecting lookup tables in an FPGA to rely on a DTC data register in the DTC circuit to achieve phase segmentation, thereby improving the resolution of the output clock and the accuracy of clock synchronization.

[0029] As a preferred example, the calculating the phase difference and frequency difference between the first clock signal and the synchronization signal by the second internal logic of the FPGA includes:

[0030] The phase difference between the first clock signal and the synchronization signal is measured by the PFD circuit of the FPGA; wherein the PFD circuit includes a first delay line and a sampling circuit composed of a plurality of D flip-flops for sampling the output of the first delay line; the first delay line includes a carry chain composed of a plurality of lookup tables connected in series;

[0031] According to the phase difference, a first frequency fine adjustment value corresponding to the first clock signal is calculated by a proportional integral method.

[0032] The present invention uses a first delay line formed by a carry chain composed of a series of lookup tables in an FPGA and a sampling circuit that uses a D flip-flop to sample the output of the delay line to construct the PFD circuit. The phase difference can be measured more accurately through the delay time of the delay line carry chain, which is convenient for reducing output jitter and improving the stability of clock synchronization. Furthermore, the first frequency fine adjustment value is calculated using a proportional integral method to further fine-tune the frequency of the first clock signal and improve the accuracy of clock differences.

[0033] As a preferred example, the method of realizing synchronization locking between the local clock signal and the synchronization signal through the first internal logic and the second internal logic of the FPGA, and outputting the synchronized clock signal, includes:

[0034] Acquire a first rising edge time of the first clock signal and a second rising edge time of the synchronization signal;

[0035] Calculate a first time threshold and a second time threshold according to the second rising edge time and the delay time of the delay chain in the PFD circuit;

[0036] Comparing the first rising edge time with the first time threshold and the second time threshold;

[0037] When the first rising edge time is greater than or equal to the first time threshold and less than or equal to the second time threshold, it is determined that the first clock signal and the synchronization signal are locked, and the first clock signal is output as a synchronized clock signal.

[0038] The present invention uses the single-stage delay time of the carry chain and the rising edge time of the synchronization signal and the first clock signal to perform signal locking judgment. Among them, taking the single-stage delay time of the carry chain as a reference can reduce the occupation of FPGA global clock resources and improve the efficiency of clock synchronization processing.

[0039] As a preferred example, the output synchronized clock signal includes:

[0040] When the first rising edge time is less than the first time threshold or the first rising edge time is greater than the second time threshold, adjusting the first frequency fine adjustment value to generate a second frequency fine adjustment value;

[0041] Calculating the sum of the second frequency fine adjustment value and the frequency coarse adjustment value, so as to perform cyclic frequency division processing on the local clock signal according to the sum of the second frequency fine adjustment value and the frequency coarse adjustment value and the period of the local clock signal through the first internal logic of the FPGA;

[0042] When the rising edge time of the clock signal after the frequency division processing is greater than or equal to the first time threshold and less than or equal to the second time threshold, it is determined that the clock signal after the frequency division processing is locked with the synchronization signal, and the clock signal after the frequency division processing is output as a synchronized clock signal.

[0043] The present invention utilizes the sum of the frequency fine adjustment value and the frequency coarse adjustment value to perform synchronization locking of the synchronization signal and the first clock signal, which can effectively reduce the number of times the local clock signal is divided, thereby improving the efficiency of clock synchronization.

[0044] On the other hand, the present invention discloses a clock synchronization system based on FPGA, including a main control module, an FPGA processing module, a synchronization signal source and a local reference frequency source;

[0045] The main control module and the FPGA processing module are connected to the synchronization signal source signal, and are used to receive the synchronization signal sent by the synchronization signal source for synchronizing the clock signal;

[0046] The main control module and the FPGA processing module are connected to the local reference frequency source signal to receive the local clock signal sent by the local reference frequency source;

[0047] The main control module is connected to the FPGA processing module by signal, and is used to obtain the frequency of the synchronization signal and the period of the local clock signal, and send the frequency and the period to the FPGA processing module, so that the FPGA processing module performs the following operations:

[0048] Performing a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal;

[0049] Calculating a phase difference and a frequency difference between the first clock signal and the synchronization signal through a second internal logic of the FPGA;

[0050] According to the frequency difference and the phase difference, the local clock signal and the synchronization signal are synchronously locked through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output.

[0051] The FPGA-based clock synchronization system disclosed in the present invention can achieve synchronization of the local clock signal according to the external input synchronization signal by only using the internal logic of the FPGA. Among them, the first internal logic in the FPGA is used to divide the frequency of the local clock signal so that the divided clock signal and the synchronization signal are synchronized and locked. Furthermore, the second internal logic in the FPGA is used to calculate the phase difference and frequency difference between the divided first clock signal and the synchronization signal, so as to complete the synchronization lock of the local clock signal and the synchronization signal according to the phase difference and frequency difference. In the present invention, the internal resources of the FPGA are used to track the external input synchronization signal in real time, and then the local clock signal is divided to complete the clock synchronization. The clock signal synchronization processing can be achieved without the need for an external PLL or a tamed clock chip, thereby reducing the cost of clock synchronization.

[0052] As a preferred example, the main control module includes an information extraction unit, a signal detection unit and a calculation unit;

[0053] The information extraction unit is used to calculate the first frequency of the synchronization signal and the second frequency of the local clock signal;

[0054] The signal detection unit is used to compare the first frequency with a preset frequency range or compare the synchronization signal with a preset code pattern, so as to determine whether the synchronization signal is a valid signal according to the comparison result;

[0055] The calculation unit is used to calculate a frequency coarse adjustment value according to the first frequency and the second frequency and calculate a period of the local clock signal according to the second frequency when the synchronization signal is determined to be a valid signal.

[0056] The present invention determines the validity of the input synchronization signal according to the frequency of the synchronization signal, so as to avoid useless clock synchronization processing in the later stage and reduce the waste of FPGA resources. After monitoring the effective synchronization signal, the frequency of the synchronization signal is used to calculate the frequency coarse adjustment value, so that the first clock signal that is subsequently initialized and synthesized according to the frequency coarse adjustment value is close to the frequency required by the input synchronization signal, without slowly increasing the frequency until it is locked, and the rate of clock synchronization can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 : A schematic diagram of a flow chart of a clock synchronization method based on FPGA disclosed in an embodiment of the present invention;

[0058] Figure 2 : A schematic diagram of a flow chart of a clock synchronization system based on FPGA disclosed in an embodiment of the present invention;

[0059] Figure 3 : A schematic diagram of the structure of a digital phase-locked loop based on FPGA disclosed in another embodiment of the present invention;

[0060] Figure 4 : A schematic diagram of a structure for clock synchronization of a digital phase-locked loop based on FPGA disclosed in another embodiment of the present invention;

[0061] Figure 5 : A schematic diagram of initializing a DTC-NCO module disclosed in yet another embodiment of the present invention;

[0062] Figure 6 : A schematic diagram of the structure of an NCO module based on a DTC circuit disclosed in yet another embodiment of the present invention;

[0063] Figure 7 : A schematic diagram of a PFD circuit based on FPGA disclosed in another embodiment of the present invention;

[0064] Figure 8 : is a structural schematic diagram of another FPGA-based PFD circuit disclosed in yet another embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] Embodiment 1

[0067] This embodiment discloses a clock synchronization method based on FPGA. For the specific implementation process of the clock synchronization method, please refer to Figure 1 , mainly including step 101 to step 103, the steps are:

[0068] Step 101: Acquire the frequency of the synchronization signal and the period of the local clock signal, and perform a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal.

[0069] In this embodiment, this step mainly includes: first, obtaining a synchronization signal input by a synchronization signal source and a local clock signal input by a local reference frequency source, and calculating a first frequency of the synchronization signal and a second frequency of the local clock signal; comparing the first frequency with a preset frequency range or comparing the synchronization signal with a preset code type to determine whether the synchronization signal is a valid signal based on the comparison result; when the synchronization signal is determined to be a valid signal, calculating a frequency coarse adjustment value based on the first frequency and the second frequency and calculating a period of the local clock signal based on the second frequency.

[0070] Secondly, the frequency coarse adjustment value is accumulated and calculated in real time according to the cycle to obtain the first phase corresponding to each cycle; according to the first phase and the preset phase threshold, the state of the clock register in the FPGA is adjusted in real time to output the first clock signal through the clock register.

[0071] Furthermore, the first phase is compared with a preset first phase threshold, and when the first phase is greater than the first phase threshold, a first pulse signal is generated to control the clock register to be reset; the first phase is compared with a preset second phase threshold, and when the first phase is greater than the second phase threshold, a first phase difference between the first phase and the second phase threshold is calculated and a trigger signal of the DTC circuit in the FPGA is generated; the delay line selection length in the DTC circuit is calculated according to the first phase difference, so as to output a second pulse signal through the DTC circuit according to the delay line selection length and the trigger signal to control the clock register to be set.

[0072] Optionally, the selected length of the delay line is decoded into a one-hot code by a decoder in the DTC circuit; the one-hot code is saved by a DTC data register in the DTC circuit to control a carry chain delay line connected to the DTC data register to carry according to the one-hot code, and output the second pulse signal; wherein the delay line includes a carry chain composed of a plurality of lookup tables connected in series; each of the lookup tables is connected to a corresponding DTC data register.

[0073] In this embodiment, this step determines the validity of the input synchronization signal according to the frequency of the synchronization signal, so as to avoid useless clock synchronization processing in the later stage and reduce the waste of FPGA resources. After monitoring a valid synchronization signal, the frequency of the synchronization signal is used to calculate the frequency coarse adjustment value, so that the first clock signal subsequently initialized and synthesized according to the frequency coarse adjustment value is close to the frequency required by the input synchronization signal, without slowly increasing the frequency until it is locked, and the rate of clock synchronization can be improved.

[0074] Furthermore, the period of the local clock signal and the coarse frequency adjustment value are used to initialize the synthetic clock signal, so that the synthetic clock signal fits the frequency of the synchronization signal, thereby improving the locking rate, and at the same time, the phase change is saved according to the clock register to realize the frequency division of the local clock; when dividing the frequency, the carry chain delay line composed of the carry chain formed by the series connection of the lookup table in the FPGA is used to rely on the DTC data register in the DTC circuit to realize the subdivision of the phase, thereby improving the resolution of the output clock and improving the accuracy of clock synchronization.

[0075] Step 102: Calculate the phase difference and frequency difference between the first clock signal and the synchronization signal through the second internal logic of the FPGA.

[0076] In this embodiment, this step mainly includes: measuring the phase difference between the first clock signal and the synchronization signal through the PFD circuit of the FPGA; wherein the PFD circuit includes a first delay line and a sampling circuit composed of a plurality of D flip-flops for sampling the output of the first delay line; the first delay line includes a carry chain composed of a plurality of lookup tables connected in series; and according to the phase difference, calculating the first frequency fine-tuning value corresponding to the first clock signal by the proportional integral method.

[0077] In this embodiment, this step uses the lookup table in the FPGA to form a series connection to construct a first delay line and uses a D flip-flop to form a sampling circuit to sample its output. The phase difference can be measured more accurately through the delay time of the carry chain, which is convenient for reducing output jitter and improving the stability of clock synchronization. Furthermore, the first frequency fine adjustment value is calculated using the proportional integral method to further fine-tune the frequency of the first clock signal and improve the accuracy of clock differences.

[0078] Step 103: According to the frequency difference and the phase difference, the local clock signal and the synchronization signal are synchronized and locked by the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output.

[0079] In this embodiment, this step mainly includes: obtaining the first rising edge time of the first clock signal and the second rising edge time of the synchronization signal; calculating the first time threshold and the second time threshold according to the second rising edge time and the single-stage delay time of the PFD circuit; comparing the first rising edge time with the first time threshold and the second time threshold; when the first rising edge time is greater than or equal to the first time threshold and less than or equal to the second time threshold, determining that the first clock signal and the synchronization signal are locked, and outputting the first clock signal as a synchronized clock signal.

[0080] Furthermore, when the first rising edge time is less than the first time threshold or the first rising edge time is greater than the second time threshold, the first frequency fine adjustment value is adjusted to generate a second frequency fine adjustment value; the sum of the second frequency fine adjustment value and the frequency coarse adjustment value is calculated, so as to perform cyclic frequency division processing on the local clock signal according to the sum of the second frequency fine adjustment value and the frequency coarse adjustment value and the period of the local clock signal through the first internal logic of the FPGA; when the rising edge time of the clock signal after the frequency division processing is greater than or equal to the first time threshold and less than or equal to the second time threshold, it is determined that the clock signal after the frequency division processing is locked with the synchronization signal, and the clock signal after the frequency division processing is output as the synchronized clock signal.

[0081] In this embodiment, this step uses the single-stage delay time of the carry chain and the rising edge time of the synchronization signal and the first clock signal to perform signal locking judgment. Among them, using the single-stage delay time of the carry chain as a reference can reduce the occupation of FPGA global clock resources and improve the efficiency of clock synchronization processing; further, using the frequency fine adjustment value and the frequency coarse adjustment value to synchronize and lock the synchronization signal and the first clock signal can effectively reduce the number of times the local clock signal is divided, thereby improving the efficiency of clock synchronization.

[0082] On the other hand, this embodiment also discloses a clock synchronization system based on FPGA. For the specific structure of the synchronization system, please refer to Figure 2 , including a main control module 201, an FPGA processing module 202, a synchronization signal source 203 and a local reference frequency source 204.

[0083] The main control module 201 and the FPGA processing module 202 are signal-connected to the synchronization signal source 203 for receiving a synchronization signal sent by the synchronization signal source 203 for synchronizing a clock signal.

[0084] The main control module 201 and the FPGA processing module 202 are signal-connected to the local reference frequency source 204 to receive a local clock signal sent by the local reference frequency source 204 .

[0085] The main control module 201 is connected to the FPGA processing module 202 by signal, and is used to obtain the frequency of the synchronization signal and the period of the local clock signal, and send the frequency and the period to the FPGA processing module 202, so that the FPGA processing module 202 performs the following operations:

[0086] Performing a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal;

[0087] Calculating a phase difference and a frequency difference between the first clock signal and the synchronization signal through a second internal logic of the FPGA;

[0088] According to the frequency difference and the phase difference, the local clock signal and the synchronization signal are synchronously locked through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output.

[0089] In this embodiment, the main control module 201 includes an information extraction unit, a signal detection unit and a calculation unit.

[0090] The information extraction unit is used to calculate a first frequency of the synchronization signal and a second frequency of the local clock signal.

[0091] The signal detection unit is used to compare the first frequency with a preset frequency range or compare the synchronization signal with a preset code pattern, so as to determine whether the synchronization signal is a valid signal according to the comparison result.

[0092] The calculation unit is used to calculate a frequency coarse adjustment value according to the first frequency and the second frequency and calculate a period of the local clock signal according to the second frequency when the synchronization signal is determined to be a valid signal.

[0093] The FPGA-based clock synchronization method and system disclosed in this embodiment can achieve synchronization of the local clock signal according to the external input synchronization signal by only using the internal logic of the FPGA. Among them, the first internal logic in the FPGA is used to divide the frequency of the local clock signal so that the divided clock signal and the synchronization signal are synchronized and locked. Furthermore, the second internal logic in the FPGA is used to calculate the phase difference and frequency difference between the divided first clock signal and the synchronization signal, so as to complete the synchronization lock of the local clock signal and the synchronization signal according to the phase difference and frequency difference. In the present invention, the internal resources of the FPGA are used to track the external input synchronization signal in real time, and then the local clock signal is divided to complete the clock synchronization. The synchronization processing of the clock signal can be achieved without the need for an external PLL or a tamed clock chip, thereby reducing the cost of clock synchronization.

[0094] Embodiment 2

[0095] This embodiment also provides a clock synchronization method based on FPGA. Specifically, refer to Figure 3 First, a digital phase-locked loop is constructed according to the internal logic of the FPGA to achieve synchronization locking between the synchronization signal sent by the synchronization signal source and the local clock signal sent by the local reference frequency source through the digital phase-locked loop.

[0096] Specifically, refer to Figure 3 ,The digital phase-locked loop built based on the internal logic of FPGA includes TDC-PFD module, loop filter, phase counter, carry chain DTC circuit, and clock register.

[0097] Reference Figure 3 , the TDC-PFD module is signal-connected to the control logic module, and the TDC-PFD module is also signal-connected to an external synchronization signal source; the loop filter is signal-connected to the TDC-PFD module and the phase counter; the phase counter is signal-connected to the local reference frequency source; specifically, the phase counter is signal-connected to the loop filter, the carry chain DTC circuit, and the control logic module; the carry chain DTC circuit receives the local clock signal sent by the local reference frequency source; the clock register receives the pulse signal sent by the phase counter and the pulse signal sent by the carry chain DTC circuit to generate a reference clock to the TDC-PFD module; the reference clock can be used to drive time-sensitive circuits; optionally, a PLL module can be used to process the reference clock to output the final reference clock signal. Reference Figure 3, PLL is a phase-locked loop; DPLL is a digital phase-locked loop; PFD is a phase-frequency discriminator; TDC is a time-to-digital converter; DTC is a digital-to-time converter; ADC is an analog-to-digital converter; DAC is a digital-to-analog converter; NCO is a digital oscillator.

[0098] Reference Figure 4 , which is based on the Figure 3 The flowchart of the method for performing clock synchronization on a digital phase-locked loop shown in the figure mainly includes steps 401 to 404, wherein the steps are:

[0099] Step 401: The control logic module detects whether the synchronization signal input by the synchronization signal source is valid, and when it is determined to be valid, calculates the frequency coarse adjustment value according to the frequency of the synchronization signal.

[0100] Specifically, in this embodiment, refer to Figure 5 , which is the process of the control logic module performing synchronization signal detection. Among them, when the control logic module detects a valid synchronization signal through frequency range or specific code pattern recognition, such as in the scenario where the audio Word C l ock is used as the synchronization signal, its input frequency must fall within the range of 8kHz-768kHz, and the synchronization signal can also be compared with a preset code pattern, such as the K.28 control code in the 8b / 10b encoding, to determine whether the synchronization signal is a valid signal based on the comparison result. The frequency of the synchronization signal can be roughly measured by a counter to determine whether the synchronization signal is valid, and then the frequency of the synchronization signal is measured or estimated, and then the frequency coarse adjustment value is output to the DTC-NCO module. At this time, the output frequency of the DTC-NCO module will be very close to the frequency required by the input synchronization signal, and there is no need to slowly increase the frequency until it is locked, which can increase the speed of the entire loop locking the synchronization signal.

[0101] Step 402: Initialize the DTC-NCO module according to the frequency coarse adjustment value, so that the DTC-NCO module divides the local clock signal provided by the local frequency reference source according to the frequency coarse adjustment value and outputs a first synthesized clock signal.

[0102] Specifically, in this embodiment, refer to Figure 6 , is a schematic diagram of the structure of the DTC-NCO module based on FPGA carry chain provided in this embodiment.

[0103] Reference Figure 6The DTC-NCO module includes a phase counter. The phase counter increments once at the rising edge of each local reference frequency source cycle, and the increment is a frequency control word, which is the sum of the input coarse frequency value and the fine frequency value. Specifically, during the initialization of the DTC-NCO module, the frequency control word is the coarse frequency value.

[0104] When the output phase exceeds 180 degrees, the 0->1 transition detection circuit outputs a pulse cycle, so that the clock output register is reset and outputs 0; when the output phase exceeds 0 degrees, the 1->0 transition detection circuit outputs a pulse cycle, so that the clock output register is set and outputs 1; thus:

[0105] Output clock frequency = local reference frequency source frequency / frequency control word / 2 相位计数器长度 ;

[0106] Output clock resolution = local reference frequency source frequency / 2 相位计数器长度 .

[0107] Further, refer to Figure 6 When the control clock output register is set, the DTC circuit based on the FPGA carry chain is introduced to achieve phase segmentation, thereby improving the output clock resolution. Figure 6 The DTC circuit is formed by the interconnection structure of FPGA. In the interconnection structure of FPGA, the interconnection structure that can connect multiple lookup table units in series is called a carry chain. In the lookup table unit, the delay of each level of the carry chain is related to different conditions such as device process, batch, voltage, temperature, etc.

[0108] In this embodiment, refer to Figure 6 , assuming that the delay of each delay line is 65ps, in order to ensure the highest subdivision resolution, the longest delay of the delay line needs to be equal to the local reference source period. If the local reference source period is 8ns, the number of carry chain delay lines needs to be at least 8ns / 65ps, which is approximately equal to 123 levels. In order to leave a margin and facilitate the design of the binary decoder, the number of delay lines is set to 128 levels.

[0109] Therefore, before the phase crosses 0 degree, the DTC-NCO module needs to obtain the difference between the phase counter and 0, and set the difference as the residual phase.

[0110] When calculating the length of the delay line to be used, set the intended output frequency of the delay line to Fo, the output period to To, the frequency control word to Fcw, the residual phase to Pr, the residual phase accumulator value to Ar, the local reference source period frequency to Fs, the delay of each stage of the delay line to Td, the number of delay line bits to D, the number of delay lines to Dn, the phase accumulator length to N, and the selected length of the delay line to Cd. Then the following mathematical relationship holds:

[0111] Fcw=Fo / Fs*2 N ; Pr = 2Pi*Ar / 2 N ; To=1 / Fo; Cd=To*Pr / 2Pi

[0112] / Td=To*Ar / (2 N *Td)=Ar / (2 N *Td*Fo)=Ar / (Td*Fcw*Fs);

[0113] Dn=2 D ;

[0114] Since Td = 1 / (Fs*Dn), we can substitute: Cd = Ar*Dn / Fcw; let K = Dn / Fcw, then Cd = Ar*K. To facilitate hardware calculation, Ar and Dn can be scaled by the same power of 2 according to parameters such as Fs, Td, and Fcw.

[0115] based on Figure 6 Only the residual phase will be updated every cycle, and the coarse frequency will hardly change during the entire synchronization process. Therefore, we can choose to remove the divider and select a fixed K value to reduce resource usage; we can also use a low-performance divider to slowly solve the K value, which will also not have a significant impact on system performance.

[0116] The solution result Cd, i.e., the delay line control signal, is decoded into a unique hot code and then passed to the DTC data register before the DTC carry chain: the closer the carry chain register to the DTC output port end is set, the shorter the delay; the farther the carry chain register from the DTC output port segment is set, the longer the output delay. When the phase exceeds 0 degrees, the 1->0 jump detection circuit outputs a DTC trigger signal, so that the following carry chain delay line carries one by one according to the delay value loaded in the DTC data register, outputs a pulse signal with an accurately adjustable time interval, sets the output register, and achieves an output rising edge time resolution as low as 65ps (instance value). This meets the requirements of most scenarios for the output jitter and resolution indicators of the clock recovery circuit. Considering that various types of PFDs only compare rising edges, improving the resolution only for rising edges can reduce FPGA resource usage and increase timing margins.

[0117] Alternatively, if the output jitter is still not satisfied or a constant duty cycle is required or a higher output frequency is required for data recovery (CDR), the built-in PLL resources of the FPGA can be used to multiply and de-jitter the clock signal output by the output register to achieve higher clock output indicators. Figure 3 The PLL related logic is shown in the figure.

[0118] Step 403: Calculate the phase difference between the first synthesized clock signal and the synchronization signal according to the TDC-PFD module, so that the loop filter calculates the frequency fine adjustment value according to the phase difference.

[0119] Specifically, in this embodiment, in the interconnection structure of the FPGA, the interconnection structure that can connect multiple lookup table units in series is called a carry chain. In the lookup table unit, the delay of each level of the carry chain is related to different conditions such as device process, batch, voltage, temperature, etc.

[0120] The first synthesized clock signal synthesized by the DTC-NCO module passes through a multi-stage delay line composed of a carry chain, is sampled by a D flip-flop triggered by the rising edge of the synchronization signal, and then synchronized to the local reference frequency source clock domain through two stages of D flip-flops for use by the loop filter logic.

[0121] Specifically, Figure 7 and Figure 8 As shown, the TDC-PFD module consists of a carry chain composed of two lookup tables (LUTs) connected in series and three D flip-flops (DFFs) sampling the output of the carry chain to form a three-stage delay line, or a carry chain composed of three lookup tables connected in series and four D flip-flops sampling the output of the carry chain to form a four-stage delay line.

[0122] The example measures the phase difference between the synchronization signal and the synthesized clock through the three-stage carry chain delay line or the four-stage carry chain delay line, but in fact, more than three-stage delay lines or four-stage carry chain delay lines are also feasible. When the number of stages of the delay line is increased, the number of lookup tables used is controlled to be the number of stages minus one, and the number of D flip-flops used is equal to the number of stages. More stages of delay lines can measure the phase difference more accurately, which is convenient for reducing output jitter and improving loop stability. Users can select a suitable delay line length based on various indicators such as loop locking speed, delay per stage of the delay line, input signal jitter, etc.

[0123] Furthermore, the loop filter uses the proportional integral method (PI) to generate a fine-tuning frequency value according to the phase error and then inputs it into the DTC-NCO module, so that the signal frequency output by the DTC-NCO module changes. The loop filter performs a proportional integral operation on the output of the TDC-PFD according to the set proportional coefficient (P) and integral coefficient (I), and outputs an error signal, which is used to adjust the fine-tuning frequency value to complete the closed-loop control of the system.

[0124] Step 404: The control logic module obtains the occurrence time of the rising edge of the first synthetic clock signal and the synchronization signal to perform signal synchronization locking according to the occurrence time.

[0125] Specifically, in this embodiment, the TDC-PFD uses the delay at the midpoint of the delay line after the rising edge of the synchronization signal as a reference. For example, if each level has a delay of 65ps and the TDC-PFD structure has a 3-level structure, if the rising edge of the synthesized clock occurs at the rising edge of the synchronization signal + 65ps (reference time), the TDC-PFD outputs a synchronization indication signal; if the rising edge of the synthesized signal is earlier than the reference time, the TDC-PFD outputs an advance indication signal; if the rising edge of the synthesized signal is later than the reference time, the TDC-PFD outputs a lag indication signal.

[0126] When the entire loop is locked, the phase difference output of the TDC-PFD will remain in the synchronization indication state, and other logic can use this to determine whether the entire loop has been locked. When the lock is lost, the TDC-PFD will output a lag or lead adjustment signal based on the phase difference (it can be the lead lag amount or just the lead lag state, depending on the TDC level), so that the loop is gradually re-locked and the reference clock and synchronization signal are restored to synchronization.

[0127] Furthermore, when the TDC-PFD outputs the lead adjustment signal, since the synthesized clock is ahead of the synchronization signal, the result is that the fine adjustment frequency value is reduced, so that the DTC-NCO output frequency gradually decreases. When the synthesized clock and the synchronization signal are completely in the same frequency and phase, the TDC-PFD does not output the lead / lag indication signal, then the synthesized clock and the synchronization signal are completely synchronized, and the system is locked.

[0128] When the TDC-PFD outputs an advance adjustment signal or a lag adjustment signal, the phase counter in the DTC-NCO module is used to further divide the local reference clock signal through the DTC-NCO module according to the sum of the fine adjustment frequency value and the coarse adjustment frequency value, until the TDC-PFD outputs a synchronization signal to complete the synchronization locking of the signal.

[0129] The FPGA-based clock synchronization method disclosed in this embodiment uses a tamed clock method to recover the clock, compared to a direct PLL recovery method, allowing a lower synchronization pulse frequency to meet scenarios where the input synchronization signal frequency is only a few Hz to tens of kHz, such as 1588v2 PTP, audio Word C l ock, etc. After losing the synchronization signal, it can continue to run freely at the previously locked frequency without oscillator instability; and when the synchronization signal is restored, it can be quickly relocked. There is no need for the user to detect the loss of the synchronization signal and start the fail-safe logic; compared to adjustable reference frequency source structures such as VC-TCXO, the adjustment range is wide and the locking is fast; compared to recovery methods such as DSM fractional-N PLL or DDS, no external devices are required, the time resolution is high, and the cost is low.

[0130] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A clock synchronization method based on FPGA, characterized in that: include: Acquire the frequency of the synchronization signal and the period of the local clock signal, and perform a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal; Calculating a phase difference and a frequency difference between the first clock signal and the synchronization signal through a second internal logic of the FPGA; According to the frequency difference and the phase difference, the local clock signal and the synchronization signal are synchronously locked through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output.

2. The FPGA-based clock synchronization method according to claim 1, characterized in that: The acquiring the frequency of the synchronization signal and the period of the local clock signal includes: Acquire a synchronization signal input by a synchronization signal source and a local clock signal input by a local reference frequency source, and calculate a first frequency of the synchronization signal and a second frequency of the local clock signal; Comparing the first frequency with a preset frequency range or comparing the synchronization signal with a preset code pattern, so as to determine whether the synchronization signal is a valid signal according to the comparison result; When the synchronization signal is determined to be a valid signal, a frequency coarse adjustment value is calculated according to the first frequency and the second frequency, and a period of the local clock signal is calculated according to the second frequency.

3. The FPGA-based clock synchronization method according to claim 2, characterized in that: The step of performing a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal includes: Accumulating and calculating the frequency coarse adjustment value in real time according to the cycle to obtain a first phase corresponding to each cycle; According to the first phase and a preset phase threshold, the state of the clock register in the FPGA is adjusted in real time to output the first clock signal through the clock register.

4. The FPGA-based clock synchronization method according to claim 3, characterized in that: The step of adjusting the state of the clock register in the FPGA in real time according to the first phase and a preset phase threshold comprises: Comparing the first phase with a preset first phase threshold, and when the first phase is greater than the first phase threshold, generating a first pulse signal to control the clock register to be reset; Compare the first phase with a preset second phase threshold, and when the first phase is greater than the second phase threshold, calculate a first phase difference between the first phase and the second phase threshold and generate a trigger signal of a DTC circuit in the FPGA; The delay line selection length in the DTC circuit is calculated according to the first phase difference value, so as to output a second pulse signal through the DTC circuit to control the clock register to be set according to the delay line selection length and the trigger signal.

5. The FPGA-based clock synchronization method according to claim 4, characterized in that: The step of outputting a second pulse signal through the DTC circuit to control the clock register to be set includes: Decoding the delay line selection length into a one-hot code by a decoder in the DTC circuit; The one-hot code is stored in the DTC data register in the DTC circuit, so as to control the delay line connected to the DTC data register to carry according to the one-hot code and output the second pulse signal; wherein the delay line includes a carry chain composed of a plurality of lookup tables connected in series; each of the lookup tables is connected to a corresponding DTC data register.

6. The FPGA-based clock synchronization method according to claim 1, characterized in that: The calculating the phase difference and frequency difference between the first clock signal and the synchronization signal by the second internal logic of the FPGA includes: The phase difference between the first clock signal and the synchronization signal is measured by the PFD circuit of the FPGA; wherein the PFD circuit includes a first delay line and a sampling circuit composed of a plurality of D flip-flops for sampling the output of the first delay line; the first delay line includes a carry chain composed of a plurality of lookup tables connected in series; According to the phase difference, a first frequency fine adjustment value corresponding to the first clock signal is calculated by a proportional integral method.

7. The FPGA-based clock synchronization method according to claim 6, characterized in that: The method of realizing synchronization locking between the local clock signal and the synchronization signal through the first internal logic and the second internal logic of the FPGA, and outputting the synchronized clock signal, comprises: Acquire a first rising edge time of the first clock signal and a second rising edge time of the synchronization signal; Calculate a first time threshold and a second time threshold according to the second rising edge time and a single-stage delay time of the PFD circuit; Comparing the first rising edge time with the first time threshold and the second time threshold; When the first rising edge time is greater than or equal to the first time threshold and less than or equal to the second time threshold, it is determined that the first clock signal and the synchronization signal are locked, and the first clock signal is output as a synchronized clock signal.

8. The FPGA-based clock synchronization method according to claim 6 or 7, characterized in that: The output synchronized clock signal comprises: When the first rising edge time is less than the first time threshold or the first rising edge time is greater than the second time threshold, adjusting the first frequency fine adjustment value to generate a second frequency fine adjustment value; Calculating the sum of the second frequency fine adjustment value and the frequency coarse adjustment value, so as to perform cyclic frequency division processing on the local clock signal according to the sum of the second frequency fine adjustment value and the frequency coarse adjustment value and the period of the local clock signal through the first internal logic of the FPGA; When the rising edge time of the clock signal after the frequency division processing is greater than or equal to the first time threshold and less than or equal to the second time threshold, it is determined that the clock signal after the frequency division processing is locked with the synchronization signal, and the clock signal after the frequency division processing is output as a synchronized clock signal.

9. The clock synchronization system based on FPGA is characterized by: It includes a main control module, an FPGA processing module, a synchronization signal source and a local reference frequency source; The main control module and the FPGA processing module are connected to the synchronization signal source signal, and are used to receive the synchronization signal sent by the synchronization signal source for synchronizing the clock signal; The main control module and the FPGA processing module are connected to the local reference frequency source signal to receive the local clock signal sent by the local reference frequency source; The main control module is connected to the FPGA processing module by signal, and is used to obtain the frequency of the synchronization signal and the period of the local clock signal, and send the frequency and the period to the FPGA processing module, so that the FPGA processing module performs the following operations: Performing a first frequency division process on the local clock signal through a first internal logic of the FPGA to obtain a first clock signal; Calculating a phase difference and a frequency difference between the first clock signal and the synchronization signal through a second internal logic of the FPGA; According to the frequency difference and the phase difference, the local clock signal and the synchronization signal are synchronously locked through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output.

10. The FPGA-based clock synchronization system according to claim 9, characterized in that: The main control module includes an information extraction unit, a signal detection unit and a calculation unit; The information extraction unit is used to calculate the first frequency of the synchronization signal and the second frequency of the local clock signal; The signal detection unit is used to compare the first frequency with a preset frequency range or compare the synchronization signal with a preset code pattern, so as to determine whether the synchronization signal is a valid signal according to the comparison result; The calculation unit is used to calculate a frequency coarse adjustment value according to the first frequency and the second frequency and calculate a period of the local clock signal according to the second frequency when the synchronization signal is determined to be a valid signal.

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