Ferroelectric vertical transistor based on oxide semiconductor and preparation method thereof

Abstract

The invention belongs to the related technical field of microelectronic devices, and discloses a ferroelectric vertical transistor based on an oxide semiconductor and a preparation method thereof, and the ferroelectric vertical transistor comprises a substrate, a gate metal electrode, a gate ferroelectric layer, a gate insulating dielectric layer, an island-shaped source electrode, the oxide semiconductor, a source electrode contact electrode and a top drain electrode. According to the invention, the hafnium oxide-based ferroelectric material is used as the gate ferroelectric material, so that the information writing and reading can be realized, the regulation effect of the gate voltage on the channel is amplified, the ratio of the gate capacitance to the channel capacitance is reduced, and the working voltage of the transistor is reduced, thereby reducing the power consumption of the ferroelectric vertical transistor. Besides, a gate insulating dielectric layer is prepared on the gate ferroelectric film to promote the formation of a ferroelectric phase, and the introduction of the insulating dielectric layer can inhibit the injection of charges, so that the polarization state of the hafnium oxide-based ferroelectric material is adjusted, and the overall performance of the ferroelectric transistor is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field related to microelectronic devices, and more specifically, relates to a ferroelectric vertical transistor based on oxide semiconductor and a preparation method thereof. Background Art

[0002] With the continuous development of the information age and global interconnection, the data generated globally has shown a short-term, exponential growth in recent years; with the arrival of new scenarios such as emerging robots, smart life, and smart driving, more and more large models have been developed to support the huge data computing needs. However, the development of transistor technology has approached the limit of Moore's Law, and further miniaturization of transistor size faces problems such as short channel effect, tunneling effect, and excessive power consumption; at the same time, due to the natural properties of the electron Boltzmann distribution characteristics, the subthreshold swing limit of the transistor is about 60mV / decade, which makes it very difficult for traditional planar transistor MOSFETs to achieve low power consumption in large-scale integrated circuits. Therefore, in order to meet the huge data storage needs and overcome the power consumption problem of large-scale integrated circuits, it is necessary to develop ultra-low power, fast read and write, and stable performance storage devices.

[0003] Inorganic ferroelectric transistors have unique advantages in low-power devices. The main principle is to use the polarization reversal characteristics of ferroelectric materials to write and read information, thereby realizing information storage. The current mainstream ferroelectric memory is mainly divided into two categories: 1T1C and 1T. Among them, the 1T1C type reads data destructively, and needs to rewrite the data after reading it. The maximum number of reads is limited, and in addition to the transistor, there is a capacitor in the circuit, which is not conducive to high-density integration. The 1T structure of a single transistor has non-destructive data reading, a relatively simple structure, and is easier to integrate on a large scale. Although two-dimensional materials are favorable channel materials for continuing the Moore's limit, their high contact resistance with the metal electrode interface increases the power consumption of the device and is incompatible with CMOS technology. Therefore, the development of transistors that can overcome the short channel effect, have low power consumption, high storage characteristics, and are compatible with CMOS technology is an important direction for future storage transistors. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a ferroelectric vertical transistor based on oxide semiconductor and a preparation method thereof, the purpose of which is to construct a ferroelectric vertical transistor with ultra-short channel, low power consumption and high storage characteristics, thereby solving the technical problems of short channel effect and tunneling effect that appear in traditional planar transistors as the channel size is miniaturized.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present invention, a ferroelectric vertical transistor based on oxide semiconductor is provided, wherein the ferroelectric vertical transistor comprises a substrate 100, a gate metal electrode 200, a gate ferroelectric layer 300, a gate insulating dielectric layer 400, an island source 500, an oxide semiconductor 600, a source contact electrode 700 and a top drain 800; the substrate 100, the gate metal electrode 200, the gate ferroelectric layer 300, the gate insulating dielectric layer 400 and the island source 500 are stacked layer by layer from bottom to top, the oxide semiconductor 600 and the source contact electrode 700 are arranged on the island source, the top drain 800 is arranged on the oxide semiconductor 600, the channel length of the ferroelectric vertical transistor is the actual thickness of the oxide semiconductor 600, and the ferroelectric vertical transistor controls the polarization direction of the gate ferroelectric layer 300 by positive and negative gate voltages, thereby realizing erasing and writing of data by the ferroelectric vertical transistor.

[0006] Preferably, the substrate 100 is a rigid substrate or a flexible substrate with an insulating layer.

[0007] Preferably, the gate metal electrode 200 is a tungsten electrode prepared by magnetron sputtering or electron beam evaporation, and has a thickness of 30 nm to 80 nm.

[0008] Preferably, the gate ferroelectric layer 300 is one of HZO, HfO2, and ZrO2 thin films prepared by atomic layer deposition, and has a thickness of 5 nm to 20 nm.

[0009] Preferably, the gate insulating dielectric layer 400 is an Al2O3 thin film prepared by atomic layer deposition, and has a thickness of 3 nm to 5 nm.

[0010] Preferably, the island-shaped source electrode 500 is configured to be one of ultra-thin island-shaped aluminum prepared by magnetron sputtering and ultra-thin island-shaped silver prepared by thermal evaporation.

[0011] Preferably, the oxide semiconductor 600 is a semiconductor layer prepared by magnetron sputtering, and has a thickness of 10 nm to 25 nm.

[0012] Preferably, the source contact electrode 700 is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm-80nm; the top drain 800 is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm-80nm.

[0013] According to another aspect of the present invention, there is provided a method for preparing a ferroelectric vertical transistor based on an oxide semiconductor, comprising the following steps:

[0014] (1) On a substrate 100 with an insulating layer, a tungsten electrode is prepared by magnetron sputtering or electron beam evaporation to serve as a gate metal electrode 200;

[0015] (2) On the gate metal electrode 200, a gate ferroelectric layer 300 and a gate insulating dielectric layer 400 are sequentially prepared from bottom to top by atomic layer deposition, and then the gate ferroelectric layer 300 and the gate insulating dielectric layer 400 are rapidly annealed in a rapid annealing furnace, the annealing temperature is 350° C. to 450° C., and the annealing time is 40 s to 60 s;

[0016] (3) On the gate insulating dielectric layer 400, an ultra-thin island-shaped aluminum is prepared by magnetron sputtering or an ultra-thin island-shaped silver is prepared by thermal evaporation, and after annealing, an island-shaped source electrode 500 is formed;

[0017] (4) Opening a window on the island source 500 by photolithography or masking, and preparing the oxide semiconductor 600 by magnetron sputtering;

[0018] (5) opening windows on the island source 500 and the oxide semiconductor 600 respectively by photolithography or masking, and then preparing a top drain 800 on the oxide semiconductor 600 and a source contact electrode 700 on the island source 500 by thermal evaporation, magnetron sputtering or printing, to obtain a ferroelectric vertical transistor;

[0019] (6) The ferroelectric vertical transistor is subjected to overall annealing to finally complete the preparation of the ferroelectric vertical transistor.

[0020] Preferably, in step (3), the magnetron sputtering process parameters are set as: power 60W-80W, pressure 1.3×10-4Torr; the metal thickness of the island source 500 ranges from 5nm to 15nm, and the annealing temperature is between 150°C and 250°C.

[0021] In general, compared with the prior art, the above technical solution conceived by the present invention provides a ferroelectric vertical transistor based on oxide semiconductor and a preparation method thereof, which mainly has the following beneficial effects:

[0022] 1. The present invention mainly proposes a new inorganic ferroelectric vertical transistor structure, which adopts a vertical structure design. The channel length of the vertical transistor is determined by the thickness of the oxide semiconductor. The short channel construction of the transistor is achieved by preparing an ultra-thin, high-quality semiconductor film. The ultra-short semiconductor channel brings high current density and high-speed response speed to the transistor. At the same time, ultra-thin island-shaped metals are used as the source by magnetron sputtering or thermal evaporation, which increases the controllability of the transistor source preparation.

[0023] 2. The present invention utilizes hafnium oxide-based ferroelectric materials as gate ferroelectric materials. On the one hand, the polarization of ferroelectric materials in different directions under positive and negative gate voltages is utilized to realize the writing and reading of information. On the other hand, the application of hafnium oxide-based ferroelectric materials can amplify the regulating effect of gate voltage on the channel, reduce the ratio of gate capacitance to channel capacitance, and reduce the operating voltage of the transistor to reduce the power consumption of the device.

[0024] 3. The present invention prepares a gate insulating dielectric layer on the gate ferroelectric layer film to promote the formation of a ferroelectric phase. At the same time, the introduction of the insulating dielectric layer can inhibit the injection of charges, thereby adjusting the polarization state of the hafnium oxide-based ferroelectric material, so that the ferroelectric vertical transistor has a higher hysteresis and a larger storage window, thereby improving the overall performance of the ferroelectric vertical transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the structure obtained in step 1 of the preparation method in an embodiment of the present invention;

[0026] Figure 2 Schematic diagram of the structure obtained in step 2 of the preparation method in an embodiment of the present invention;

[0027] Figure 3 Schematic diagram of the structure obtained in step 3 of the preparation method in an embodiment of the present invention;

[0028] Figure 4 Schematic diagram of the structure obtained in step 4 of the preparation method in an embodiment of the present invention;

[0029] Figure 5 Schematic diagram of the structure obtained in step 5 of the preparation method in an embodiment of the present invention;

[0030] Figure 6 Schematic diagram of the structure obtained in step 6 of the preparation method in an embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of the structure obtained in step 7 of the preparation method in an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of an expected transfer characteristic curve of a ferroelectric vertical transistor prepared in an embodiment of the present invention;

[0033] Throughout the drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0034] 100—substrate, 200—gate metal electrode, 300—gate ferroelectric layer, 400—gate insulating dielectric layer, 500—island source, 600—oxide semiconductor, 700—source contact electrode, 800—top drain. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] This embodiment introduces a HZO-based In2O3 ferroelectric vertical transistor and a preparation method thereof. The ferroelectric vertical transistor, such as Figure 7 As shown, it includes a substrate (100), a gate metal electrode (200), a gate ferroelectric layer (300), a gate insulating dielectric layer (400), an island source (500), an oxide semiconductor (600), a source contact electrode (700) and a top drain (800); the substrate (100), the gate metal electrode (200), the gate ferroelectric layer (300), the gate insulating dielectric layer (400), and the island source (500) are stacked from bottom to top, the oxide semiconductor (600) and the source contact electrode (700) are arranged on the island source, and the top drain (800) is arranged on the oxide semiconductor (600). The channel length of the ferroelectric vertical transistor is the actual thickness of the oxide semiconductor (600), and the ferroelectric vertical transistor controls the polarization direction of the gate ferroelectric layer (300) by positive and negative gate voltages, thereby realizing the erasing and writing of data by the ferroelectric vertical transistor.

[0037] The specific steps of a method for preparing an In2O3 ferroelectric vertical transistor based on HZO are as follows:

[0038] Step 1: Prepare a substrate 100 .

[0039] Select a silicon wafer with 300nm SiO2, cut it into 2cm×2cm size using a dicing machine, then ultrasonically clean it in acetone and isopropanol for 15min each, rinse it with deionized water, and blow it dry with nitrogen to use as a substrate. Figure 1 .

[0040] Step 2: Preparation of gate metal electrode 200 .

[0041] The tungsten electrode was prepared by using a DC target material of magnetron sputtering. The substrate with a window of 250μm×350μm previously opened by laser direct writing was placed in the chamber. The experiment was started after vacuuming. The process parameters were DC 120W, 50sccm Ar, and a 50nm tungsten electrode was prepared as the gate metal electrode. Figure 2 .

[0042] Step 3: Preparation of the gate ferroelectric layer 300 .

[0043] Using the atomic layer deposition process, the oxygen source, zirconium source and hafnium source are preheated, the sample is placed in the reaction chamber, and then the chamber is evacuated. At 300°C as the reaction temperature, a 15nm HZO film is grown on the gate metal electrode. Figure 3 .

[0044] Step 4: Preparation of gate insulating dielectric layer 400 .

[0045] Using the atomic layer deposition process, the oxygen source and aluminum source are preheated, the sample is placed in the reaction chamber, and then the chamber is evacuated. At 280°C as the reaction temperature, a 5nm Al2O3 film is grown on the HZO film as the gate insulating dielectric layer. Figure 4 ; The prepared film is then rapidly annealed at 450°C / 45s in a rapid annealing furnace to promote the formation of the HZO ferroelectric phase.

[0046] Step 5: Preparation of the island-shaped source electrode 500 .

[0047] Using magnetron sputtering equipment, after the chamber is evacuated to high vacuum, DC sputtering is performed on the gate insulating dielectric layer with a power of 80W and a pre-sputtering time of 5 minutes. Then the substrate baffle is opened and sputtering is performed for 5 minutes. Finally, annealing is performed at 150°C to form an island source, such as Figure 5 .

[0048] Step 6: Preparation of oxide semiconductor 600 .

[0049] A 150 μm×250 μm window is opened on the island source obtained in step 5 by laser direct writing, and then In2O3 is sputtered by direct current magnetron sputtering with process parameters of 60 W, 35 sccm Ar, and 5 sccm O2 to prepare 20 nm In2O3 as an oxide semiconductor, such as Figure 6 .

[0050] Step 7: Preparation of source contact electrode 700 and top drain electrode 800 .

[0051] A 100 μm×100 μm window is opened on the island source 500 obtained in step 5 and the semiconductor channel 600 obtained in step 6 by laser direct writing, and then Al is sputtered by direct current magnetron sputtering with process parameters of 80 W and 20 sccm Ar to prepare 50 nm Al as the source contact electrode 700 and the top drain 800, as shown in FIG. Figure 7 .

[0052] Step 8: Annealing of the ferroelectric vertical transistor.

[0053] In a tubular furnace, the ferroelectric vertical transistor is subjected to overall annealing. The process scheme is annealing at 250° C. for 1 hour in a nitrogen atmosphere to complete the preparation of the ferroelectric vertical transistor.

[0054] The transfer characteristic curve of the ferroelectric vertical transistor in this embodiment is as follows: Figure 8 . This embodiment uses a hafnium oxide-based ferroelectric dielectric layer, which can amplify the regulation of the gate voltage on the channel, reduce the ratio of gate capacitance to channel capacitance, and achieve low-power operation of the transistor. It is expected that the prepared ferroelectric vertical transistor has a low subthreshold swing. At the same time, since an additional gate insulating dielectric layer is added above the gate ferroelectric layer, the formation of a ferroelectric phase in the ferroelectric material is further promoted, and the prepared ferroelectric vertical transistor has a higher hysteresis and a larger storage window.

[0055] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A ferroelectric vertical transistor based on an oxide semiconductor, characterized in that: The ferroelectric vertical transistor comprises a substrate (100), a gate metal electrode (200), a gate ferroelectric layer (300), a gate insulating dielectric layer (400), an island source (500), an oxide semiconductor (600), a source contact electrode (700) and a top drain (800); the substrate (100), the gate metal electrode (200), the gate ferroelectric layer (300), the gate insulating dielectric layer (400) and the island source (500) are stacked layer by layer from bottom to top, the oxide semiconductor (600) and the source contact electrode (700) are arranged on the island source, the top drain (800) is arranged on the oxide semiconductor (600), the channel length of the ferroelectric vertical transistor is the actual thickness of the oxide semiconductor (600), and the ferroelectric vertical transistor controls the polarization direction of the gate ferroelectric layer (300) by positive and negative gate voltages, thereby realizing erasing and writing of data by the ferroelectric vertical transistor.

2. The ferroelectric vertical transistor based on oxide semiconductor according to claim 1, characterized in that: The substrate (100) is a rigid substrate or a flexible substrate with an insulating layer.

3. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, characterized in that: The gate metal electrode (200) is a tungsten electrode prepared by magnetron sputtering or electron beam evaporation, and has a thickness of 30 nm to 80 nm.

4. The ferroelectric vertical transistor based on oxide semiconductor according to claim 1, characterized in that: The gate ferroelectric layer (300) is one of HZO, HfO2 and ZrO2 thin films prepared by atomic layer deposition, and has a thickness of 5nm to 20nm.

5. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, characterized in that: The gate insulating dielectric layer (400) is an Al2O3 film prepared by atomic layer deposition, and has a thickness of 3nm to 5nm.

6. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, characterized in that: The island-shaped source (500) is configured to be one of ultra-thin island-shaped aluminum prepared by magnetron sputtering and ultra-thin island-shaped silver prepared by thermal evaporation.

7. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, characterized in that: The oxide semiconductor (600) is a semiconductor layer prepared by magnetron sputtering, and has a thickness of 10 nm to 25 nm.

8. The oxide semiconductor-based ferroelectric vertical transistor according to claim 1, characterized in that: The source contact electrode (700) is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm-80nm; the top drain (800) is one of aluminum, silver, gold and indium tin oxide, and its thickness is 40nm-80nm.

9. A method for preparing a ferroelectric vertical transistor based on an oxide semiconductor as claimed in any one of claims 1 to 8, characterized in that: The following steps are involved: (1) On a substrate (100) with an insulating layer, a tungsten electrode is prepared by magnetron sputtering or electron beam evaporation to serve as a gate metal electrode (200); (2) on the gate metal electrode (200), a gate ferroelectric layer (300) and a gate insulating dielectric layer (400) are sequentially prepared from bottom to top by atomic layer deposition, and then a rapid annealing furnace is used to rapidly anneal the gate ferroelectric layer (300) and the gate insulating dielectric layer (400), wherein the annealing temperature is 350° C. to 450° C. and the annealing time is 40 s to 60 s; (3) On the gate insulating dielectric layer (400), ultra-thin island-shaped aluminum prepared by magnetron sputtering or ultra-thin island-shaped silver prepared by thermal evaporation is annealed to form an island-shaped source electrode (500); (4) opening a window on the island source (500) by photolithography or masking, and preparing an oxide semiconductor (600) by magnetron sputtering; (5) opening windows on the island source (500) and the oxide semiconductor (600) respectively by photolithography or masking, and then preparing a top drain (800) on the oxide semiconductor (600) and a source contact electrode (700) on the island source (500) by thermal evaporation, magnetron sputtering or printing, to obtain a ferroelectric vertical transistor; (6) The ferroelectric vertical transistor is subjected to overall annealing to finally complete the preparation of the ferroelectric vertical transistor.

10. The method for preparing a ferroelectric vertical transistor based on an oxide semiconductor according to claim 1, characterized in that: In the step (3), the magnetron sputtering process parameters are set as: power 60W-80W, pressure 1.3×10-4 Torr; the metal thickness of the island source (500) ranges from 5nm to 15nm, and the annealing temperature is between 150°C and 250°C.

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