Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a plurality of pixel circuits, each pixel circuit comprises a plurality of transistors, the display panel further comprises a substrate, a first organic layer and a first metal layer, the first organic layer is arranged on one side of the substrate, and the first metal layer is arranged on the side, away from the substrate, of the first organic layer; the first metal layer comprises a first conductor part, and the first conductor part is overlapped with the orthographic projection of at least one transistor in the pixel circuit on the substrate. Wherein the first conductor part comprises a first opening, and the orthographic projection of the first opening on the substrate is at least partially overlapped with the orthographic projection of the first organic layer on the substrate. According to the display panel, the first opening is additionally formed in the first conductor part, so that water vapor and the like remaining in the first organic layer can be released through the first opening, the risks of film layer bulging and first conductor part falling caused by sealing of the water vapor are improved, and the preparation yield and the use reliability of the display panel are improved.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to a display panel and a display device. Background Art

[0002] With the development of science and technology, the field of display panels has also achieved tremendous progress and diversified development. On this basis, people's requirements for display panels are also increasing day by day. How to improve the reliability of display panels while meeting performance requirements has become one of the research directions of manufacturers. Summary of the invention

[0003] Embodiments of the present application provide a display panel and a display device, which can improve the reliability of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel includes a plurality of pixel circuits, the pixel circuits include a plurality of transistors, the display panel also includes a substrate, a first organic layer and a first metal layer, the first organic layer is arranged on one side of the substrate, the first metal layer is arranged on the side of the first organic layer away from the substrate, the first metal layer includes a first conductor portion, the first conductor portion and at least one transistor in the pixel circuit are overlapped in their orthographic projection on the substrate. The first conductor portion includes a first opening, the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the first organic layer on the substrate.

[0005] In a second aspect, an embodiment of the present application provides a display device, which includes a display panel in any of the aforementioned embodiments.

[0006] The embodiment of the present application provides a display panel and a display device, in which the first conductor part is used not only to transmit a specific signal to meet the operation requirements of the display panel, but also to cover and shield the transistor, thereby reducing the possibility that the light emitted by the display panel itself or the ambient light will irradiate the transistor due to refraction or reflection, etc., reducing the adverse effect of light on the transistor, and improving the operation reliability of the pixel circuit. On this basis, by adding a first opening in the first conductor part, the water vapor remaining in the first organic layer can be released through the first opening, thereby improving the risk of film bulging and the first conductor part falling off due to the sealed water vapor, and improving the production yield and use reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0008] Figure 1is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application;

[0009] Figure 2 is a schematic diagram of a cross-sectional structure of a display panel at another area provided by an embodiment of the present application;

[0010] Figure 3 This is a simplified arrangement diagram of a pixel circuit provided in an embodiment of the present application;

[0011] Figure 4a and Figure 4b It is a simplified circuit diagram of two pixel circuits in a display panel provided in an embodiment of the present application;

[0012] Figure 5 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0013] Figure 6a and Figure 6b is a schematic structural diagram of a first metal layer in another display panel provided in an embodiment of the present application;

[0014] Figure 7 This is another simplified schematic diagram of a circuit layout in a display panel provided in an embodiment of the present application;

[0015] Figure 8 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0016] Fig. 9 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0017] Fig.10 It is a schematic diagram of a local pixel arrangement structure of another display panel provided in an embodiment of the present application;

[0018] Fig.11 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0019] Fig.12 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0020] Fig.13 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0021] Fig.14 is a schematic structural diagram of a second metal layer in another display panel provided in an embodiment of the present application;

[0022] Fig.15 is a schematic diagram of the positional relationship between the first metal layer and the second metal layer in another display panel provided in an embodiment of the present application;

[0023] Fig.16 The present application provides another schematic diagram of the positional relationship between the first metal layer and the first organic layer in a display panel;

[0024] Fig.17 It is a structural schematic diagram of a display device provided in an embodiment of the present application.

[0025] Marking Description:

[0026] 100. display panel; 200. display device;

[0027] 10. Substrate;

[0028] 20. first organic layer; 21. exhaust hole;

[0029] 30. first metal layer; 31. first conductor portion; 311. first sub-portion; 312. second sub-portion; 313. connection portion; 32. first opening; 321. first type of opening; 322. second type of opening; 33. conduction portion;

[0030] 41. first insulating layer; 42. second insulating layer; 421. second opening;

[0031] 50. second metal layer; 51. second conductor portion; 52. third type opening; 53. fourth type opening; 54. first pad; 55. second pad;

[0032] 61, first active layer; 611, first active structure; 612, first exposed portion; 62, second active layer; 621, second active structure; 622, second exposed portion;

[0033] P, pixel circuit; P1, pulse width modulation circuit; P2, pulse amplitude modulation circuit; M, transistor; C, repetitive circuit group; J, spacing area; V, shift register unit; F, light emitting element;

[0034] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0035] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0036] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0037] First, see Figures 1 to 3 The embodiment of the present application provides a display panel 100, which includes a plurality of pixel circuits P, the pixel circuits P include a plurality of transistors M, the display panel 100 also includes a substrate 10, a first organic layer 20 and a first metal layer 30, the first organic layer 20 is disposed on one side of the substrate 10, the first metal layer 30 is disposed on the side of the first organic layer 20 away from the substrate 10, the first metal layer 30 includes a first conductor portion 31, the first conductor portion 31 is overlapped with the orthographic projection of at least one transistor M in the pixel circuit P on the substrate 10. The first conductor portion 31 includes a first opening 32, the orthographic projection of the first opening 32 on the substrate 10 at least partially overlaps with the orthographic projection of the first organic layer 20 on the substrate 10.

[0038] The display panel 100 is a device for displaying images. The display panel 100 may include a light-emitting element. The light-emitting element is a main component for realizing the light-emitting function. The light-emitting element may be a micro light-emitting element such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a sub-millimeter light-emitting diode (Mini Light Emitting Diode, MiniLED). Among them, the light-emitting element may have a variety of structural forms, for example, the light-emitting element may be a flip-chip, or a face-mounted chip, or a vertical chip, which is not limited in the embodiments of the present application.

[0039] The pixel circuit P is a circuit structure used to drive and control whether the light-emitting element emits light or not. There are multiple pixel circuits P, and the multiple pixel circuits P respectively control different light-emitting elements to realize the light-emitting function. Figure 3, it is shown that a plurality of adjacently arranged pixel circuits P together form a repeated circuit group C, and the plurality of repeated circuit groups C are arranged in arrays along a plurality of directions. The pixel circuit P may include a plurality of device structures such as a storage capacitor and a transistor M. The specific form of the pixel circuit P is not limited in the embodiment of the present application. Figure 4a and Figure 4b , Figure 4a and Figure 4b Two different forms of pixel circuits P are provided in the embodiment of the present application, wherein Figure 4a and Figure 4b In the embodiment, the pixel circuit P includes a pulse width modulation circuit P1 and a pulse amplitude modulation circuit P2, and the pulse width modulation circuit P1 and the pulse amplitude modulation circuit P2 each include a plurality of transistors M.

[0040] The substrate 10 is a film layer used for supporting and bearing in the display panel 100. Other film layer structures and device structures are stacked sequentially on the substrate 10. The stacking arrangement mentioned here means that other film layer structures and device structures are sequentially arranged along the thickness direction Z of the substrate 10. Among them, the thickness direction Z of the substrate 10 is usually consistent with the thickness direction Z of other film layers. For the convenience of description, the thickness direction Z of the substrate 10 and the thickness direction Z of other film layers are schematically shown in the same direction in the embodiments of the present application.

[0041] The first metal layer 30 is a film layer provided on one side of the substrate 10 and including a metal conductor material. The first metal layer 30 includes a first conductor portion 31. The first conductor portion 31 may have a variety of shapes and sizes. For example, the orthographic projection of the first conductor portion 31 on the substrate 10 may be a whole-surface structure, or the first conductor portion 31 may include a plurality of sub-portion structures, and the orthographic projection of a single sub-portion structure on the substrate 10 may also be a strip-shaped or block-shaped structure.

[0042] The first conductor portion 31 may be a conductor structure for transmitting a specific signal in the display panel 100. The embodiment of the present application does not limit the specific type of the signal transmitted by the first conductor portion 31. Furthermore, the conductor structures in different regions of the first conductor portion 31 may be used to transmit the same potential voltage, or may also be used to transmit different potential voltages.

[0043] The orthographic projection of the first conductor portion 31 on the substrate 10 at least partially overlaps with that of at least one transistor M in the pixel circuit P. The “at least partially overlap” mentioned here means that there is an overlapping area between the orthographic projection of the first conductor portion 31 and at least one transistor M on the substrate 10, wherein the orthographic projection of the first conductor portion 31 on the substrate 10 may overlap with only one transistor M, or the orthographic projection of the first conductor portion 31 on the substrate 10 may overlap with multiple transistors M at the same time.

[0044] The transistor M is usually composed of different structures located in different film layers. For example, the transistor M may include an active structure located in an active layer, a control terminal located in one of the conductor layers, and a first electrode and a second electrode located in other conductor layers. The control terminal is used to control whether the first electrode and the second electrode are turned on or off. Under this design, in addition to being used to transmit specific signals to meet the operating needs of the display panel 100, the first conductor portion 31 can also cover and shield the transistor M, reduce the possibility that the light emitted by the display panel 100 itself or the ambient light is irradiated on the transistor M due to refraction or reflection, reduce the adverse effects of light on the transistor M, and improve the operating reliability of the pixel circuit P.

[0045] In some optional embodiments, the dimensions of the first conductor portion 31 in the first direction X and the second direction are not less than 40 μm, and the first direction X, the second direction, and the thickness direction Z intersect each other. In this way, the first conductor portion 31 is a large metal structure, which helps to improve the covering and shielding effect of the first conductor portion 31 on the transistor M, and further reduce the adverse effects of light on the transistor M.

[0046] The first organic layer 20 is a film layer provided on one side of the substrate 10 and including an organic material. The first organic layer 20 is provided between the substrate 10 and the first metal layer 30, wherein the first organic layer 20 may be provided in contact with the first metal layer 30, or the first organic layer 20 may be provided spaced apart from the first metal layer 30 in the thickness direction Z. In addition to insulating and isolating the first metal layer 30 from other conductive film layers located on the side of the first organic layer 20 facing the substrate 10, the first organic layer 20 may also reduce the parasitic capacitance formed between the first metal layer 30 and other conductive film layers located on the side of the first organic layer 20 facing the substrate 10, thereby improving the performance and stability of the circuit structure in the display panel 100.

[0047] It should be noted that, in addition to the above-mentioned film layer structure, the display panel 100 may also have other film layer structures, such as Figure 1 As shown, the first organic layer 20 may further include a first conductive functional layer B1 and a second conductive functional layer B2 on the side facing the substrate 10, wherein both the first conductive functional layer B1 and the second conductive functional layer B2 include a conductor material, wherein the first conductive functional layer B1 may be provided with signal lines such as a data line and a power signal line, and the second conductive functional layer B2 may be provided with signal lines such as a scan line and a light-emitting control line. Alternatively, the first electrode and the second electrode of the transistor M may be located in the first conductive functional layer B1, and the control terminal may be located in the second conductive functional layer B2.

[0048] During the preparation of the display panel 100, the display panel 100 needs to go through multiple film-forming processes. During the preparation of the first organic layer 20, water vapor will be sealed between the first organic layer 20 and other film layers located on the side away from the substrate 10, waiting for the discharge of gas. On this basis, at the position where the first conductor part 31 overlaps with the first organic layer 20, the first conductor part 31 will hinder the release process of the gas, resulting in increased difficulty in gas release. Especially for the first conductor part 31 with a larger projected area, for example, when the size of the first conductor part 31 in the first direction X and the second direction is not less than 40μm, the difficulty of gas release is further increased. At this time, the display panel 100 is prone to bulging at a local position, and it is easy to cause the risk of the first conductor part 31 falling off, affecting the preparation yield and reliability of the display panel 100.

[0049] In view of this, the embodiment of the present application adjusts the structure of the first conductor part 31, and adds a first opening 32 in the first conductor part 31. The first opening 32 is arranged to penetrate the first conductor part 31 along the thickness direction Z, and the orthographic projection of the first opening 32 on the substrate 10 at least partially overlaps with the orthographic projection of the first organic layer 20 on the substrate 10. In this way, at least part of the structure in the first organic layer 20 can be exposed relative to the first conductor part 31 by means of the first opening 32, so that during the manufacturing process corresponding to the first conductor part 31, the water vapor and the like remaining in the first organic layer 20 can be released through the first opening 32, thereby improving the risk of film bulging and the falling off of the first conductor part 31 caused by the sealed water vapor, and improving the manufacturing yield and the reliability of the display panel 100.

[0050] It should be noted that the embodiment of the present application does not limit the size, shape and number of the first opening 32. There may be only one first opening 32, or there may be multiple first openings 32. When there are multiple first openings 32, the shapes and sizes of different first openings 32 may be the same or different. For example, the orthographic projection of the first opening 32 on the substrate 10 may be a regular shape such as a circle, a triangle, or a square, or may be an irregular shape, and the embodiment of the present application does not limit this.

[0051] The embodiment of the present application does not limit the positional relationship between the first opening 32 and the transistor M. The orthographic projection of the first opening 32 on the substrate 10 can be overlapped with the orthographic projection of the transistor M on the substrate 10, or as shown in FIG. Figure 2As shown, it may also be arranged not to overlap with the orthographic projection of the transistor M on the substrate 10. Further, when there are multiple first openings 32, the orthographic projections of each first opening 32 on the substrate 10 may overlap with the orthographic projection of the transistor M on the substrate 10, or the orthographic projections of each first opening 32 on the substrate 10 may not overlap with the orthographic projection of the transistor M on the substrate 10, or the orthographic projections of some first openings 32 on the substrate 10 overlap with the orthographic projection of the transistor M on the substrate 10, and the orthographic projections of other first openings 32 on the substrate 10 do not overlap with the orthographic projection of the transistor M on the substrate 10.

[0052] In addition, the conductor structures of the first conductor part 31 located on different sides of the first opening 32 can be used to transmit the same potential voltage, or can also be used to transmit different potential voltages, that is, the conductor structures of the first conductor part 31 located on different sides of the first opening 32 can be used to transmit different signals. Further, the conductor structures of the first conductor part 31 located on different sides of the first opening 32 can be connected as a whole, or can also be disconnected from each other.

[0053] In summary, in the embodiment of the present application, the first conductor portion 31 is used not only to transmit specific signals to meet the operation requirements of the display panel 100, but also to cover and shield the transistor M, thereby reducing the possibility that the light emitted by the display panel 100 itself or the ambient light is irradiated on the transistor M due to refraction or reflection, etc., reducing the adverse effect of light on the transistor M, and improving the operation reliability of the pixel circuit P. On this basis, by adding the first opening 32 in the first conductor portion 31, the water vapor remaining in the first organic layer 20 can be released through the first opening 32, thereby improving the risk of film bulging and the first conductor portion 31 falling off due to the sealed water vapor, and improving the production yield and use reliability of the display panel 100.

[0054] In some embodiments, see Figure 5 , at least a portion of the orthographic projection of the first opening 32 on the substrate 10 overlaps at least a portion of the orthographic projection of the transistor M in the pixel circuit P on the substrate 10; and / or Figure 2 As shown, at least a portion of the orthographic projection of the first opening 32 on the substrate 10 is located outside the orthographic projection of each transistor M in the pixel circuit P on the substrate 10 .

[0055] For the first opening 32, a single first opening 32 and the transistor M may have a variety of positional relationships, and when there are multiple first openings 32, the positional relationships between different first openings 32 and the transistor M may be the same or different. On this basis, according to different actual needs, the orthographic projection of some or all of the first openings 32 on the substrate 10 may be overlapped with the orthographic projection of the transistor M in the pixel circuit P on the substrate 10, or the orthographic projection of some or all of the first openings 32 on the substrate 10 may be not overlapped with the orthographic projection of the transistor M in the pixel circuit P on the substrate 10.

[0056] It should be noted that when the orthographic projection of a single first opening 32 on the substrate 10 is located outside the orthographic projections of each transistor M in the pixel circuit P on the substrate 10, the orthographic projection of the first opening 32 on the substrate 10 may be located between the orthographic projections of adjacent pixel circuits P on the substrate 10, or the orthographic projection of the first opening 32 on the substrate 10 may also be located on the outer peripheral side of the orthographic projections of all pixel circuits P on the substrate 10, or the orthographic projection of the first opening 32 on the substrate 10 may also be located within the range of the orthographic projection of a single pixel circuit P on the substrate 10, and may be staggered with the orthographic projections of each transistor M on the substrate 10, and the embodiments of the present application do not impose any restrictions on this.

[0057] In the embodiment of the present application, the first opening 32 and the transistor M may have a variety of positional relationships, and the positional relationships between different first openings 32 and the transistor M may be the same or different. On this basis, by changing the number and relative positions of the first openings 32, it is possible to reduce the adverse effects of light on the transistor M while improving the water vapor release effect, reducing the risk of film bulging and the first conductor portion 31 falling off, and having strong flexibility and practicality.

[0058] In some embodiments, see Figure 1 , Figure 2 , Figure 5 as well as Figure 6a The plurality of first openings 32 include first-type openings 321 and second-type openings 322 . The size of the first-type openings 321 is greater than the size of the second-type openings 322 .

[0059] There are multiple first openings 32, and the multiple first openings 32 are arranged at intervals from each other, that is, there is a certain distance between adjacent first openings 32 and they are distributed in different areas of the display panel 100, so as to meet the exhaust needs of the display panel 100 at different positions. The multiple first openings 32 include first-type openings 321 and second-type openings 322. The size of the first-type openings 321 is larger than the size of the second-type openings 322. The "size" mentioned here refers to the orthographic projection area on the substrate 10, that is, the orthographic projection area of ​​the first-type openings 321 on the substrate 10 is larger than the orthographic projection area of ​​the second-type openings 322 on the substrate 10.

[0060] Furthermore, the first type of opening 321 refers to an opening whose corresponding orthographic projection area is larger than the first preset value, and the second type of opening 322 refers to an opening whose corresponding orthographic projection area is smaller than the first preset value. The specific size of the first preset value is not limited in the embodiment of the present application. Optionally, the first preset value is 40 μm. 2 There may be multiple first-type openings 321, and the shapes and sizes of different first-type openings 321 on the substrate 10 may be the same or different. Similarly, there may be multiple second-type openings 322, and the shapes and sizes of different second-type openings 322 on the substrate 10 may be the same or different.

[0061] Optionally, the number of the first type of openings 321 is less than the number of the second type of openings 322 .

[0062] The embodiment of the present application does not limit the positional relationship between the first type of opening 321 and the second type of opening 322 relative to the pixel circuit P. The orthographic projection of the first type of opening 321 on the substrate 10 can be arranged to overlap with the orthographic projection of the pixel circuit P on the substrate 10, or can be arranged not to overlap. The positional relationship between the second type of opening 322 and the pixel circuit P is similar to the same, and the embodiment of the present application will not be repeated.

[0063] In the embodiment of the present application, in view of the different needs in different areas of the display panel 100, the plurality of first openings 32 are configured to include first-type openings 321 and second-type openings 322 of different sizes and spaced apart from each other, so as to further increase the gas release effect at a specific position with the help of the first-type openings 321, thereby improving the manufacturing yield. The existence of the second-type openings 322 can achieve a covering and shielding effect on the underlying film structure with the help of the conductor structure around the second-type openings 322 while meeting the gas release needs, thereby helping to improve the performance of the display panel 100.

[0064] In some embodiments, Figure 1 , Figure 2 , Figure 5 as well as Figure 6aAs shown, on a plane perpendicular to the display panel 100, the first type of opening 321 and the pixel circuit P do not overlap; on a plane perpendicular to the display panel 100, at least part of the second type of opening 322 overlaps with the pixel circuit P. Figure 6a The pixel circuit P is schematically shown in the form of a dotted box.

[0065] The direction perpendicular to the plane where the display panel 100 is located is the thickness direction Z. On this basis, the first type of opening 321 and the pixel circuit P do not overlap, that is, the orthographic projection of the first type of opening 321 on the substrate 10 is located outside the orthographic projection of the pixel circuit P on the substrate 10. At least part of the second type of opening 322 overlaps with the pixel circuit P, that is, the orthographic projection of at least part of the second type of opening 322 on the substrate 10 and the orthographic projection of the pixel circuit P on the substrate 10 have an overlapping area. Among them, when there are multiple second type of openings 322, all of the second type of openings 322 may overlap with the pixel circuit P, or some of the second type of openings 322 overlap with the pixel circuit P, and some of the second type of openings 322 do not overlap with the pixel circuit P.

[0066] In the embodiment of the present application, the first type of opening 321 is an opening structure with a relatively large size. By arranging the first type of opening 321 and the pixel circuit P not to overlap, the exhaust function can be realized outside the area where the pixel circuit P is located, the gas release effect can be improved, and the risk of performance degradation caused by large-area exposure of the pixel circuit P to the first type of opening 321 can be reduced. As for the second type of opening 322, by overlapping at least part of the second type of opening 322 with the pixel circuit P, the exhaust requirement at the area where the pixel circuit P is located can be met with the help of the second type of opening 322. Since the second type of opening 322 is an opening structure with a relatively small size, the exposed area of ​​the pixel circuit P at the second type of opening 322 is relatively small, thereby reducing the degree of performance degradation of the pixel circuit P due to light irradiation and laser bonding, etc., which helps to improve the manufacturing yield and use effect of the display panel 100.

[0067] In some embodiments, the orthographic projection of the first type opening 321 on the substrate 10 is located between the orthographic projections of adjacent pixel circuits P on the substrate 10. Figure 6a In the embodiment, the plurality of pixel circuits P include a first circuit D1 and a second circuit D2 , and a portion of the first type openings 321 are located between the first circuit D1 and the second circuit D2 .

[0068] In the embodiment of the present application, considering that at least some of the adjacent pixel circuits P may have a larger spacing dimension, the first type of openings 321 are correspondingly arranged between the adjacent pixel openings. This design can, on the one hand, improve the gas release capability of the first conductor part 31 with the help of the first type of openings 321, and reduce the risk of the first conductor part 31 falling off. On the other hand, it can also meet the need to avoid the first type of openings 321 relative to the pixel circuits P, and reduce the risk of performance degradation caused by the large area of ​​the pixel circuits P being exposed to the first type of openings 321.

[0069] It should be noted that only one first-type opening 321 may be provided between two adjacent pixel circuits P, or multiple first-type openings 321 may be provided at the same time, and the embodiment of the present application is not limited to this. Optionally, multiple first-type openings 321 may be provided between two pixel circuits P adjacently provided in the first direction X, and the multiple first-type openings 321 are arranged side by side and spaced apart along the second direction Y, and the first direction X, the second direction Y, and the thickness direction Z intersect each other.

[0070] In some embodiments, Figure 1 , Figure 2 , Figure 5 as well as Figure 6a As shown, a plurality of adjacent pixel circuits P together form a repeated circuit group C, and a plurality of repeated circuit groups C are repeatedly arranged; wherein adjacent repeated circuit groups C are arranged at intervals to form a spacing area J, and the first type of opening 321 is located in the spacing area J.

[0071] The display panel 100 includes a plurality of repeating circuit groups C, and the structural layout of the pixel circuits P in each repeating circuit group C and the arrangement of different pixel circuits P are consistent. The plurality of repeating circuit groups C may be arranged along only one direction, or may be arranged along multiple directions. Figure 6a As shown, a single repeating circuit group C includes a first pixel circuit PX1, a second pixel circuit PX2, and a third pixel circuit PX3 arranged side by side along a first direction X, and a plurality of repeating circuit groups C are arranged along the first direction X and the second direction Y. Among them, the first circuit D1 is the third pixel circuit PX3 in one repeating circuit group C, and the second circuit DP2 is the first pixel circuit PX1 in another repeating circuit group C.

[0072] Furthermore, the display panel 100 may include a pixel unit composed of a plurality of light-emitting elements, and the plurality of pixel units are repeatedly arranged, wherein the pixel unit and the repeated circuit group C are arranged corresponding to each other, that is, the plurality of pixel circuits P in a single repeated circuit group C are used to drive the plurality of light-emitting elements in a single pixel unit, and different pixel circuits P in different repeated circuit groups C are used to drive different light-emitting elements in different pixel units.

[0073] In some optional embodiments, the arrangement of multiple pixel circuits P in a single repeating circuit group C is the same as the arrangement of multiple light-emitting elements F in a single pixel unit, and the arrangement of multiple repeating circuit groups C is the same as the arrangement of corresponding pixel units.

[0074] In the embodiment of the present application, the spacing area J is an area between adjacent repeating circuit groups C and is not provided with pixel circuits P. Compared with the distance between two adjacent pixel circuits P in a single repeating circuit group C, the distance between two adjacent pixel circuits P in adjacent repeating circuit groups C is often larger. On this basis, by arranging the first type of opening 321 in the spacing area J, the first type of opening 321 is located between two adjacent pixel circuits P in adjacent repeating circuit groups C. In this way, the first type of opening 321 can avoid the pixel circuits P while having a larger size, thereby improving the gas release capability of the first conductor part 31 and reducing the risk of film bulging and the first conductor part 31 falling off.

[0075] It should be noted that, according to different actual needs, some of the second type openings 322 may also be arranged in the spacer J, or there may be no second type openings 322 in the spacer J, and the embodiment of the present application is not limited to this. Optionally, there are both first type openings 321 and second type openings 322 in the spacer J, and a plurality of second type openings 322 are located between adjacent first type openings 321.

[0076] In some embodiments, see Figure 1 , Figure 2 , Figure 5 , Figure 6b as well as Figure 7 The display panel 100 further includes a shift register unit V, which is located between adjacent pixel circuits P. The orthographic projection of the shift register unit V on the substrate 10 is at least partially overlapped with the orthographic projection of the first type of opening 321 on the substrate 10; and / or, the orthographic projection of the shift register unit V on the substrate 10 is at least partially overlapped with the orthographic projection of the second type of opening 322 on the substrate 10.

[0077] The shift register unit V is a sequential logic circuit that can store and transmit specific signals. The shift register unit V includes a plurality of cascaded shift register circuits, and the connection between these shift register circuits enables the output end of a shift register circuit to be electrically connected to the corresponding signal line and also to provide an input signal to the next level shift register circuit.

[0078] The display panel 100 may include a display area and a frame area located around the display area. The display area is an area in the display panel 100 for realizing light-emitting display and the light-emitting element F and the corresponding pixel circuit P are both arranged in the display area. The frame area is located around the display area and can be used to set up some wiring and circuit structures. On this basis, the shift register unit V is located between adjacent pixel circuits P, that is, the shift register unit V is also arranged in the display area, which can save the space required for setting the shift register unit V in the frame area, which is conducive to the display panel 100 to achieve a narrow frame effect, that is, to achieve a higher screen-to-body ratio display.

[0079] The specific positions of the multiple shift register circuits in the shift register unit V relative to the pixel circuit P are not limited in the embodiments of the present application. For example, taking the first direction X as the row direction and the second direction Y as the column direction, the multiple pixel circuits P arranged side by side along the first direction X together form a circuit row, and the multiple pixel circuits P arranged side by side along the second direction Y together form a circuit column. In this case, Figure 7 As shown, a single shift register circuit can be arranged between adjacent circuit rows, or can also be arranged between adjacent circuit columns, as long as there is a spacing distance between adjacent shift register circuits in the second direction Y.

[0080] In addition, the embodiment of the present application does not limit the type of signal output by the shift register unit V. For example, the display panel 100 includes a scan line, and the shift register unit V can be electrically connected to the scan line to provide a scan signal scan to the scan line. Alternatively, the display panel 100 includes a light-emitting control line, and the shift register unit V can be electrically connected to the light-emitting control line to provide a light-emitting control signal em to the light-emitting control line.

[0081] Further, in the embodiment of the present application, since the shift register unit V is located between adjacent pixel circuits P, the orthographic projection of the shift register unit V on the substrate 10 can be arranged to overlap with the first opening 32 on the substrate 10. Further, according to different actual needs, the shift register unit V can be selectively arranged to overlap with at least one of the first type of opening 321 and the second type of opening 322, thereby reducing the risk of bulging or film shedding of the display panel 100 in the area where the shift register unit V is located, and improving the reliability of the display panel 100.

[0082] In some embodiments, see Figure 8 The first organic layer 20 includes a vent hole 21 , and the first opening 32 at least partially overlaps with an orthographic projection of the vent hole 21 on the substrate 10 .

[0083] The exhaust hole 21 is a hole-like structure formed by the surface of the first organic layer 20 facing away from the substrate 10 and recessed inward to realize the exhaust function. The exhaust hole 21 can be completely set through the first organic layer 20 along the thickness direction Z, or the exhaust hole 21 can also be set through only a part of the structure of the first organic layer 20 along the thickness direction Z. The exhaust hole 21 can have a variety of sizes and shapes. For example, the orthographic projection of the exhaust hole 21 on the substrate 10 can be circular, square or other regular and irregular shapes.

[0084] The orthographic projections of the first opening 32 and the exhaust hole 21 on the substrate 10 at least partially overlap, that is, the first opening 32 and the exhaust hole 21 are arranged at corresponding positions. The orthographic projection of the first opening 32 on the substrate 10 may completely cover the orthographic projection of the exhaust hole 21 on the substrate 10, or the orthographic projection of the first opening 32 on the substrate 10 may only cover the orthographic projection of a part of the structure of the exhaust hole 21 on the substrate 10.

[0085] In the embodiment of the present application, an exhaust hole 21 is additionally provided in the display panel 100, and the exhaust hole 21 is arranged at a position corresponding to the first opening 32, so that water vapor and the like remaining in the first organic layer 20 can be moved to the first opening 32 through the exhaust hole 21, and released through the first opening 32. In this way, the cooperation between the first opening 32 and the exhaust hole 21 helps to further improve the risk of film bulging and falling off of the first conductor portion 31 due to the sealing of water vapor, thereby improving the preparation yield and the reliability of use of the display panel 100.

[0086] In some embodiments, Figure 8 As shown, the orthographic projection of the exhaust hole 21 on the substrate 10 is located within the orthographic projection of the first opening 32 on the substrate 10 , and the orthographic projection area of ​​the exhaust hole 21 on the substrate 10 is smaller than the orthographic projection area of ​​the first opening 32 on the substrate 10 .

[0087] It can be seen from the accompanying drawings that since the orthographic projection area corresponding to the exhaust hole 21 is smaller than the first opening 32, and the position of the exhaust hole 21 is completely corresponding to the first opening 32, the first conductor portion 31 can be completely set on the surface of the first organic layer 20 facing away from the substrate 10, that is, the first conductor portion 31 will not be located in the exhaust hole 21, and the first organic layer 20 can provide flat support for the first conductor portion 31.

[0088] Furthermore, in the process of manufacturing the display panel 100, this design can also enable the exhaust hole 21 to be formed behind the first opening 32. Specifically, a continuous and full-surface organic material layer can be formed first, and then a first metal layer 30 is formed on the organic material layer. Then, with the shielding effect of the first conductor portion 31 in the first metal layer 30, a portion of the structure of the organic material layer corresponding to the first opening 32 can be etched away, thereby forming the first organic layer 20 and the exhaust hole 21 corresponding to the first opening 32.

[0089] In this way, the exhaust holes 21 can be formed in the first organic layer 20 without the need for a mask plate, which helps to reduce the difficulty and cost of preparation. At the same time, the organic material layer with a full-surface structure can provide a flat and complete surface for the preparation of the first metal layer 30, thereby reducing the difficulty of preparing the first metal layer 30 and improving the preparation reliability of the first metal layer 30.

[0090] In summary, in the embodiment of the present application, the exhaust hole 21 is completely located in the first opening 32, so that the first conductor part 31 is completely located on the surface of the first organic layer 20 on the side away from the substrate 10, thereby providing a flat support for the first conductor part 31. And when the gas is released through the exhaust hole 21, the first conductor part 31 will not be in the gas release path, thereby reducing the risk of the first conductor part 31 falling off or bulging relative to the first organic layer 20. Further, this also helps to reduce the difficulty and cost of preparation, and improve the preparation reliability of the first metal layer 30.

[0091] In some embodiments, Figure 8 As shown, the display panel 100 further includes a first insulating layer 41 disposed on a side of the first metal layer 30 facing away from the substrate 10 , and a portion of the structure in the first insulating layer 41 is located in the first opening 32 and the exhaust hole 21 .

[0092] The first insulating layer 41 is a film layer structure located on the side of the first metal layer 30 away from the substrate 10 and including an insulating material. The first insulating layer 41 can have a variety of material compositions, for example, the first insulating layer 41 can include an organic insulating material, or can also include an inorganic insulating material. Among them, the first insulating layer 41 can be directly in contact with the first metal layer 30, or can also be spaced apart, that is, other film layer structures can be sandwiched between the first metal layer 30 and the first insulating layer 41, or there can be no other film layer structures, and the embodiment of the present application does not limit this.

[0093] In the embodiment of the present application, part of the structure in the first insulating layer 41 is located in the first opening 32 and the exhaust hole 21, so that the first insulating layer 41 can provide a relatively flat surface while meeting the insulation requirements of the display panel 100, thereby reducing the adverse effects of the exhaust hole 21 and the first opening 32 on the preparation of other film layers located on the side of the first insulating layer 41 away from the substrate 10, which helps to improve the preparation yield and reliability of the display panel 100.

[0094] In some embodiments, the first insulating layer 41 is disposed in contact with the sidewall of the first conductor portion 31 facing the first opening 32 .

[0095] In the embodiment of the present application, there is no other film layer structure between the first insulating layer 41 and the first metal layer 30. The first insulating layer 41 can insulate the first conductor portion 31, thereby reducing the risk of contact short circuit between the first conductor portion 31 and other conductors or semiconductor structures located on the side of the first insulating layer 41 away from the substrate 10, thereby improving the reliability of signal transmission corresponding to the first conductor portion 31.

[0096] Furthermore, the first insulating layer 41 is also arranged to fit the side wall of the first conductor portion 31 toward the first opening 32. In this way, during the preparation of other film layers on the side of the first insulating layer 41 facing away from the substrate 10, the first insulating layer 41 can cover and protect the first conductor layer, thereby reducing the risk of the first conductor portion 31 being side-etched and the risk of oxidation reaction on the side wall of the first conductor portion 31, thereby improving the structural reliability of the first conductor portion 31.

[0097] In some embodiments, see Fig. 9 The display panel 100 further includes a second insulating layer 42 disposed between the first metal layer 30 and the first organic layer 20 . The second insulating layer 42 includes a second opening 421 . The second opening 421 overlaps with the exhaust hole 21 in an orthographic projection of the substrate 10 .

[0098] The second insulating layer 42 is a film structure including an insulating material and located between the first organic layer 20 and the first metal layer 30. The second insulating layer 42 may have a variety of material compositions, for example, the second insulating layer 42 may include an organic insulating material, or may include an inorganic insulating material. The second insulating layer 42 may be directly in contact with the first metal layer 30, or may be spaced apart, that is, other film structures may be sandwiched between the second metal layer 50 and the first insulating layer 41, or other film structures may not exist. The relationship between the second insulating layer 42 and the first organic layer 20 is similar to the relationship between the second insulating layer 42 and the first organic layer 20, and the embodiments of the present application do not limit this.

[0099] The second insulating layer 42 includes a second opening 421, and the second opening 421 at least partially overlaps with the orthographic projection of the exhaust hole 21 on the substrate 10, that is, the second opening 421 is arranged corresponding to the position of the exhaust hole 21. Further optionally, the second opening 421 at least partially overlaps with the orthographic projection of the first opening 32 on the substrate 10. The orthographic projection of the second opening 421 on the substrate 10 may completely cover the orthographic projection of the exhaust hole 21 on the substrate 10, or the orthographic projection of the second opening 421 on the substrate 10 may only cover the orthographic projection of a part of the structure of the exhaust hole 21 on the substrate 10.

[0100] In the embodiment of the present application, since there is a second insulating layer 42 between the first organic layer 20 and the first metal layer 30, in order to reduce the effect of the second insulating layer 42 on the release of gases such as water vapor in the first organic layer 20, a second opening 421 is added in the second insulating layer 42, and the second opening 421 is arranged corresponding to the position of the exhaust hole 21, so that the water vapor and the like remaining in the first organic layer 20 can move to the first opening 32 through the exhaust hole 21 and the second opening 421 in sequence, and be released through the first opening 32. In this way, the cooperation of the first opening 32, the second opening 421 and the exhaust hole 21 helps to further improve the risk of film bulging and falling off of the first conductor portion 31 due to the sealing of water vapor, thereby improving the preparation yield and use reliability of the display panel 100.

[0101] In some embodiments, the second insulating layer 42 includes an inorganic material.

[0102] The chemical inertness of inorganic materials is relatively stable, and inorganic materials have a certain function of isolating water vapor. On this basis, in order to meet the need for water vapor release, the embodiment of the present application is provided with a second opening 421 in the second insulating layer 42. Water vapor can move to the first opening 32 through the exhaust holes 21 and the second opening 421 in sequence, and be released through the first opening 32, thereby reducing problems such as bulging caused by the accumulation of water vapor on the side of the second insulating layer 42 toward the substrate 10, thereby improving the reliability of the display panel 100.

[0103] In some embodiments, see Fig.10 The display panel 100 further includes a second metal layer 50 disposed on one side of the substrate 10 . The second metal layer 50 includes a second conductor portion 51 . The orthographic projection of the second conductor portion 51 on the substrate 10 overlaps with the orthographic projection of at least part of the first opening 32 on the substrate 10 .

[0104] The second metal layer 50 is a film layer structure including a metal conductor material and located on the same side of the substrate 10 as the first metal layer 30. The second metal layer 50 may be located on the side of the first metal layer 30 facing the substrate 10, or the second metal layer 50 may be located on the side of the first metal layer 30 facing away from the substrate 10. Further optionally, the display panel 100 includes a first active layer 61, and the first metal layer 30 and the second metal layer 50 are both located on the side of the first active layer 61 facing away from the substrate 10.

[0105] The second metal layer 50 includes a second conductor portion 51. Depending on actual needs, the second conductor portion 51 can be used to transmit the same type of signal as the first conductor portion 31, or can also transmit different types of signals. Furthermore, the second conductor portion 51 can be insulated from the first conductor portion 31, or the second conductor portion 51 can also be electrically connected to the first conductor portion 31 through a via or the like.

[0106] The embodiment of the present application does not limit the specific shape and size of the second conductor portion 51. For example, the orthographic projection of the second conductor portion 51 on the substrate 10 can be a planar structure, or the second conductor portion 51 can also include a plurality of sub-portion structures arranged at intervals, and the orthographic projection of a single sub-portion structure on the substrate 10 can be a strip or block structure.

[0107] The orthographic projection of the second conductor portion 51 on the substrate 10 overlaps with the orthographic projection of at least part of the first openings 32 on the substrate 10, that is, there is an overlapping region between the orthographic projection of the second conductor portion 51 on the substrate 10 and the orthographic projection of at least part of the first openings 32 on the substrate 10. The orthographic projection of the second conductor portion 51 on the substrate 10 may overlap with the orthographic projection of all the first openings 32 on the substrate 10, or the orthographic projection of the second conductor portion 51 on the substrate 10 may overlap with only the orthographic projection of part of the first openings 32 on the substrate 10, while the orthographic projections of the other first openings 32 on the substrate 10 are located outside the orthographic projection of the second conductor portion 51 on the substrate 10.

[0108] Further, for the first opening 32 and the second conductor portion 51 that overlap each other, there may be various positions between the two, for example, the orthographic projection of the second conductor portion 51 on the substrate 10 may completely cover the orthographic projection of the first opening 32 on the substrate 10, or may overlap with the orthographic projection of part of the structure in the first opening 32 on the substrate 10, while the orthographic projection of other structures in the first opening 32 on the substrate 10 is located outside the orthographic projection of the second conductor portion 51 on the substrate 10. Optionally, the orthographic projection of the second conductor portion 51 on the substrate 10 completely covers at least part of the orthographic projection of the first opening 32 on the substrate 10.

[0109] In the embodiment of the present application, in addition to satisfying its own signal transmission function, the second conductor portion 51 and its partial structure corresponding to the area where the first opening 32 is located can also cover and protect other film layer structures located on the side of the second metal layer 50 facing the substrate 10, for example, it can protect at least part of the structure in the transistor M, thereby improving the manufacturing yield of the display panel 100.

[0110] In some embodiments, Fig.10 As shown, the display panel 100 also includes a first active layer 61 arranged on the side of the second metal layer 50 facing the substrate 10, the first active layer 61 includes a first active structure 611, the first active structure 611 includes a first exposed portion 612, the orthographic projection of the first exposed portion 612 on the substrate 10 is located within the first opening 32, and the orthographic projection of the second conductor portion 51 on the substrate 10 at least partially overlaps with the orthographic projection of the first exposed portion 612 on the substrate 10.

[0111] The first active layer 61 is a semiconductor film layer located on the side of the first metal layer 30 and the second metal layer 50 facing the substrate 10. According to different actual needs, the display panel 100 may include only one semiconductor film layer, the first active layer 61, or may include two semiconductor film layers at the same time. Specifically, when the display panel 100 includes only one semiconductor film layer, the first active layer 61, the pixel circuit P in the display panel 100 may adopt LTPS technology, and the LTPS technology only includes LTPS (Low Temperature Poly-Silicon)-TFT. In this case, the material of the first active layer 61 includes low temperature polysilicon. When the display panel 100 includes two semiconductor film layers at the same time, the pixel circuit in the display panel 100 may adopt LTPO technology, and the LTPO technology includes LTPS-TFT and IGZO (Indium Gallium Zinc Oxide)-TFT at the same time. In this case, the first active layer 61 may include low temperature polysilicon, or include metal oxide.

[0112] The first active structure 611 is a semiconductor structure located in the first active layer 61. The first active structure 611 includes a first exposed portion 612 corresponding to the position of the first opening 32. In combination with the foregoing content, it can be known that the multiple first openings 32 include first-type openings 321 and second-type openings 322 of different sizes, wherein the orthographic projection of the first-type opening 321 on the substrate 10 can be located outside the orthographic projection of the first active structure 611 on the substrate 10, and the orthographic projection of the second-type opening 322 on the substrate 10 has an overlapping area with the orthographic projection of the first active structure 611 on the substrate 10, and the partial structure of the first active structure 611 corresponding to the overlapping area is the first exposed portion 612.

[0113] Further, in the embodiment of the present application, the second metal layer 50 is located on the side of the first active layer 61 away from the substrate 10, and the orthographic projection of the second conductor portion 51 on the substrate 10 can overlap with the orthographic projection of the first exposed portion 612 on the substrate 10, so that the second conductor portion 51 can protect the first exposed portion 612, reduce the adverse effects of processes such as laser bonding on the first active structure 611, and improve the reliability of the first active structure 611 and the yield rate of the display panel 100. At the same time, the layout of the first active structure 611 may not be limited by the position of the first opening 32, which helps to reduce the layout difficulty of the first active structure 611, thereby improving the display effect and display accuracy.

[0114] In some embodiments, see Fig.11The second metal layer 50 is located on the side of the first metal layer 30 facing the substrate 10. The display panel 100 also includes a second active layer 62 arranged between the second metal layer 50 and the first metal layer 30. The second active layer 62 includes a second active structure 621. The orthographic projection of the second active structure 621 on the substrate 10 is located outside the orthographic projection of the first exposed portion 612 on the substrate 10.

[0115] In the embodiment of the present application, the display panel 100 includes two semiconductor film layers, a first active layer 61 and a second active layer 62 , that is, the pixel circuit P adopts LTPO technology, wherein the material of the first active layer 61 may include low-temperature polycrystalline silicon, and the material of the second active layer 62 includes metal oxide.

[0116] The first active layer 61, the first metal layer 30, the second active layer 62 and the second metal layer 50 are stacked in sequence in a direction gradually away from the substrate 10. In combination with the foregoing content, it can be seen that the first active structure 611 in the first active layer 61 will include a first exposed portion 612 corresponding to the first opening 32, and the second conductor portion 51 in the second metal layer 50 can be arranged corresponding to the first exposed portion 612 to protect the first exposed portion 612, reduce the risk of damage to the first exposed portion 612 due to processes such as laser bonding, and improve reliability.

[0117] Furthermore, with respect to the second active layer 62, since the second active layer 62 is located on the side of the second metal layer 50 away from the substrate 10, the second metal layer 50 cannot protect the second active layer 62 during the subsequent manufacturing process. On this basis, in order to reduce the risk of the second active layer 62, the embodiment of the present application also sets the second active structure 621 in the second active layer 62 to be located outside the orthographic projection of the first opening 32 on the substrate 10 in the orthographic projection of the substrate 10. Further, optionally, the orthographic projection of the second active structure 621 on the substrate 10 can be completely located within the orthographic projection of the first conductor portion 31 on the substrate 10, so that the first conductor portion 31 can protect the second active structure 621, thereby reducing the risk of damage to the second active structure 621 due to processes such as laser bonding, thereby improving reliability.

[0118] In summary, in the embodiment of the present application, since the first active layer 61 is located on the side of the first metal layer 30 and the second metal layer 50 facing the substrate 10, some structures in the first active structure 611, such as the first exposed portion 612, can be arranged corresponding to the first opening 32, and the first exposed portion 612 can be protected by the second conductor portion 51. As for the second active layer 62, since it is located between the first metal layer 30 and the second metal layer 50, in order to reduce the impact of subsequent processes on the second active layer 62, the orthographic projection of the second active structure 621 on the substrate 10 is arranged to be located outside the orthographic projection of the first exposed portion 612 on the substrate 10, so as to protect the second active structure 621 by means of the first conductor portion 31. This design can further improve the manufacturing yield and reliability of the display panel 100.

[0119] In some embodiments, see Fig.12 , the second metal layer 50 is disposed on a side of the first metal layer 30 facing away from the substrate 10 .

[0120] The first metal layer 30 is provided with a first opening 32. The existence of the first opening 32 is likely to have an adverse effect on the film layer structure below in the subsequent process technology. On this basis, in the embodiment of the present application, the second metal layer 50 is arranged to be located on the side of the first metal layer 30 away from the substrate 10, that is, the first metal layer 30 is not the metal film layer farthest from the substrate 10 in the display panel 100. And the second conductor part 51 is arranged to overlap the orthographic projection of the substrate 10 with the orthographic projection of at least part of the first opening 32 on the substrate 10, so that the second conductor part 51 can protect the partial structures of the other multiple film layers located on the side of the first metal layer 30 facing the substrate 10 that are exposed relative to the first opening 32, thereby helping to further improve the manufacturing yield rate of the display panel 100.

[0121] The embodiments of the present application do not limit the specific positional relationship between the first metal layer 30 and the second metal layer 50, and the specific type of the signal transmitted by the first conductor portion 31 and the second conductor portion 51. Optionally, the second conductor portion 51 includes a first pad and a second pad that are insulated from each other, and the first pad and the second pad are respectively used to be fixed to the two electrodes of the light-emitting element. The first conductor portion 31 can be used to transmit a power supply voltage signal. On this basis, if the power supply voltage signal is a PVDD signal, the first pad and the second pad are both insulated from the first conductor portion 31. If the power supply voltage signal is a PVEE signal, one of the first pad and the second pad can be electrically connected to the first conductor portion 31, and the other can be insulated from the first conductor portion 31.

[0122] In some embodiments, see Fig.13The display panel 100 also includes a second active layer 62 disposed between the first metal layer 30 and the first active layer 61, the second active layer 62 includes a second active structure 621, the second active structure 621 includes a second exposed portion 622, the orthographic projection of the second exposed portion 622 on the substrate 10 is located within the first opening 32, and the orthographic projection of the second conductor portion 51 on the substrate 10 at least partially overlaps with the orthographic projection of the second exposed portion 622 on the substrate 10.

[0123] The first active layer 61, the second active layer 62, the first metal layer 30 and the second metal layer 50 are stacked in sequence in a direction gradually away from the substrate 10, and the second active structure 621 is a semiconductor structure located in the second active layer 62. In some cases, according to different actual layout requirements, the second active structure 621 may include a second exposed portion 622 corresponding to the position of the first opening 32.

[0124] In combination with the foregoing content, it can be known that the multiple first openings 32 include first-type openings 321 and second-type openings 322 of different sizes. Optionally, the orthographic projection of the first-type openings 321 on the substrate 10 can be located outside the orthographic projection of the second active structure 621 on the substrate 10, and the orthographic projection of the second-type openings 322 on the substrate 10 and the orthographic projection of the second active structure 621 on the substrate 10 have an overlapping area, and the partial structure of the second active structure 621 corresponding to the overlapping area is the second exposed portion 622.

[0125] Further, in the embodiment of the present application, the second metal layer 50 is located on the side of the second active layer 62 away from the substrate 10, and the orthographic projection of the second conductor portion 51 on the substrate 10 can overlap with the orthographic projection of the second exposed portion 622 on the substrate 10, so that the second conductor portion 51 can protect the second exposed portion 622, reduce the adverse effects of laser bonding and other processes on the second active structure 621, and improve the reliability of the second active structure 621 and the yield rate of the display panel 100. At the same time, the layout of the second active structure 621 can be not limited by the position of the first opening 32, which helps to reduce the layout difficulty of the second active structure 621, thereby improving the display effect and display accuracy.

[0126] In some embodiments, Fig.12 and Fig.13 As shown, the first opening 32 among the plurality of first openings 32 , which is arranged to at least partially overlap with the first active structure 611 , at least partially overlaps with the orthographic projection of the second conductor portion 51 on the substrate 10 .

[0127] The first opening 32 at least partially overlaps with the first active structure 611, that is, the first opening 32 overlaps with the orthographic projection of the first exposed portion 612 on the substrate 10. If there is no other shielding structure in the area corresponding to the first opening 32, then in the subsequent laser bonding process, the laser can easily pass through the first opening 32 to irradiate the first exposed portion 612, and there will be a risk of damage to the first active structure 611.

[0128] In view of this, in the embodiment of the present application, the first opening 32 corresponding to the first exposed portion 612 is overlapped with the orthographic projection of the second conductor portion 51 on the substrate 10, so that the second conductor portion 51 can shield the first exposed portion 612, reduce the damage to the first active structure 611 caused by subsequent processes such as laser bonding, and improve the reliability of the display panel 100.

[0129] In some optional embodiments, the display panel 100 also includes a second active layer 62 arranged between the first metal layer 30 and the first active layer 61, the second active layer 62 includes a second active structure 621, and a first opening 32 among the multiple first openings 32 that is at least partially overlapping with the second active structure 621 at least partially overlaps with the orthographic projection of the first conductor portion 31 on the substrate 10.

[0130] In some embodiments, see Fig.12 and Fig.14 The display panel 100 includes a second metal layer 50 on a side away from the substrate 10 . The second metal layer 50 includes a second conductor portion 51 . The second conductor portion 51 includes a third type of opening 52 and a fourth type of opening 53 . The size of the third type of opening 52 is larger than that of the fourth type of opening 53 .

[0131] Similar to the first metal layer 30, a plurality of opening structures may also be provided in the second metal layer 50, and the plurality of opening structures include a third type of opening 52 and a fourth type of opening 53 of different sizes. The "size" mentioned here refers to the orthographic projection area on the substrate 10, that is, the orthographic projection area of ​​the third type of opening 52 on the substrate 10 is larger than the orthographic projection area of ​​the fourth type of opening 53 on the substrate 10.

[0132] Furthermore, the third type of opening 52 refers to an opening whose corresponding orthographic projection area is greater than the second preset value, and the fourth type of opening 53 refers to an opening whose corresponding orthographic projection area is less than the second preset value. The specific size of the second preset value is not limited in the embodiment of the present application. Optionally, the first preset value and the second preset value are the same value. Among them, the number of the third type of openings 52 can be multiple, and the shapes and sizes of different third type openings 52 on the substrate 10 can be the same, or they can be different. Similarly, the number of the fourth type of openings 53 can be multiple, and the shapes and sizes of different fourth type openings 53 on the substrate 10 can be the same, or they can be different.

[0133] 6 , the present embodiment does not limit the positional relationship between the third type of openings 52 and the fourth type of openings 53 relative to the first type of openings 321 and the second type of openings 322. The orthographic projection of the third type of openings 52 on the substrate 10 can be located outside the orthographic projections of the first type of openings 321 and the second type of openings 322 on the substrate 10 at the same time, or the orthographic projection of the third type of openings 52 on the substrate 10 can also overlap with the orthographic projection of one of the first type of openings 321 and the second type of openings 322 on the substrate 10. The fourth type of openings 53 are the same, and the present embodiment will not be repeated.

[0134] In the embodiment of the present application, the second metal layer 50 is similar to the first metal layer 30 and also includes a plurality of opening structures of different sizes. On this basis, with the help of the third type of openings 52 and the fourth type of openings 53, it helps to further improve the gas release effect of the display panel 100, reduce the risk of water vapor and the like gathering on the side of the second metal layer 50 facing the substrate 10 and causing bulging, and improve the yield rate and reliability of the display panel 100.

[0135] In some embodiments, as shown in FIG. 4 and Fig.12 As shown, the pixel circuit P includes a low power supply terminal and a high power supply terminal, the low power supply terminal provides a low power supply voltage, the high power supply terminal provides a high power supply voltage, the first conductor portion 31 is used to transmit the low power supply voltage or the high power supply voltage, and the second conductor portion 51 is used to transmit the low power supply voltage or the high power supply voltage.

[0136] Taking the light-emitting element in the display panel 100 as a microled, and the light-emitting element includes a first electrode and a second electrode as an example, the pixel circuit P will be introduced in the embodiment of the present application. The pixel circuit P includes a pulse width modulation circuit P1 and a pulse amplitude modulation circuit P2, the pulse width modulation circuit P1 is configured to control the pulse width of the driving current provided to the light-emitting element based on the pulse width modulation data voltage, and the pulse amplitude modulation circuit P2 is configured to control the amplitude of the driving current provided to the light-emitting element based on the pulse amplitude modulation data voltage. Among them, the pulse width of the driving current can be understood as the duration of the driving current, and the amplitude of the driving current can be understood as the current value of the driving current.

[0137] Furthermore, if Figure 4a and Figure 4bAs shown, the pixel circuit P may include a pulse width modulation circuit P1 and a pulse amplitude modulation circuit P2, and the pixel circuit P generates a driving current under the control of the pulse amplitude modulation circuit P2 and the pulse width modulation circuit P1. The pulse amplitude modulation circuit P2 can be used to control the amplitude of the driving current, and the pulse width modulation circuit P1 can be used to adjust the pulse width of the voltage applied to the second electrode of the light-emitting element F. The pulse width modulation circuit P1 adjusts the actual emission period of the driving current applied to the light-emitting element F by adjusting the pulse width of the voltage applied to the second electrode of the light-emitting element F, that is, the pulse width modulation circuit P1 adjusts the driving current applied to the light-emitting element F; at the same time, the driving current applied to the light-emitting element F can be maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting element F, rather than adjusting the grayscale or brightness displayed by the light-emitting element F by adjusting the magnitude of the driving current applied to the light-emitting element F. Therefore, the pulse amplitude modulation circuit P2 can provide a driving current to the light-emitting element F so that the light-emitting element F is driven with the best luminous efficiency, and adjust the grayscale or brightness displayed by the light-emitting element F by adjusting the light-emitting duty cycle of the light-emitting element (that is, the emission period of the light-emitting element F) through the pulse width modulation circuit P1. Among them, the output end of the pulse width modulation circuit P1 can be directly connected to the control end of a driving transistor in the pulse amplitude modulation circuit P2, that is, the electrical signal output by the output end of the pulse width modulation circuit P1 is directly written to the control end of the driving transistor to adjust the driving current amplitude.

[0138] It should be noted that the figure only illustrates a connection method between the pulse width modulation circuit P1 and the pulse amplitude modulation circuit P2. Depending on the actual needs, the two circuits can also be connected in various other forms, which is not limited by the embodiments of the present application. In some other embodiments, the output end of the pulse width modulation circuit P1 can be connected to the pulse amplitude modulation circuit P2 through a first capacitor. Specifically, the pixel circuit P also includes a first capacitor, the first plate of the first capacitor is electrically connected to the output end of the pulse width modulation circuit P1, and the second plate of the first capacitor is electrically connected to the pulse amplitude modulation circuit P2. Among them, the second plate of the first capacitor is connected to the control end of the controlled transistor, and the controlled transistor can be a driving transistor that generates a driving current in the pulse amplitude modulation circuit P2, or it can be other transistors in the pulse amplitude modulation circuit P2 that are connected in series with the driving transistor.

[0139] Furthermore, the embodiments of the present application also do not limit the specific circuit configuration of the first driving circuit and the second driving circuit. Figure 4aAs shown, the pulse width modulation circuit P1 includes a first driving transistor M1, a first gate reset transistor M2, a first data writing transistor M3, a first compensation transistor M4, a first control transistor M6, a third control transistor M5 and a storage capacitor Cst. The third control transistor M5 is connected between the first power supply voltage PWM-vdd and the first electrode of the first driving transistor M1, and the first control transistor M6 is connected between the second electrode of the second driving transistor M1 and the output end of the first driving circuit. The first data writing transistor M3 is connected to the first electrode of the second driving transistor M1, the first compensation transistor M4 is connected to the second electrode and the control end of the second driving transistor M1, and the first gate reset transistor M2 is connected to the control end of the second driving transistor M1. The first plate of the storage capacitor Cst is connected to the control end of the first driving transistor M1, and the second plate of the storage capacitor Cst is connected to the sweep signal SWEEP. Among them, the control end of the first gate reset transistor M2 receives the first scanning signal PWM-S1, and the gates of the first data writing transistor M3 and the first compensation transistor M4 receive the second scanning signal PWM-S2. The gates of the first control transistor M6 and the third control transistor M5 receive the first light emission control signal PWM-EM.

[0140] The pulse amplitude modulation circuit P2 includes a second driving transistor M7, a second gate reset transistor M8, a second data writing transistor M9, a second compensation transistor M10, a second control transistor M11, a fourth control transistor M12, and an electrode reset transistor M13. The second control transistor M11 is connected between the second power supply voltage PAM-vdd and the first electrode of the second driving transistor M7, and the fourth control transistor M12 is connected between the second electrode of the second driving transistor M7 and the light emitting element F. The second driving transistor M7 is configured to generate a driving current under the control of the voltage at its control terminal. The second data writing transistor M9 is connected to the first electrode of the second driving transistor M7, the second compensation transistor M10 is connected to the second electrode and the control terminal of the second driving transistor M7, the second gate reset transistor M8 is connected to the control terminal of the second driving transistor M7, the electrode reset transistor M13 is connected to the second electrode of the light emitting element F, the fourth control transistor M12 is also connected to the second electrode of the light emitting element F, and the first electrode of the light emitting element F is connected to the third power supply voltage PVEE. The control end of the second gate reset transistor M8 receives the third scan signal PAM-S1; the control ends of the second data write transistor M9, the second compensation transistor M10 and the electrode reset transistor M13 receive the fourth scan signal PAM-S2. The gates of the second control transistor M11 and the fourth control transistor M12 receive the second light emission control signal PAM-EM.

[0141] Or Figure 4bAs shown, the pulse amplitude modulation circuit P2 and the pulse width modulation circuit P1 both include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light emitting control unit 114 / 124, a storage capacitor C1 / C2 and a driving transistor PAM-DR / PWM-DR (wherein the pulse amplitude modulation circuit P2 includes an initialization unit 111, a data writing unit 112, a threshold compensation unit 113, a light emitting control unit 114, a storage capacitor C2 and a driving transistor PAM-DR; the pulse width modulation circuit P1 includes an initialization unit 111 / 121, a data writing unit 112, a threshold compensation unit 113, a light emitting control unit 114, a storage capacitor C2 and a driving transistor PAM-DR; The initialization unit 121, the data writing unit 122, the threshold compensation unit 123, the light emitting control unit 124, the storage capacitor C2 and the driving transistor PWM-DR), the initialization unit 111 / 121 is electrically connected between the initialization signal VREF and the first node N11 / N12, and the initialization unit 111 / 121 is used to provide the initialization signal VREF to the first node N11 / N12 during the initialization stage (the initialization signal provided by the initialization signal end of the pulse amplitude modulation circuit P2 may have the same value as or different from the initialization signal of the pulse width modulation circuit P1). The data writing unit 112 / 122 is electrically connected between the data signal PAM-DATA / PWM-DATA and the first electrode of the driving transistor PAM-DR / PWM-DR, and the control end of the driving transistor PAM-DR / PWM-DR and the first electrode plate of the storage capacitor C2 / C1 are electrically connected to the first node N11 / N12; the data writing unit 112 / 122 is used to provide the data signal PAM-DATA / PWM-DATA to the first node N11 / N12 through the driving transistor PAM-DR / PWM-DR during the data writing phase. The threshold compensation unit 113 / 123 is electrically connected between the second electrode of the driving transistor PAM-DR / PWM-DR and the first node N11 / N12, and the threshold compensation unit 113 / 123 is used to compensate the threshold voltage of the driving transistor PAM-DR / PWM-DR to the first node N11 / N12.

[0142] In the pulse width modulation circuit P1, the second plate of the storage capacitor C1 is electrically connected to the sweep signal SWEEP, and the light-emitting control unit 124 is electrically connected between the first power supply voltage PWM-vdd and the first node N11 in the pulse amplitude modulation circuit P2; the light-emitting control unit 124 is used to control the driving transistor PWM-DR to generate a driving pulse during the light-emitting stage.

[0143] In the pulse amplitude modulation circuit P2, the second plate of the storage capacitor C2 is electrically connected to the second power signal PAM-vdd, and the light-emitting control unit 114 is electrically connected between the second power signal PAM-vdd and the light-emitting element F; the light-emitting control unit 114 is used to control the driving transistor PAM-DR to generate a driving current flowing into the light-emitting element F in the light-emitting stage, so as to drive the light-emitting element F to emit light.

[0144] On this basis, whether Figure 4a The circuit structure shown is still Figure 4b In the circuit structure shown, the low power supply voltage includes the third power supply voltage PVEE, and the high power supply voltage includes the power supply voltage PVDD, wherein the power supply voltage PVDD includes the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd. Further, the first conductor portion 31 and the second conductor portion 51 can be used to transmit one of the low power supply voltage and the high power supply voltage, wherein the first conductor portion 31 and the second conductor portion 51 can be used to transmit the same power supply voltage at the same time, in which case the first conductor portion 31 and the second conductor portion 51 can be connected to each other by vias, or the first conductor portion 31 and the second conductor portion 51 can be used to transmit different signals respectively, in which case the first conductor portion 31 and the second conductor portion 51 need to be insulated from each other.

[0145] In the embodiment of the present application, with respect to the specific circuit form of the pixel circuit P, in order to meet the luminous display needs of the display panel 100, the first conductor portion 31 and the second conductor portion 51 are both configured to transmit a low power supply voltage or a high power supply voltage, thereby meeting the transmission needs of the power supply voltage and realizing the luminous display function of the display panel 100.

[0146] In some embodiments, the first conductor portion 31 and the second conductor portion 51 transmit different signals.

[0147] In the embodiment of the present application, the first conductor portion 31 and the second conductor portion 51 transmit different signals, that is, one of the two is used to transmit the low power supply voltage, and the other is used to transmit the high power supply voltage. Among them, the first conductor portion 31 and the second conductor portion 51 may have an overlapping area in their orthographic projections on the substrate 10. On this basis, since the low power supply voltage and the high power supply voltage are both constant voltage potentials, even if the first conductor portion 31 and the second conductor portion 51 transmit different signals and there is an overlapping area, it is not easy to generate parasitic capacitance, which helps to improve the reliability of signal transmission in the first conductor portion 31 and the second conductor portion 51, and improve the display effect of the display panel 100.

[0148] In some embodiments, the pixel circuit P includes a pulse amplitude modulation circuit P2 and a pulse width modulation circuit P1, wherein the pulse amplitude modulation circuit P2 is configured to drive the amplitude of the current based on the modulation data, and the pulse width modulation circuit P1 is configured to control the pulse width of the driving circuit. The pulse modulation circuit includes a first power supply terminal, the first power supply terminal is used to provide a first power supply voltage PWM-vdd, and the first conductor portion 31 transmits the first power supply voltage PWM-vdd. The pulse amplitude modulation circuit P2 includes a second power supply terminal, the second power supply terminal is used to provide a second power supply voltage PAM-vdd, and the second conductor portion 51 transmits the second power supply voltage PAM-vdd.

[0149] In the embodiment of the present application, both the first conductor portion 31 and the second conductor portion 51 can be used to transmit the power supply voltage PVDD. The difference is that the first conductor portion 31 is used to transmit the first power supply voltage PWM-vdd, and the second conductor portion 51 is used to transmit the second power supply voltage PAM-vdd. On this basis, the first conductor portion 31 and the second conductor portion 51 still need to be insulated from each other, and because both are used to transmit constant voltage potential, even if the first metal layer 30 and the second metal layer 50 are two adjacent metal layers, and there is an overlapping area between the first conductor portion 31 and the second conductor portion 51, it is not easy to generate parasitic capacitance, which helps to improve the reliability of signal transmission inside the display panel 100, and improve the display effect and service life.

[0150] In some embodiments, see Fig.12 , Fig.14 and Fig.15 , in a direction perpendicular to the plane of the display panel 100 , the third type of opening 52 does not overlap with the pixel circuit P; and / or the fourth type of opening 53 at least partially overlaps with the pixel circuit P.

[0151] The third type of opening 52 does not overlap with the pixel circuit P, that is, the orthographic projection of the third type of opening 52 on the substrate 10 may be located outside the orthographic projection of each transistor M in the pixel circuit P on the substrate 10. The fourth type of opening 53 at least partially overlaps with the pixel circuit P, that is, the orthographic projection of the fourth type of opening 53 on the substrate 10 overlaps with the orthographic projection of the transistor M in the pixel circuit P on the substrate 10.

[0152] In the embodiment of the present application, the third type of opening 52 is an opening structure with a relatively large size. By arranging the third type of opening 52 and the pixel circuit P not to overlap, the exhaust function can be realized outside the area where the pixel circuit P is located, the gas release effect can be improved, and the risk of performance degradation caused by large-area exposure of the pixel circuit P to the third type of opening 52 can be reduced. As for the fourth type of opening 53, by overlapping at least part of the fourth type of opening 53 with the pixel circuit P, the exhaust requirement in the area where the pixel circuit P is located can be met with the help of the fourth type of opening 53. Since the fourth type of opening 53 is an opening structure with a relatively small size, the exposed area of ​​the pixel circuit P at the fourth type of opening 53 is relatively small, thereby reducing the probability of performance degradation of the pixel circuit P due to light irradiation and laser bonding, etc., which helps to improve the manufacturing yield and use effect of the display panel 100.

[0153] In some optional embodiments, in a direction perpendicular to the plane where the display panel 100 is located, the third type of opening 52 does not overlap with the pixel circuit P, and the fourth type of opening 53 at least partially overlaps with the pixel circuit P.

[0154] In some embodiments, the orthographic projection of the third type opening 52 on the substrate 10 is located between the orthographic projections of adjacent pixel circuits P on the substrate 10 .

[0155] In the embodiment of the present application, considering that at least some adjacent pixel circuits P may have a larger spacing dimension, the third type of openings 52 are correspondingly arranged between adjacent pixel openings. This design can, on the one hand, improve the gas release capability of the second conductor part 51 with the help of the third type of openings 52, and reduce the risk of the second conductor part 51 falling off. On the other hand, the need for the third type of openings 52 to avoid the pixel circuits P can be achieved, and the risk of performance and yield rate degradation caused by large-area exposure of the pixel circuits P to the third type of openings 52 can be reduced.

[0156] It should be noted that only one third type opening 52 may be provided between two adjacent pixel circuits P, or multiple third type openings 52 may be provided at the same time, and the embodiment of the present application is not limited to this. Optionally, multiple third type openings 52 may be provided between two pixel circuits P adjacently provided in the first direction X, and the multiple third type openings 52 are provided side by side and spaced apart along the second direction Y.

[0157] In some embodiments, a plurality of adjacent pixel circuits P together form a repeating circuit group C, and a plurality of repeating circuit groups C are repeatedly arranged; wherein adjacent repeating circuit groups C are arranged at intervals to form a spacing region J, and the third type opening 52 is located in the spacing region J.

[0158] In the embodiment of the present application, the spacing area J is an area between adjacent repeated circuit groups C and is not provided with pixel circuits P. Compared with the distance between two adjacent pixel circuits P in a single repeated circuit group C, the distance between two adjacent pixel circuits P in adjacent repeated circuit groups C is often larger. On this basis, by arranging the third type of opening 52 in the spacing area J, the third type of opening 52 is located between two adjacent pixel circuits P in adjacent repeated circuit groups C. In this way, the third type of opening 52 can avoid the pixel circuits P while having a larger size, thereby improving the gas release capability of the second conductor portion 51 and reducing the risk of film bulging and the second conductor portion 51 falling off.

[0159] In some embodiments, Fig.14 and Fig.15 As shown, the second conductor portion 51 includes a first pad 54 and a second pad 55 which are insulated from each other, and the second pad 55 is connected to the pixel circuit P. The first pad 54 includes a fourth type of opening 53 ; and / or the second pad 55 includes a fourth type of opening 53 .

[0160] In the embodiment of the present application, the first metal layer 30 is a metal film layer used to connect to the light-emitting element F. Specifically, the light-emitting element F may include a first electrode and a second electrode. The first solder pad 54 may be connected and fixed to the first electrode by laser bonding, and the second solder pad 55 may be connected and fixed to the second electrode by laser bonding.

[0161] The second pad 55 is connected to the pixel circuit P, that is, the second pad 55 is a pad structure required to realize the electrical connection between the pixel circuit P and the first electrode. On this basis, the first pad 54 is used to transmit the third power supply voltage PVEE.

[0162] The embodiment of the present application does not limit the size and shape of the first pad 54 and the second pad 55, as long as the first pad 54 and the second pad 55 are insulated from each other. For example, the first pad 54 can be a whole surface structure, and a via structure is provided in a part of the area, and the second pad 55 is accommodated in the via structure and is insulated from the first pad 54.

[0163] Furthermore, in the embodiment of the present application, since the fourth-type opening 53 is an opening structure with a smaller size, the fourth-type opening 53 can be set on the first solder pad 54 or on the second solder pad 55. That is, according to different actual needs, the fourth-type opening 53 can be selectively set on at least one of the first solder pad 54 and the second solder pad 55 to meet the exhaust needs at the second conductor portion 51, which has strong practicality and flexibility.

[0164] It should be noted that, in some optional embodiments, a fourth type of opening 53 may be provided on the first solder pad 54, and a fourth type of opening 53 may also be provided on the second solder pad 55. On this basis, the size, shape and other parameters of the fourth type of opening 53 located on the first solder pad 54 may be the same as the size, shape and other parameters of the fourth type of opening 53 located on the second solder pad 55, or they may be different, and the embodiments of the present application are not limited to this.

[0165] In some embodiments, the size of the fourth type opening 53 of the first pad 54 is greater than the size of the fourth type opening 53 of the second pad 55 .

[0166] The size of the fourth type opening 53 of the first solder pad 54 is the area size of the orthographic projection of the fourth type opening 53 located on the first solder pad 54 on the substrate 10. Similarly, the size of the fourth type opening 53 of the second solder pad 55 is the area size of the orthographic projection of the fourth type opening 53 located on the second solder pad 55 on the substrate 10.

[0167] In combination with the above content, it can be known that the first pad 54 can be a whole-surface structure, so the size of the first pad 54 itself is often larger than the size of the second pad 55 itself. On this basis, in view of the size difference between the first pad 54 and the second pad 55, the embodiment of the present application sets the size of the fourth type opening 53 of the first pad 54 to be larger than the size of the fourth type opening 53 of the second pad 55, that is, the pad structure with a large size is provided with a fourth type opening 53 of a larger size, and the pad structure with a small size is provided with a fourth type opening 53 of a smaller size. This design can meet the need to form the fourth type opening 53 on the first pad 54 and the second pad 55, while allowing the first pad 54 and the second pad 55 to still have a certain size, thereby meeting the need for the transmission of the corresponding signal. While meeting the exhaust need of the second conductor part 51, the display reliability of the display panel 100 is improved.

[0168] In some embodiments, Fig.14 As shown, the first pad 54 includes an annular fourth type opening 53, and the second pad 55 is located in the annular fourth type opening 53. The third type opening 52 is disposed on the first pad 54 and is spaced apart from the annular fourth type opening 53.

[0169] The first solder pad 54 and the second solder pad 55 need to be insulated from each other, that is, the two need to be designed to be separated from each other. On this basis, the embodiment of the present application forms a ring-shaped fourth-type opening 53 in the first solder pad 54, the second solder pad 55 is located inside the ring structure and the ring structure surrounds the second solder pad 55, and the first solder pad 54 is located outside the ring structure and surrounds the ring structure.

[0170] During the preparation of the second metal layer 50 , a fourth type of annular opening 53 may be formed by etching or other processes. In this case, the conductor structure inside the annular structure is the second pad 55 , and the conductor structure outside the annular structure is the first pad 54 .

[0171] It should be noted that, except for the annular fourth type opening 53, the shapes of other fourth type openings 53 are not limited in the present embodiment. Optionally, the orthographic projections of other fourth type openings 53 on the substrate 10 may be circular, square or other regular or irregular shapes.

[0172] Further, in the embodiment of the present application, considering that the first pad 54 may have a relatively large size, a third type of opening 52 may be provided on the first pad 54. On this basis, considering that the second pad 55 is relatively small in size and is used to connect to the pixel circuit P, the area near the annular fourth type of opening 53 is usually corresponding to the area where the pixel circuit P is located. Further, in order to reduce the adverse effects of the third type of opening 52 on the pixel circuit P, the embodiment of the present application also arranges the third type of opening 52 and the annular fourth type of opening 53 at intervals, thereby reducing the degree of overlap between the orthographic projection of the third type of opening 52 on the substrate 10 and the pixel circuit P on the substrate 10. This design can reduce the adverse effects of the third type of opening 52 on the pixel circuit P while improving the corresponding exhaust capacity of the second conductor portion 51, thereby improving the performance reliability of the pixel circuit P and the manufacturing yield of the display panel 100.

[0173] In some embodiments, as shown in FIG. 6, Fig.12 , Fig.14 as well as Fig.15 As shown, the plurality of first openings 32 include first-type openings 321 and second-type openings 322, and the size of the first-type openings 321 is larger than the size of the second-type openings 322. On a plane perpendicular to the display panel 100, the first-type openings 321 and the pixel circuits P do not overlap, and at least part of the second-type openings 322 overlap with the pixel circuits P. In particular, on a plane perpendicular to the display panel 100, at least part of the second-type openings 322 and the fourth-type openings 53 do not overlap, and / or at least part of the first-type openings 321 and the third-type openings 52 do not overlap.

[0174] The first conductor portion 31 includes a first type of opening 321 and a second type of opening 322 of different sizes, and the second conductor portion 51 includes a third type of opening 52 and a fourth type of opening 53 of different sizes. The first type of opening 321 and the third type of opening 52 are not overlapped with the pixel circuit P, while the second type of opening 322 and the fourth type of opening 53 are at least partially overlapped with the pixel circuit P.

[0175] On this basis, in the embodiment of the present application, the second type of opening 322 and the fourth type of opening 53 do not overlap, that is, the second type of opening 322 and the fourth type of opening 53 are not arranged correspondingly, and the second type of opening 322 and the fourth type of opening 53 are arranged in a staggered position in the orthographic projection of the substrate 10. On this basis, in the area where at least part of the second type of opening 322 is located, there will be no fourth type of opening 53, and there will be a corresponding conductor structure in the second conductor part 51. Similarly, in the area where at least part of the fourth type of opening 53 is located, there will be no second type of opening 322, and there will be a corresponding conductor structure in the first conductor part 31.

[0176] In this way, with the joint design of the first conductor part 31 and the second conductor part 51, the risk of large-area structure exposure in other film layers of the first metal layer 30 and the second metal layer 50 facing the substrate 10 due to the corresponding arrangement of the second type of opening 322 and the fourth type of opening 53 can be reduced, thereby reducing the adverse effects of processes such as laser bonding on other film layers of the first metal layer 30 and the second metal layer 50 facing the substrate 10, and improving the yield rate and reliability of the display panel 100. Among them, the relationship between the first type of opening 321 and the third type of opening 52 is the same, and the embodiment of the present application will not be repeated.

[0177] It should be noted that the embodiment of the present application does not limit the positional relationship between the first type of opening 321 and the fourth type of opening 53. For example, the first type of opening 321 and the fourth type of opening 53 can be arranged to overlap each other, or the two can also be arranged to be staggered with each other. Similarly, the embodiment of the present application does not limit the positional relationship between the second type of opening 322 and the third type of opening 52.

[0178] In addition, for different regions of the display panel 100, the second type of opening 322 and the fourth type of opening 53 may not overlap in some regions, but may overlap in other regions. Alternatively, in each region of the display panel 100, the second type of opening 322 and the fourth type of opening 53 may not overlap.

[0179] In some optional embodiments, at the area where the pixel circuit P is located, the orthographic projection of the fourth type of opening 53 on the substrate 10 is arranged not to overlap with the second type of opening 322, and the third type of opening 52 and the first type of opening 321 are both located outside the area where the pixel circuit P is located. This design enables the pixel circuit P to be covered by the conductor structure of at least one of the first conductor portion 31 and the second conductor portion 51 at the area where the pixel circuit P is located, thereby reducing the adverse effects of processes such as laser bonding on the pixel circuit P and improving the reliability of the pixel circuit P.

[0180] For the first type of openings 321 and the third type of openings 52, in some optional embodiments, the third type of openings 52 and the first type of openings 321 are arranged not to overlap in the area between the corresponding adjacent pixel circuits P. This design enables at least a portion of the third type of openings 52 and the first type of openings 321 in the area corresponding to the first type of openings 321 to be shielded and covered by the conductor structures in the first conductor portion 31 and the second conductor portion 51, respectively, thereby reducing the adverse effects of processes such as laser bonding on other film layer structures of the first metal layer 30 and the second metal layer 50 facing the substrate 10, and improving the yield rate and reliability of the display panel 100.

[0181] In some embodiments, the orthographic projections of some second-type openings 322 on the substrate 10 are located between the orthographic projections of adjacent pixel circuits P on the substrate 10, and the orthographic projections of multiple second-type openings 322 on the substrate 10 at least partially overlap with the orthographic projections of the same third-type opening 52 on the substrate 10; and / or, the orthographic projections of some fourth-type openings 53 on the substrate 10 are located between the orthographic projections of adjacent pixel circuits P on the substrate 10, and the orthographic projections of multiple fourth-type openings 53 on the substrate 10 at least partially overlap with the orthographic projections of the same first-type opening 321 on the substrate 10.

[0182] Taking the third type of opening 52 as an example, the third type of opening 52 is not set corresponding to the first type of opening 321, but corresponds to multiple second type openings 322. Therefore, water vapor and the like can move to the third type of opening 52 through multiple second type openings 322 in sequence, and be released from the third type opening 52, thereby providing an exhaust path parallel to the thickness direction Z for the release of gas, reducing the difficulty of gas release, improving the exhaust reliability of the display panel 100, reducing the risk of bulging or falling off of part of the film layer, and improving the yield rate.

[0183] In addition, since the third type of opening 52 is a large-sized opening and the second type of opening 322 is a small-sized opening, in the area where the third type of opening 52 is located, the partial conductor structure between the adjacent second type of openings 322 can cover and protect the first metal layer 30 and other film layers of the second metal layer 50 facing the substrate 10, thereby reducing the adverse effects of processes such as laser bonding on the first metal layer 30 and other film layer structures of the second metal layer 50 facing the substrate 10, and improving the yield rate of the display panel 100. The first type of opening 321 is the same, and the embodiments of the present application will not be repeated.

[0184] In summary, in the embodiment of the present application, by arranging the third type of opening 52 and the first type of opening 321 not to overlap, and arranging the third type of opening 52 and the plurality of second type of openings 322 to overlap, and arranging the first type of opening 321 and the plurality of fourth type of openings 53 to overlap, there is a small-sized opening structure at the location of the third type of opening 52 and the first type of opening 321 to improve the exhaust effect of the display panel 100, and there is a conductor structure for covering and protecting the first metal layer 30 and other film layers of the second metal layer 50 facing the substrate 10, thereby helping to further improve the yield rate and reliability of use of the display panel 100.

[0185] In some embodiments, at a region corresponding to between adjacent pixel circuits P, an orthographic projection of the second type opening 322 on the substrate 10 at least partially overlaps an orthographic projection of the fourth type opening 53 on the substrate 10 .

[0186] Considering that the area between adjacent pixel circuits P is an area where no pixel circuit P exists, even if the metal layer has an opening structure in this area, it is not easy to have an adverse effect on the pixel circuit P. In view of this, in the embodiment of the present application, the second type of opening 322 with a smaller size can be arranged to at least partially overlap with the fourth type of opening 53 in the area between adjacent pixel circuits P, so as to help improve the exhaust effect of the display panel 100 without affecting the performance of the pixel circuit P.

[0187] In some embodiments, Figure 1 As shown, the first conductor portion 31 includes a first sub-portion 311 and a second sub-portion 312 adjacently disposed on both sides of the first opening 32 along a first direction X, the first sub-portion 311 and the second sub-portion 312 transmit the same signal, and the first direction X is parallel to the plane where the substrate 10 is located.

[0188] The first sub-section 311 and the second sub-section 312 are conductor structures of the first conductor section 31 located on different sides of the first opening 32 along the first direction X. The first sub-section 311 and the second sub-section 312 transmit the same signal, that is, both are used to transmit the same potential voltage. The specific relationship between the first sub-section 311 and the second sub-section 312 is not limited in the embodiment of the present application. Exemplarily, the first sub-section 311 and the second sub-section 312 can be connected as one piece through other conductor structures in the first conductor section 31, or both can be respectively connected to the same conductor structure in other film layers of the first metal layer 30 facing or away from the substrate 10, or both can be electrically connected through other conductor structures located in the first metal layer 30 to transmit the same signal.

[0189] In the embodiment of the present application, the first sub-section 311 and the second sub-section 312 in the first conductor section 31 are arranged on both sides of the first opening 32, and the first sub-section 311 and the second sub-section 312 transmit the same signal, so that more conductor structures in the first conductor section 31 can transmit the same signal, thereby increasing the size of the conductor structure in the first conductor section 31 used to transmit the same signal, which helps to reduce the resistance and load of the first conductor section 31 and improve the reliability of signal transmission.

[0190] In some embodiments, see Figure 1 and Fig.16 The first sub-section 311 and the second sub-section 312 are connected and arranged as a whole.

[0191] In the embodiment of the present application, the first sub-section 311 and the second sub-section 312 can be connected and integrated by the connecting section 313. The connecting section 313 is a conductor structure of the first conductor section 31 arranged on at least one side of the first opening 32 along the second direction Y, and the two ends of the connecting section 313 in the first direction X are respectively connected to the first sub-section 311 and the second sub-section 312. This design can make the first conductor section 31 present a whole surface or block structure with the first opening 32, which helps to reduce the difficulty of preparing the first conductor section 31, reduce the resistance and load of the first conductor section 31, and improve the reliability of signal transmission.

[0192] In some embodiments, Figure 1 and Fig.16 As shown, the first metal layer 30 further includes a conductive portion 33 extending along the first direction X. The conductive portion 33 has an orthographic projection on the substrate 10 located within the first opening 32 , and the conductive portion 33 connects the first sub-portion 311 and the second sub-portion 312 .

[0193] In addition to the first conductor part 31, the first metal layer 30 further includes a conductive part 33, which may be made of the same material as the first conductor part 31, or may be made of a different material from the first conductor part 31. Further, optionally, the first conductor part 31 and the conductive part 33 may be made of the same material and formed together in the same preparation process.

[0194] In the embodiment of the present application, the conducting portion 33 is correspondingly located in the first opening 32, and the two ends of the conducting portion 33 in the first direction X can be respectively connected to the first sub-portion 311 and the second sub-portion 312. In combination with the above content, it can be known that the first sub-portion 311 and the second sub-portion 312 are connected and arranged as one body. On this basis, the existence of the conducting portion 33 can further help realize the signal transmission between the first sub-portion 311 and the second sub-portion 312, and can also further reduce the resistance and load of the first conductor portion 31, thereby improving the reliability of signal transmission.

[0195] In some embodiments, the pixel circuit P includes a pulse amplitude modulation circuit P2 and a pulse width modulation circuit P1, the pulse amplitude modulation circuit P2 is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit P1 is configured to control the pulse width of the driving current; the pulse width modulation circuit P1 includes a first power supply terminal, the first power supply terminal is used to provide a first power supply voltage, and the first conductor portion 31 transmits the first power supply voltage PWM-vdd, and / or the pulse amplitude modulation circuit P2 includes a second power supply terminal PWM-vdd, the second power supply terminal is used to provide a second power supply voltage PAM-vdd, and the first conductor portion 31 transmits the second power supply voltage PAM-vdd.

[0196] The power supply voltage PVDD includes a first power supply voltage PWM-vdd and a second power supply voltage PAM-vdd. Further, according to different actual needs, the first conductor portion 31 in the first metal layer 30 can be used to transmit one of the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd. Of course, the first conductor portion 31 may include different conductor structures that are insulated from each other, and the different conductor structures are used to transmit the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd respectively.

[0197] In the embodiment of the present application, with respect to the specific circuit form of the pixel circuit P, in order to meet the luminous display needs of the display panel 100, the first conductor portion 31 is configured to transmit at least one of the first power supply voltage PWM-vdd and the second power supply voltage PAM-vdd, thereby meeting the transmission needs of the power supply voltage PVDD and realizing the luminous display function of the display panel 100.

[0198] Second, see Fig.17 An embodiment of the present application provides a display device 200, and the display device 200 includes a display panel in any of the aforementioned embodiments.

[0199] It should be noted that the display device 200 provided in the embodiment of the present application has the beneficial effects of the display panel in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the display panel for details, and the embodiment of the present application will not be repeated.

[0200] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0201] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel circuits, each of which includes a plurality of transistors; the display panel further includes: substrate; A first organic layer is disposed on one side of the substrate; A first metal layer is disposed on a side of the first organic layer away from the substrate, the first metal layer comprises a first conductor portion, and the first conductor portion at least partially overlaps with an orthographic projection of at least one transistor in the pixel circuit on the substrate; The first conductor portion includes a first opening, and an orthographic projection of the first opening on the substrate at least partially overlaps with an orthographic projection of the first organic layer on the substrate.

2. The display panel according to claim 1, characterized in that: An orthographic projection of at least a portion of the first opening on the substrate at least partially overlaps with an orthographic projection of the transistor in the pixel circuit on the substrate; and / or, At least part of the first opening is located outside the orthographic projection of each transistor in the pixel circuit on the substrate.

3. The display panel according to claim 2, characterized in that: The plurality of first openings include first-type openings and second-type openings, and the size of the first-type openings is larger than the size of the second-type openings; 4. The display panel according to claim 3, characterized in that: On a plane perpendicular to the display panel, the first type of opening and the pixel circuit do not overlap; On a plane perpendicular to the display panel, at least a portion of the second-type openings overlaps with the pixel circuit.

5. The display panel according to claim 3, characterized in that: The orthographic projection of the first type of opening on the substrate is located between the orthographic projections of adjacent pixel circuits on the substrate.

6. The display panel according to claim 3, characterized in that: A plurality of adjacently arranged pixel circuits together form a repeated circuit group, and a plurality of the repeated circuit groups are repeatedly arranged; Wherein, adjacent repeated circuit groups are spaced to form a spacing area, and the first type of opening is located in the spacing area.

7. The display panel according to claim 3, characterized in that: It also includes a shift register unit, and the shift register unit is located between adjacent pixel circuits; The orthographic projection of the shift register unit on the substrate at least partially overlaps with the orthographic projection of the first type of opening on the substrate; and / or the orthographic projection of the shift register unit on the substrate at least partially overlaps with the orthographic projection of the second type of opening on the substrate.

8. The display panel according to claim 1, characterized in that: The first organic layer includes an exhaust hole, and the first opening at least partially overlaps with an orthographic projection of the exhaust hole on the substrate.

9. The display panel according to claim 8, characterized in that: The orthographic projection of the exhaust hole on the substrate is located within the orthographic projection of the first opening on the substrate, and the orthographic projection area of ​​the exhaust hole on the substrate is smaller than the orthographic projection area of ​​the first opening on the substrate.

10. The display panel according to claim 8, characterized in that: It also includes a first insulating layer disposed on a side of the first metal layer away from the substrate, and a portion of the structure in the first insulating layer is located in the first opening and the exhaust hole.

11. The display panel according to claim 10, characterized in that: The first insulating layer is disposed in contact with a side wall of the first conductor portion facing the first opening.

12. The display panel according to claim 8, characterized in that: It also includes a second insulating layer disposed between the first metal layer and the first organic layer, the second insulating layer includes a second opening, and the second opening and the exhaust hole are overlapped in the orthographic projection of the substrate.

13. The display panel according to claim 12, characterized in that: The second insulating layer includes an inorganic material.

14. The display panel according to claim 1, characterized in that: It also includes a second metal layer disposed on one side of the substrate, the second metal layer includes a second conductor portion, and the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of at least part of the first opening on the substrate.

15. The display panel according to claim 14, characterized in that: It also includes a first active layer arranged on the side of the second metal layer facing the substrate, the first active layer includes a first active structure, the first active structure includes a first exposed portion, the orthographic projection of the first exposed portion on the substrate is located within the first opening, and the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the first exposed portion on the substrate.

16. The display panel according to claim 15, characterized in that: The second metal layer is located on the side of the first metal layer facing the substrate. The display panel also includes a second active layer arranged between the second metal layer and the first metal layer. The second active layer includes a second active structure. The orthographic projection of the second active structure on the substrate is located outside the orthographic projection of the first opening on the substrate.

17. The display panel according to claim 15, characterized in that: The second metal layer is disposed on a side of the first metal layer facing away from the substrate.

18. The display panel according to claim 17, characterized in that: It also includes a second active layer arranged between the first metal layer and the first active layer, the second active layer includes a second active structure, the second active structure includes a second exposed portion, the orthographic projection of the second exposed portion on the substrate is located within the first opening, and the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the second exposed portion on the substrate.

19. The display panel according to claim 17, characterized in that: The first opening among the plurality of first openings, which is arranged to at least partially overlap with the first active structure, at least partially overlaps with an orthographic projection of the second conductor portion on the substrate.

20. The display panel according to claim 1, characterized in that: It also includes a second metal layer arranged on the side of the first metal layer away from the substrate, the second metal layer includes a second conductor part, the second conductor part includes a third type of opening and a fourth type of opening, and the size of the third type of opening is larger than the size of the fourth type of opening.

21. The display panel according to claim 20, characterized in that: The pixel circuit includes a low power supply terminal and a high power supply terminal, the low power supply terminal provides a low power supply voltage, the high power supply terminal provides a high power supply voltage, the first conductor part is used to transmit the low power supply voltage or the high power supply voltage, and the second conductor part is used to transmit the low power supply voltage or the high power supply voltage.

22. The display panel according to claim 21, characterized in that: The first conductor portion and the second conductor portion transmit different signals.

23. The display panel according to claim 22, characterized in that: The pixel circuit includes a pulse amplitude modulation circuit and a pulse width modulation circuit, the pulse amplitude modulation circuit is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit is configured to control the pulse width of the driving current; The pulse width modulation circuit comprises a first power supply terminal, the first power supply terminal is used to provide a first power supply voltage, and the first conductor part transmits the first power supply voltage; The pulse amplitude modulation circuit includes a second power supply terminal, the second power supply terminal is used to provide a second power supply voltage, and the second conductor part transmits the second power supply voltage.

24. The display panel according to claim 20, characterized in that: In a direction perpendicular to the plane where the display panel is located, the third type of opening does not overlap with the pixel circuit, and / or the fourth type of opening at least partially overlaps with the pixel circuit.

25. The display panel according to claim 24, characterized in that: The orthographic projection of the third type of opening on the substrate is located between the orthographic projections of adjacent pixel circuits on the substrate.

26. The display panel according to claim 25, characterized in that: The second conductor portion includes a first pad and a second pad that are insulated, and the second pad is connected to the pixel circuit; The first pad includes the fourth type of opening, and / or the second pad includes the fourth type of opening.

27. The display panel according to claim 26, characterized in that: The size of the fourth type opening of the first pad is larger than the size of the fourth type opening of the second pad.

28. The display panel according to claim 27, characterized in that: The first pad includes a ring-shaped fourth-type opening, and the second pad is located in the ring-shaped fourth-type opening; The third type of opening is arranged on the first pad and is spaced apart from the annular fourth type of opening.

29. The display panel according to claim 20, characterized in that: The plurality of first openings include first-type openings and second-type openings, and the size of the first-type openings is larger than the size of the second-type openings; On a plane perpendicular to the display panel, the first type of opening and the pixel circuit do not overlap; On a plane perpendicular to the display panel, at least a portion of the second-type openings overlaps with the pixel circuit; On a plane perpendicular to the display panel, at least part of the second type of openings and the fourth type of openings do not overlap, and / or at least part of the first type of openings and the third type of openings do not overlap.

30. The display panel according to claim 29, characterized in that: The orthographic projections of some of the second-type openings on the substrate are located between the orthographic projections of adjacent pixel circuits on the substrate, and the orthographic projections of a plurality of the second-type openings on the substrate at least partially overlap with the orthographic projection of the same third-type opening on the substrate; and / or, The orthographic projections of some of the fourth-type openings on the substrate are located between the orthographic projections of adjacent pixel circuits on the substrate, and the orthographic projections of multiple fourth-type openings on the substrate at least partially overlap with the orthographic projection of the same first-type opening on the substrate.

31. The display panel according to claim 29, characterized in that: In a region corresponding to between adjacent pixel circuits, an orthographic projection of the second type of opening on the substrate at least partially overlaps with an orthographic projection of the fourth type of opening on the substrate.

32. The display panel according to claim 1, characterized in that: The first conductor portion includes a first sub-portion and a second sub-portion adjacently disposed on both sides of the first opening along a first direction, the first sub-portion and the second sub-portion transmit the same signal, and the first direction is parallel to the plane where the substrate is located.

33. The display panel according to claim 32, characterized in that: The first sub-section and the second sub-section are connected and arranged as one body.

34. The display panel according to claim 33, characterized in that: The first metal layer further includes a conductive portion extending along the first direction, an orthographic projection of the conductive portion on the substrate is located within the first opening, and the conductive portion connects the first sub-portion and the second sub-portion.

35. The display panel according to claim 1, characterized in that: The pixel circuit includes a pulse amplitude modulation circuit and a pulse width modulation circuit, the pulse amplitude modulation circuit is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit is configured to control the pulse width of the driving current; The pulse width modulation circuit includes a first power supply terminal, the first power supply terminal is used to provide a first power supply voltage, and the first conductor part transmits the first power supply voltage, and / or the pulse amplitude modulation circuit includes a second power supply terminal, the second power supply terminal is used to provide a second power supply voltage, and the first conductor part transmits the second power supply voltage.

36. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 35.

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