Host exception handling method and device and electronic equipment

Abstract

The invention discloses a host exception handling method and device and electronic equipment, and relates to the technical field of communication, and the method comprises the following steps: obtaining first operation information of a first host, second operation information of a second host and third operation information of a slave, and then according to the first operation information and the second operation information, executing the first operation information and the second operation information; and the third operation information verifies whether the first host is abnormal or not, and if the first host is verified to be abnormal, the reset operation of the first host is executed. By means of the method, whether the first host is abnormal or not can be accurately verified, so that when the first host is abnormal, the abnormity can be processed in time, and the situation that the whole computing system is out of control due to the abnormity of the host is prevented.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a host exception processing method, device and electronic equipment. Background Art

[0002] Current communication networks usually use a master-slave dual-host control mechanism or a one-master-multiple-slave host control mechanism to manage computing systems, where the master host is used to control the entire computing system, and the standby host is on standby as a hot standby, where hot standby means that the standby host is in operation. When multiple hosts in a communication network are started, each host decides on the master and standby hosts based on its own operating status and startup sequence. For example, if host A starts before host B, and the self-test status of host A is normal, host A becomes the master host and host B becomes the standby host.

[0003] In order to maintain the normal operation of the computing system, if the main host is removed or reset due to some factors, the main state is automatically released. At this time, the backup host automatically seizes the main state and maintains it. The removal or reset of the backup host will not affect the main and backup states. In the related art, when the main host is abnormal, there are generally two main and backup arbitration mechanisms:

[0004] The master-slave mechanism is that the master host is only controlled by its own self-test. Once it detects an abnormality, it will reset itself and release control. At this time, the standby host will automatically become the master host and take over the computing system. In order to avoid abnormal reset of the master host due to abnormality of the standby host itself, this mechanism sets that the standby host cannot reset the master host.

[0005] The backup host takes over the master mechanism. If the backup host detects that the main host is abnormal, it will reset the main host and actively obtain control of the computing system without waiting for the main host to release control.

[0006] In the above-mentioned master-to-standby mechanism, when the master host has some functional abnormalities and has not detected its own abnormalities, for example, when the master host cannot communicate with all slaves, has functional abnormalities, and has not detected its own abnormalities, the standby host can communicate normally with the slaves, but cannot actively seize the master control, which will cause the entire computing system to function abnormally. Similarly, in the above-mentioned standby-to-master mechanism, although the standby host can detect the abnormality of the master host and reset the abnormal master host, when the standby host itself operates abnormally, for example, the device hardware is damaged and an error signal is generated, it may cause the standby host to mistakenly reset the master host and obtain control of the computing system, thereby causing the entire computing system to function abnormally. Summary of the invention

[0007] The present application provides a host exception processing method, device and electronic device, which can solve the problem of abnormal function of the entire computing system caused by abnormality of the main host and / or backup host in the current computing system.

[0008] In a first aspect, the present application provides a host exception handling method, the method comprising:

[0009] Acquire first operation information of a first host, second operation information of a second host, and third operation information of a slave, wherein the first host manages the second host and the slave, and the second host is connected to the slave;

[0010] Verifying whether the first host is abnormal according to the first operation information, the second operation information, and the third operation information;

[0011] If it is verified that the first host is abnormal, a reset operation of the first host is performed.

[0012] Through the above method, based on the first operating information of the first host, the second operating information of the second host, and the third operating information of the slave, it is possible to accurately verify whether the first host has an abnormality, so that when an abnormality occurs in the first host, the abnormality can be handled in time to prevent the entire computing system from being disconnected due to the host abnormality.

[0013] In a possible design, verifying that an abnormality occurs in the first host according to the first operation information, the second operation information, and the third operation information includes:

[0014] If there is abnormal information in the first operation information, then verifying that the first host is abnormal; or

[0015] The first operating information is compared with the third operating information. If the comparison shows that there is no abnormal information in the first operating information, but there is abnormal information in the third operating information, and when the second operating information is compared with the third operating information, it is found that there is no abnormal information in both the second operating information and the third operating information, then it is verified that an abnormality has occurred in the first host.

[0016] Through the above method, whether the first host is abnormal can be accurately checked according to the first operation information of the first host, the second operation information of the second host, and the third operation information of the slave.

[0017] In a possible design, the first operation information includes communication status information between the first host and the slave;

[0018] The second operation information includes communication status information between the second host and the slave;

[0019] The third operation information includes communication status information between the slave and the first host, and communication status information between the slave and the second host.

[0020] Through the above method, comprehensive first operation information of the first host, second operation information of the second host, and third operation information of the slave are obtained, and then whether the first host is abnormal can be accurately checked based on these operation information.

[0021] In a possible design, performing a reset operation on the first host includes:

[0022] Opening a reset path of the first host;

[0023] When the reset path is opened and a reset signal sent by the second host is received, a reset operation of the first host is performed.

[0024] By using the above method, when the reset path of the first host is opened and the first host receives a reset signal, the reset operation of the first host is executed, which can not only handle the host abnormality in time, but also prevent the first host from being reset by mistake through two reset conditions.

[0025] In one possible design, the method further includes:

[0026] If it is verified that the first host has no abnormality, controlling the first host to shield the reset signal sent by the second host; or

[0027] If it is detected according to the second operation information that the second host is abnormal, the reset signal sent by the second host is shielded.

[0028] By means of the above method, when the first host does not have an abnormality or the second host has an abnormality, the second host is prohibited from resetting the first host, thereby ensuring the normal operation of the computing system.

[0029] In a second aspect, the present application provides a host exception processing device, the device comprising:

[0030] an acquisition module, configured to acquire first operation information of a first host, second operation information of a second host, and third operation information of a slave, wherein the first host manages the second host and the slave, and the second host is connected to the slave;

[0031] a verification module, configured to verify whether the first host is abnormal according to the first operation information, the second operation information, and the third operation information;

[0032] The execution module is used to execute a reset operation of the first host if it is verified that the first host is abnormal.

[0033] In a possible design, the verification module is specifically used to:

[0034] If there is abnormal information in the first operation information, then verifying that the first host is abnormal; or

[0035] The first operating information is compared with the third operating information. If the comparison shows that there is no abnormal information in the first operating information, but there is abnormal information in the third operating information, and when the second operating information is compared with the third operating information, it is found that there is no abnormal information in both the second operating information and the third operating information, then it is verified that an abnormality has occurred in the first host.

[0036] In a possible design, the first operation information includes communication status information between the first host and the slave;

[0037] The second operation information includes communication status information between the second host and the slave;

[0038] The third operation information includes communication status information between the slave and the first host, and communication status information between the slave and the second host.

[0039] In a possible design, the execution module is specifically used to:

[0040] Opening a reset path of the first host;

[0041] When the reset path is opened and a reset signal sent by the second host is received, a reset operation of the first host is performed.

[0042] In one possible design, the device further includes:

[0043] a shielding module, configured to shield the reset signal sent by the second host if it is verified that the first host has no abnormality; or

[0044] If it is detected according to the second operation information that the second host is abnormal, the reset signal sent by the second host is shielded.

[0045] In a third aspect, the present application provides an electronic device, including:

[0046] Memory, used to store computer programs;

[0047] The processor is used to implement the above-mentioned host exception handling method steps when executing the computer program stored in the memory.

[0048] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned host exception handling method steps are implemented.

[0049] Based on the host exception handling method provided by the present application, whether the first host has an exception can be accurately verified according to the first operation information of the first host, the second operation information of the second host, and the third operation information of the slave, so that when the first host has an exception, the exception can be handled in time to prevent the entire computing system from being disconnected due to the host exception. At the same time, when the first host has no exception, the second host is prohibited from resetting the first host to ensure the normal operation of the computing system.

[0050] The technical effects that can be achieved in each of the above-mentioned second to fourth aspects and each of the above-mentioned aspects refer to the technical effects that can be achieved in the above-mentioned first aspect or various possible schemes in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic diagram of an application scenario applicable to the embodiments of the present application;

[0052] Figure 2 A flowchart of a host exception handling method provided in an embodiment of the present application;

[0053] Figure 3 A logical diagram of host exception processing provided in an embodiment of the present application;

[0054] Figure 4 A schematic diagram of the structure of a host exception handling device provided in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of the structure of another host exception handling device provided in an embodiment of the present application;

[0056] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" is understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, and A and B exist, and B exists alone. A is connected to B, which can represent: A is directly connected to B and A is connected to B through C. In addition, in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0058] In order to facilitate understanding by those skilled in the art, the technical terms involved in the embodiments of the present application are first explained.

[0059] (1) The heartbeat mechanism means that the first host sends a custom structure, such as a heartbeat packet or a heartbeat frame, to the second host and the slave at regular intervals, so that the second host and the slave can determine that the first host is online to ensure the effectiveness of communication.

[0060] (2) The service counting mechanism refers to determining the communication status between the first host and the slave, the second host and the slave, the slave and the first host, and the slave and the second host by using the values ​​0 and 1. The value 0 represents abnormal communication, and the value 1 represents normal communication.

[0061] The following is a brief introduction to the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In specific implementation, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.

[0062] Figure 1 Schematic diagram of an application scenario applicable to the embodiment of the present application. The scenario mainly includes a first host 101, a second host 102, and a slave 103. Among them, the first host 101 manages the second host 102 and the slave 103, the second host 102 is connected to the slave 103, the number of the second hosts 102 is N, N is an integer greater than 0, of course, the number of slaves can also be 1 or more.

[0063] Exemplarily, the first host 101 includes a control system 101a and a microcontroller unit (MCU) 101b. The control system 101a includes a central processing unit (CPU), a memory and other basic startup and operation components, and has the functions of master-slave election, master-slave status recording, access and management of the second host 102 and the slave 103; the MCU 101b is used to receive the first operation information of the first host 101, obtain the second operation information of the second host 102 and the third operation information of the slave 103, and open the reset path of the first host 101.

[0064] Furthermore, the control system 101a periodically reports the first operation information of the first host 101 to the MCU 101b, wherein the periodic reporting may be every 5 seconds or every 10 seconds, and the specific value depends on the situation and is not specifically limited here. At the same time, the MCU 101b will also obtain the second operation information of the second host 102 and the third operation information of the slave 103 according to the same period, so that the MCU 101b can detect whether the first host 101 is abnormal based on these operation information.

[0065] Exemplarily, the second host 102 includes a control system 102a and an MCU 102b, and the first host 101 and the second host 102 can be connected through an internal interface in the control system 101a and an internal interface in the control system 102a, or directly connected through MCU 101b and MCU 102b. The control system 102a periodically reports the second operation information of the second host 102 to the MCU 102b, and the MCU 102b also obtains the first operation information of the first host 101 and the third operation information of the slave 103 according to the same cycle.

[0066] Exemplarily, the slave 103 includes a control system 103a and an MCU 103b, and the control system 103a periodically reports the third operation information of the slave to the MCU 103b.

[0067] In order to solve the problem of abnormal functions of the entire computing system caused by abnormalities of the main host and / or the backup host in the current computing system, based on the above-mentioned application scenario, a host exception handling method provided in an embodiment of the present application can accurately verify whether the first host has an abnormality according to the first operating information of the first host, the second operating information of the second host, and the third operating information of the slave, so that when an abnormality occurs in the first host, the abnormality can be handled in time to prevent the entire computing system from being disconnected due to the host abnormality. At the same time, when the first host does not have an abnormality, the second host is prohibited from resetting the first host to ensure the normal operation of the computing system. Among them, the method and device described in the embodiment of the present application are based on the same technical concept. Since the principles of the problems solved by the method and the device are similar, the embodiments of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0068] To further illustrate the technical solution provided by the embodiment of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiment of the present application provides the method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiment of the present application. The method may be executed or executed in parallel in the actual processing process or when the device is executed in accordance with the method sequence shown in the embodiment or drawings.

[0069] Figure 2 A flowchart of a host exception handling method provided in an embodiment of the present application, which can be executed by a host exception handling device, which can be implemented by software, hardware, or a combination of software and hardware to ensure the normal operation of the computing system. Figure 2 As shown, the process includes the following steps:

[0070] S21, obtaining first operating information of the first host, second operating information of the second host, and third operating information of the slave;

[0071] In the embodiment of the present application, when multiple hosts in the communication network are started, each host decides to start the communication network according to its own operating status and startup sequence. Figure 1 The first host 101 and the second host 102 are shown. For example, host A starts before host B, and host B starts before host C, and the self-test status of host A is normal, then host A becomes the first host 101, and hosts B and C become the second host 102; further, each host can be numbered, for example, the second host B is numbered 1, and the second host C is numbered 2, so as to facilitate the distinction between the hosts. In the decision-making process, the first host 101 and the second host 102 can also be decided based on their respective numbering sequences.

[0072] In some possible embodiments, the first operation information reported by the control system 101a in the first host 101 to the MCU 101b includes the communication status information between the first host 101 and the slave 103. The communication status information refers to the communication status between the first host 101 and the slave 103, for example, the first host 101 and the slave 103 communicate normally.

[0073] In some other possible embodiments, the first operation information may also include time information of the first host 101 and communication quantity information between the first host 101 and the slave 103. The time information refers to the time when the control system 101a reports the first operation information to the MCU 101b, for example, 2021.2.30 18:50; the communication quantity information refers to the number of successful communications between the first host 101 and the slave 103, for example, the first host 101 and the slave 103 agree to communicate once per second, and the communication quantity is automatically increased by 1 for each successful communication.

[0074] Among them, the time information can help the user accurately determine whether there is an abnormality in the first host 101. For example, if the time information reported by the control system 101a within 3 minutes is all historical time information, it means that there is an abnormality in the first host 101; the communication quantity information can help the user accurately determine whether there is a communication abnormality between the first host 101 and the slave 103. For example, the first host 101 and the slave 103 agree to communicate once per second, but the communication quantity information in the first operation information within 10 seconds is only 5 times, it means that there is a communication abnormality between the first host 101 and the slave 103.

[0075] The second operation information of the second host 102 acquired by the MCU 101b includes the communication status information between the second host 102 and the slave 103. The communication status information refers to the communication status between the second host 102 and the slave 103, for example, the second host 102 and the slave 103 communicate normally.

[0076] In some other possible embodiments, the second operation information may further include time information of the second host 102 and communication quantity information between the second host 102 and the slave 103. The time information refers to the time when the second host 102 reports the second operation information to the MCU 102b, for example, 2021.2.30 18:50; the communication quantity information refers to the number of successful communications between the second host 102 and the slave 103, for example, the second host 102 and the slave 103 agree to communicate once per second, and the communication quantity is automatically increased by 1 for each successful communication.

[0077] Among them, the time information can help the user accurately determine whether there is an abnormality in the second host 102. For example, if the time information reported by the control system 102a within 3 minutes is all historical time information, it means that there is an abnormality in the second host 102; the communication quantity information can help the user accurately determine whether there is a communication abnormality between the second host 102 and the slave 103. For example, the second host 102 and the slave 103 agree to communicate once per second, but the communication quantity information in the second operation information within 10 seconds is only 6 times, it means that there is a communication abnormality between the second host 102 and the slave 103.

[0078] The third operation information of the slave 103 acquired by the MCU101b may include the communication status information between the slave 103 and the first host 101, and the communication status information between the slave 103 and the second host 102. The communication status information between the slave 103 and the first host 101 refers to the communication status between the slave 103 and the first host 101, for example, the slave 103 and the first host 101 communicate normally; the communication status information between the slave 103 and the second host 102 refers to the communication status between the slave 103 and the second host 102, for example, the slave 103 and the second host 102 communicate normally.

[0079] In some other possible embodiments, the third operation information may also include time information of the slave 103, communication quantity information between the slave 103 and the first host 101, and communication quantity information between the slave 103 and the second host 102. The time information refers to the time when the slave 103 reports the third operation information to the MCU 103b, for example, 2021.2.30 18:50; the communication quantity information between the slave 103 and the first host 101 refers to the number of successful communications between the slave 103 and the first host 101, for example, the slave 103 and the first host 101 agree to communicate once per second, and the communication quantity automatically increases by 1 for each successful communication; the communication quantity information between the slave 103 and the second host 102 refers to the number of successful communications between the slave 103 and the second host 102, for example, the slave 103 and the second host 102 agree to communicate once per second, and the communication quantity automatically increases by 1 for each successful communication.

[0080] Among them, the time information can help the user accurately determine whether the slave 103 has an abnormality. For example, if the time information reported by the control system 103a within 3 minutes is all historical time information, it means that the slave 103 has an abnormality; the communication quantity information can help the user accurately determine whether there is a communication abnormality between the slave 103 and the first host 101 and the second host 102. For example, the slave 103 and the first host 101 agree to communicate once per second, and the communication quantity information between the slave 103 and the first host 101 in the third operation information within 10s is only 5 times, which means that a communication abnormality has occurred between the slave 103 and the first host 101; the slave 103 and the second host 102 agree to communicate once per second, and the communication quantity information between the slave 103 and the second host 102 in the third operation information within 10s is only 6 times, which means that a communication abnormality has occurred between the slave 103 and the second host 102.

[0081] The communication status information between the first host 101 and the slave 103 , the second host 102 and the slave 103 , the slave 103 and the first host 101 , and the slave 103 and the second host 102 may be realized through a heartbeat mechanism or a service counting mechanism.

[0082] In other possible embodiments, the first operating information reported by the first host 101 may also include key process information of the first host 101, such as system process information, host process information of the command line program, etc., and the specific information is determined by the main function of the first host 101; the second operating information reported by the second host 102 may also include key process information of the second host 102, such as system process information, host process information of the command line program, etc., and the specific information is determined by the main function of the second host 102; the third operating information reported by the slave 103 may also include key process information of the slave 103, such as system process information, host process information of the command line program, etc., and the specific information is determined by the main function of the slave 103.

[0083] S22, verifying whether an abnormality occurs in the first host according to the first operation information, the second operation information, and the third operation information;

[0084] In a possible implementation, if the MCU 101b of the first host 101 detects that there is abnormal information in the first operation information reported by the first host 101, for example, the MCU 101b detects that the first operation information within a period of time is empty information, then it is verified that the first host 101 is abnormal; or

[0085] MCU101b compares the first operating information of the first host 101 with the third operating information of the slave 103. If the comparison shows that there is no abnormal information in the first operating information, but there is abnormal information in the third operating information, and when the MCU102b of the second host 102 compares the second operating information with the third operating information, it is found that there is no abnormal information in both the second operating information and the third operating information, then it is verified that an abnormality has occurred in the first host 101.

[0086] For example, MCU101b compares the first operation information with the third operation information, and finds that the communication status information between the first host 101 and the slave 103 in the first operation information does not contain abnormal information, and the communication status information between the slave 103 and the first host 101 in the third operation information does contain abnormal information. Further, the second operation information of the second host 102 is compared with the third operation information, and it is found that the communication status information between the second host 102 and the slave 103 in the second operation information does not contain abnormal information, and the communication status information between the slave 103 and the second host 102 in the third operation information does not contain abnormal information, which indicates that the slave 103 and the second host 102 can communicate with each other normally. Further, combined with the situation that the slave 103 and the first host 101 cannot communicate normally, it is verified that the first host 101 is abnormal.

[0087] S23: If it is verified that the first host is abnormal, a reset operation of the first host is performed.

[0088] In a possible implementation, if the MCU 101b of the first host 101 verifies that the first host 101 is abnormal according to the first operation information, the second operation information, and the third operation information, the reset path of the first host 101 is opened; at the same time, when the control system 102a or MCU 102b of the second host 102 receives the notification message of the abnormality of the first host 101 sent by the control system 101a or MCU 101b of the first host 101, the second host 102 sends a reset signal to the first host 101. When the reset path is opened and the first host 101 receives the reset signal sent by the second host 102, the control system 101a of the first host 101 performs a reset operation, for example, the control system 101a releases the control right of the computing system, and at this time, the second host 102 obtains the control right of the computing system instead of the first host 101.

[0089] In one possible implementation, when there are N second hosts 102, the N second hosts 102 decide on a target host from the N second hosts 102 based on their respective second operating information and numbers, and the target host sends a reset signal to the first host 101, and obtains control of the computing system on behalf of the first host 101.

[0090] For example, when N is 3, when the four hosts in the communication network are started, the second host B is numbered 1, the second host C is numbered 3, and the second host D is numbered 2. Then, when an abnormality occurs in the first host 101, if the second operating information of the second host B does not contain abnormal information, the second host B numbered 1 is used as the target host, and the second host B sends a reset signal to the first host 101; if the second operating information of the second host B contains abnormal information, and the second operating information of the second hosts C and D does not contain abnormal information, the second host D numbered 2 is used as the target host, and the second host D sends a reset signal to the first host 101; if after processing the abnormal information of the second host B, the second host B and the second host D can both be used as target hosts, the N second hosts re-determine the target host based on their respective second operating information and numbers, and the target host sends a reset signal to the first host 101.

[0091] By controlling the first host to perform the reset operation through the above method, the first host can be prevented from being reset by mistake. For example, when the MCU101b of the first host 101 itself is abnormal, the MCU101b may mistakenly open the reset path of the first host 101, but because the MCU101b itself is abnormal, the MCU102b does not obtain the abnormal information of the first host 101 from the MCU101b, and will not send a reset signal to the first host 101, so the first host 101 will not be reset abnormally.

[0092] In some possible embodiments, if it is verified according to the first operation information, the second operation information, and the third operation information that the first host 101 has no abnormality, the first host 101 shields the reset signal sent by the second host 102; or

[0093] If the second host 102 is detected to be abnormal according to the second operation information of the second host 102, the first host 101 shields the reset signal sent by the second host.

[0094] In one possible design, when there are N second hosts 102, if, based on the second operating information of each of the N second hosts 102, it is detected that M of the N second hosts 102 are abnormal, the first host 101 shields the reset signals sent by the M second hosts, where M is an integer greater than 0 and less than or equal to N.

[0095] Therefore, when the second host 102 (or M second hosts among N second hosts 102) itself operates abnormally, for example, the common "memory stepping" error in the software field or the hardware is damaged and generates an error signal, only the control system 102b of the second host 102 (or M second hosts among N second hosts 102) will mistakenly send a reset signal to the first host 101 and enter the standby main process. Since the MCU101b of the first host 101 does not detect that the first host 101 is abnormal, it will not open the reset path of the first host 101, and therefore the first host 101 will not be reset abnormally.

[0096] In some other possible embodiments, the health score of the first host 101 can be scored based on the first operating information of the first host 101, and the health score of the second host 102 can be scored based on the second operating information of the second host 102. When the health score of the second host 102 is greater than the health score of the first host 101, the first host 101 opens a reset path, and the second host 102 sends a reset signal to the first host 101, so that the first host 101 performs a reset operation.

[0097] Based on the above Figure 2 The host exception handling method shown is Figure 3 An exemplary logic diagram of host exception handling is shown, such as Figure 3 As shown, host A can be the first host or the second host, or host B can be the first host or the second host, wherein the master-slave state of the first host is master, and the master-slave state of the second host is slave.

[0098] exist Figure 3 In the example, when host A is the first host and host B is the second host, the master-slave state of host A is master. Only when the MCU of host A detects that host A is abnormal can the reset path of host A be opened through the OR gate. At this time, the control system of host B will send a reset signal to host A. Host A will perform the reset operation when it receives the reset signal through the AND gate. In addition, host B can perform the reset operation unconditionally. Similarly, when host A is the second host and host B is the first host, the reset execution process of host A and host B is similar, and will not be repeated here. The reset execution status when host A is in the master state is shown in Table 1:

[0099]

[0100] Table 1: A host reset execution situation

[0101] Based on the host exception handling method, it is possible to accurately check whether the first host has an exception, so that when the first host has an exception, the exception can be handled in time to prevent the entire computing system from being disconnected due to the host exception. At the same time, when the first host has no exception, the second host is prohibited from resetting the first host to ensure the normal operation of the computing system.

[0102] Based on the same inventive concept, a host exception handling device is also provided in the embodiment of the present application, such as Figure 4 FIG. 1 is a schematic diagram of a host exception handling device in the present application, the device comprising:

[0103] An acquisition module 41 is used to acquire first operation information of a first host, second operation information of a second host, and third operation information of a slave, wherein the first host manages the second host and the slave, and the second host is connected to the slave;

[0104] A verification module 42, configured to verify whether the first host is abnormal according to the first operation information, the second operation information, and the third operation information;

[0105] The execution module 43 is used to execute a reset operation of the first host if it is verified that the first host is abnormal.

[0106] In a possible design, the verification module 42 is specifically used for:

[0107] If there is abnormal information in the first operation information, then verifying that the first host is abnormal; or

[0108] The first operating information is compared with the third operating information. If the comparison shows that there is no abnormal information in the first operating information, but there is abnormal information in the third operating information, and when the second operating information is compared with the third operating information, it is found that there is no abnormal information in both the second operating information and the third operating information, then it is verified that an abnormality has occurred in the first host.

[0109] In a possible design, the first operation information includes communication status information between the first host and the slave;

[0110] The second operation information includes communication status information between the second host and the slave;

[0111] The third operation information includes communication status information between the slave and the first host, and communication status information between the slave and the second host.

[0112] In a possible design, the execution module 43 is specifically used to:

[0113] Opening a reset path of the first host;

[0114] When the reset path is opened and a reset signal sent by the second host is received, the reset operation is performed.

[0115] In other embodiments, in addition to the above Figure 4 In addition to the modules shown in FIG. 1 , a shielding module may be further included, such as Figure 5 , which is a schematic diagram of another host exception handling device provided by an embodiment of the present application. The device comprises: an acquisition module 41, a verification module 42, an execution module 43, and a shielding module 51.

[0116] A shielding module 51 is used to shield the reset signal sent by the second host if it is verified that the first host has no abnormality; or

[0117] If it is detected according to the second operation information that the second host is abnormal, the reset signal sent by the second host is shielded.

[0118] Based on the above-mentioned host exception handling device, it is possible to accurately check whether the first host has an exception, so that when the first host has an exception, the exception can be handled in time to prevent the entire computing system from being disconnected due to the host exception. At the same time, when the first host has no exception, the second host is prohibited from resetting the first host to ensure the normal operation of the computing system.

[0119] Based on the same inventive concept, an electronic device is also provided in the embodiment of the present application, and the electronic device can realize the function of the aforementioned host abnormality processing device, referring to Figure 6 , the electronic device comprises:

[0120] At least one processor 61, and a memory 62 connected to the at least one processor 61. The specific connection medium between the processor 61 and the memory 62 is not limited in the embodiment of the present application. Figure 6 In the example, the processor 61 and the memory 62 are connected via a bus 60. The bus 60 is Figure 6 The connection between other components is shown by bold lines, and the connection between other components is only for schematic illustration and is not intended to be limiting. The bus 60 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. Alternatively, the processor 61 can also be called a controller, and there is no limitation on the name.

[0121] In the embodiment of the present application, the memory 62 stores instructions that can be executed by at least one processor 61. The at least one processor 61 can execute the host exception handling method discussed above by executing the instructions stored in the memory 62. The processor 61 can implement Figure 4 Or the functions of each module in the device shown in 5.

[0122] Among them, the processor 61 is the control center of the device, and can use various interfaces and lines to connect the various parts of the entire control device. By running or executing instructions stored in the memory 62 and calling data stored in the memory 62, the various functions of the device and processing data, the device can be monitored as a whole.

[0123] In a possible design, the processor 61 may include one or more processing units, and the processor 61 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the modem processor may not be integrated into the processor 61. In some embodiments, the processor 61 and the memory 62 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on separate chips.

[0124] The processor 61 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the host exception handling method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0125] The memory 62 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 62 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. The memory 62 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 62 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0126] By programming the processor 61, the code corresponding to the host exception handling method described in the above embodiment can be fixed into the chip, so that the chip can execute the code when running. Figure 2 The steps of the host exception handling method of the embodiment shown are as follows: How to design and program the processor 61 is a technique known to those skilled in the art and will not be described in detail here.

[0127] Based on the same inventive concept, an embodiment of the present application further provides a storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the computer executes the host exception handling method discussed above.

[0128] In some possible implementations, various aspects of the host exception handling method provided in the present application may also be implemented in the form of a program product, which includes a program code. When the program product is run on the device, the program code is used to enable the control device to execute the steps of the host exception handling method according to various exemplary embodiments of the present application described above in this specification.

[0129] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0130] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0131] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0133] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A host exception handling method, characterized in that: The method comprises: Acquire first operation information of a first host, second operation information of a second host, and third operation information of a slave, wherein the first host manages the second host and the slave, and the second host is connected to the slave; Verifying whether the first host is abnormal according to the first operation information, the second operation information, and the third operation information; If it is verified that the first host is abnormal, a reset operation of the first host is performed.

2. The method according to claim 1, characterized in that The checking that the first host is abnormal includes: If there is abnormal information in the first operation information, then verifying that the first host is abnormal; or The first operating information is compared with the third operating information. If the comparison shows that there is no abnormal information in the first operating information, but there is abnormal information in the third operating information, and when the second operating information is compared with the third operating information, it is found that there is no abnormal information in both the second operating information and the third operating information, then it is verified that an abnormality has occurred in the first host.

3. The method according to claim 2, characterized in that The first operation information includes communication status information between the first host and the slave; The second operation information includes communication status information between the second host and the slave; The third operation information includes communication status information between the slave and the first host, and communication status information between the slave and the second host.

4. The method according to claim 1, characterized in that The performing of the resetting operation of the first host includes: Opening a reset path of the first host; When the reset path is opened and a reset signal sent by the second host is received, a reset operation of the first host is performed.

5. The method according to claim 1, characterized in that The method further comprises: If it is verified that the first host has no abnormality, shielding the reset signal sent by the second host; or If it is detected according to the second operation information that the second host is abnormal, the reset signal sent by the second host is shielded.

6. A host abnormality processing device, characterized in that: The device comprises: an acquisition module, configured to acquire first operation information of a first host, second operation information of a second host, and third operation information of a slave, wherein the first host manages the second host and the slave, and the second host is connected to the slave; a verification module, configured to verify whether the first host is abnormal according to the first operation information, the second operation information, and the third operation information; The execution module is used to execute a reset operation of the first host if it is verified that the first host is abnormal.

7. The device according to claim 6, characterized in that The verification module is specifically used for: If there is abnormal information in the first operation information, then verifying that the first host is abnormal; or The first operating information is compared with the third operating information. If the comparison shows that there is no abnormal information in the first operating information, but there is abnormal information in the third operating information, and when the second operating information is compared with the third operating information, it is found that there is no abnormal information in both the second operating information and the third operating information, then it is verified that an abnormality has occurred in the first host.

8. The device according to claim 6, characterized in that The execution module is specifically used for: Opening a reset path of the first host; When the reset path is opened and a reset signal sent by the second host is received, a reset operation of the first host is performed.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to implement the method steps of any one of claims 1 to 5 when executing the computer program stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps of any one of claims 1 to 5 are implemented.

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