Clock correction method, circuit and device
Through the multi-round correction method and lookup table update correction parameters, the existing clock duty cycle correction circuit is solved, and the target value is fast locked and efficient correction is achieved, suitable for high-frequency and multi-channel scenarios.
Patent Information
- Application Number
- CN202310850724.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-11
- Publication Date
- 2025-01-14
AI Technical Summary
The existing clock duty cycle correction circuit has low efficiency, long time and high hardware consumption at high operating frequency and wide correction range, making it difficult to meet the needs of high-speed circuits, especially in the repetition of multi-channel and multi-scenarios, which leads to the accumulation of locking time. The overall chip clock duty cycle correction time becomes longer.
Using multiple rounds of correction methods, the lookup table is used to correct according to the distortion offset and calibration correction parameters, and the locked target value and lookup table are used to update the initial value and adjustment step size of the correction parameters, reducing hardware consumption and quickly locking the target value, improving calibration efficiency .
The clock correction logic is realized through software, which reduces hardware consumption, shortens the lock time of the target value, and improves correction efficiency. It is suitable for high-frequency and multi-channel scenarios and improves clock signal quality.
Smart Images
Figure CN119315969A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology, and in particular to a clock correction method, circuit and device. Background Art
[0002] In the CMOS (Complementary Metal Oxide Semiconductor) process, non-idealities such as noise coupling between the power supply and the substrate, PVT (process, voltage and temperature) fluctuations, and signal reflections can all lead to distortion of the clock duty cycle. In addition, during the clock signal transmission process, the asymmetric structure or size of the driver can cause a mismatch in the effects on the rising and falling edges of the clock signal, causing the duty cycle of the clock signal to be distorted after transmission.
[0003] Figure 1 It is a principle block diagram of a traditional clock duty cycle correction circuit. The implementation principle is that if the duty cycle of the clock signal is different, the size of the pulse and common mode level of the clock signal will also be different. Figure 1 The circuit shown can detect and correct duty cycle distortion, which refers to changes in the desired duty cycle, and quadrature clock phase distortion, which refers to changes in the 90 degree difference between the I and Q signals. Figure 1 In the embodiment, the distortion detection module 11 performs distortion detection on the output clock and outputs an error indication signal dcd_cmpr to the clock correction module 14. The clock correction module 14 generates a duty cycle distortion correction feedback signal and an orthogonal clock correction feedback signal according to the error indication signal dcd_cmpr using corresponding correction logic, and transmits the two signals to the duty cycle correction module 12 and the orthogonal clock error correction module 13 respectively, so that the two modules respectively perform duty cycle correction and phase correction on the input clock signal according to the feedback signals.
[0004] The clock duty cycle correction circuit can be implemented in two ways: digital and analog. Although the circuit can be corrected quickly by digital method, this method will increase jitter, reduce the accuracy of analog-to-digital converter (ADC), require a large chip area, consume a lot of power, and the circuit is quite complicated. Therefore, the clock duty cycle correction circuit implemented by digital method is difficult to be designed for high operating frequency and wide correction range. Compared with the digital method, the clock duty cycle correction circuit implemented by analog method has smaller random jitter and deterministic jitter, and can obtain higher accuracy; but the disadvantage is that the locking time is long, which cannot meet the application requirements of high-speed circuits.
[0005] In addition, with the rapid development of communication technology, the application of multi-channels has led to more scenarios where the clock duty cycle of the same chip needs to be distorted. In order to save chip area, the digital circuits in the clock duty cycle correction are generally multiplexed, usually in the following ways:
[0006] 1) The correction value is fixedly added or subtracted according to the feedback offset. If this method is used, the convergence time will be too long if the correction range is large or the correction accuracy is high and the offset is small.
[0007] 2) Use a combination of coarse and fine adjustment to increase the correction range. In this method, the fine adjustment circuit and the coarse adjustment circuit are used at the same time, which not only increases the chip area, but also introduces mismatch problems.
[0008] 3) In the multiplexing of clock correction, only the fixed offset is corrected and then the initial value is restored. The previous correction has little relationship with the next correction. For the same source clock on the same chip, the resource utilization rate of the multiplexed correction module is not high.
[0009] Regardless of the above method, the repeated multiplexing of multiple channels and multiple scenes means the accumulation of locking time, which will inevitably lead to a longer time for the overall chip clock duty cycle correction. Summary of the invention
[0010] The embodiments of the present invention provide a clock correction method, circuit and device to accelerate the locking process of clock correction, improve the clock correction efficiency and save hardware resources.
[0011] To this end, the embodiment of the present invention provides the following technical solutions:
[0012] In one aspect, an embodiment of the present invention provides a clock correction method, the method comprising:
[0013] Perform multiple rounds of clock calibration according to the distortion offset and the lookup table until the calibration parameter reaches the locked target value and the calibration is completed. The lookup table is used to indicate the corresponding relationship between voltage, temperature and calibration calibration parameters.
[0014] After the calibration is completed, the initial values of the calibration parameters and the initial values of the adjustment step length for the next round of calibration are determined using the locked target value and the corresponding calibrated calibration parameters in the lookup table, and the initial values of the calibration parameters and the initial values of the adjustment step length are written into the lookup table.
[0015] Optionally, the correction parameters include: a duty cycle correction parameter and a phase correction parameter.
[0016] Optionally, performing multiple rounds of correction on the clock according to the distortion offset and the lookup table until the correction parameter reaches a locked target value and the correction ends includes:
[0017] Determine the initial values of the correction parameters and the initial values of the adjustment step length for this round of correction;
[0018] The distortion offset obtained by sampling the clock signal detection;
[0019] The correction parameter and / or the adjustment step size are adjusted according to the set rule until the current round of correction is determined to be finished according to the distortion offset.
[0020] Optionally, the method further comprises:
[0021] Setting the adjustment step corresponding to different difference values, wherein the difference value refers to the difference between the current correction parameter and the calibrated correction parameter;
[0022] Determining the initial value of the correction parameter and the initial value of the adjustment step length for this round of correction includes:
[0023] If this round of calibration is an initial calibration, the user sets the initial values of the calibration parameters or uses the default values, and sets the adjustment step length to the maximum adjustment step length;
[0024] If the current round of calibration is not an initial calibration, the initial values of the calibration parameters and the initial values of the adjustment step length are obtained from the lookup table.
[0025] Optionally, the determining the initial value of the correction parameter and the initial value of the adjustment step length for the next round of correction by using the locked target value and the corresponding calibration correction parameter in the lookup table comprises:
[0026] The average of the locked target value and the corresponding calibration correction parameter in the lookup table is used as the initial value of the correction parameter for the next round of calibration;
[0027] The initial value of the adjustment step length for the next round of calibration is determined according to the difference between the target value locked in the previous round of calibration and the corresponding calibrated calibration parameter.
[0028] Optionally, adjusting the correction parameter and / or the adjustment step according to a set rule until determining that the current round of correction is finished according to the distortion offset includes:
[0029] In a manner of adjusting the step size from large to small, the correction parameter of the current round is increased or decreased in sequence according to the set step size until a jump edge of the distortion offset is detected each time;
[0030] After the adjustment step is reduced to the minimum unit and the transition edge of the distortion offset is detected, it is determined that the current round of correction is finished.
[0031] Optionally, the method further includes: establishing the lookup table through simulation.
[0032] On the other hand, an embodiment of the present invention further provides a clock correction circuit, the circuit comprising:
[0033] A lookup table module, used to store a lookup table, wherein the lookup table is used to indicate a corresponding relationship between voltage, temperature and calibration correction parameters;
[0034] A logic control module, used for performing multiple rounds of clock correction according to the distortion offset and the lookup table, until the correction parameter reaches the locked target value and the correction is completed;
[0035] The lookup table updating module is used to determine the initial value of the correction parameter and the initial value of the adjustment step for the next round of correction after the correction is completed using the locked target value and the corresponding calibrated correction parameters in the lookup table, and write the initial value of the correction parameter and the initial value of the adjustment step into the lookup table.
[0036] Optionally, the logic control module includes:
[0037] An initial value determination unit, used to determine the initial value of the current round of correction parameters and the initial value of the adjustment step length;
[0038] A sampling unit, used for sampling the distortion offset detected by the clock signal;
[0039] A parameter adjustment unit is used to adjust the correction parameter and / or the adjustment step according to a set rule until the current round of correction is determined to be finished according to the distortion offset.
[0040] Optionally, the initial value determination unit is specifically used to, when this round of correction is an initial correction, allow the user to set the initial value of the correction parameter for this round or use the default value, and set the adjustment step to the maximum adjustment step; when this round of correction is not an initial correction, obtain the initial value of the correction parameter from the lookup table.
[0041] Optionally, the clock includes multiple channels; the circuit further includes: a state machine, used for sequentially selecting a channel of the clock to be calibrated.
[0042] On the other hand, an embodiment of the present invention further provides a clock correction device, the device comprising: a duty cycle distortion compensation circuit, a phase correction circuit, a distortion detection circuit, and the clock correction circuit described above;
[0043] The duty cycle distortion compensation circuit is used to perform duty cycle distortion compensation on the input clock signal according to the correction parameter output by the clock correction circuit;
[0044] The phase correction circuit is used to perform phase correction on the compensated clock signal output by the duty cycle distortion compensation circuit, and output the corrected clock signal;
[0045] The distortion detection circuit is used to perform distortion detection on the corrected clock signal and output a distortion offset;
[0046] The clock correction circuit is used to sample the distortion offset, and feed back duty cycle correction parameters and phase correction parameters to the duty cycle distortion compensation circuit and the phase correction circuit respectively according to the distortion offset, and adjust the correction parameters to perform multiple rounds of clock correction until the correction parameters reach the locked target value and the correction is completed.
[0047] The clock correction method, circuit and device provided in the embodiments of the present invention implement the clock correction logic through software, reduce the hardware consumption of the clock correction circuit, and, through a lookup table, can quickly select a valid initial value in each round of correction, effectively shorten the locking time of the target value, and improve the correction efficiency.
[0048] Furthermore, during the initial round of calibration, the user sets the initial values of the calibration parameters for this round or uses the default values, and sets the adjustment step to the maximum adjustment step; during the non-initial round of calibration, the initial values of the calibration parameters for this round are determined based on the calibration parameters at the end of the previous round of calibration and the calibrated calibration parameters, and the adjustment step is determined based on the difference between the calibration parameters at the end of the previous round of calibration and the calibrated calibration parameters, thereby making the setting of the initial values of the calibration parameters and the adjustment step more reasonable and enabling the target value to be locked more quickly.
[0049] Furthermore, during the calibration process, the adjustment step size changes step by step from large to small, so as to better balance the calibration accuracy and the calibration speed and improve the quality of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] Figure 1 It is the principle block diagram of the traditional clock duty cycle correction circuit;
[0051] Figure 2 is a flow chart of a clock correction method provided by an embodiment of the present invention;
[0052] Figure 3 is a structural schematic diagram of a clock correction circuit provided by an embodiment of the present invention;
[0053] Figure 4 The invention is a schematic diagram of a clock correction device according to an embodiment of the invention. DETAILED DESCRIPTION
[0054] The principle and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.
[0055] Duty cycle refers to the ratio of high pulse width to period within a pulse signal cycle. The ideal clock model is a square wave with a duty cycle of 50% and a fixed period. In applications, non-idealities such as voltage and temperature fluctuations and signal reflections can cause distortion of the clock duty cycle. Existing clock correction circuits have problems such as long correction time, low efficiency, and large chip area occupation. To this end, an embodiment of the present invention provides a clock correction method, circuit, and device, which implements clock correction logic through software to reduce the hardware consumption of the clock correction circuit. Moreover, through a lookup table, an effective initial value can be quickly selected in each round of correction, effectively shortening the locking time of the target value and improving the correction efficiency.
[0056] like Figure 2 FIG. 1 is a flow chart of a clock correction method provided by an embodiment of the present invention, comprising the following steps:
[0057] Step 201, multiple rounds of clock calibration are performed according to the distortion offset and a lookup table until the calibration parameter reaches a locked target value and the calibration is terminated. The lookup table is used to indicate the corresponding relationship between voltage, temperature and calibration calibration parameters.
[0058] In the embodiment of the present invention, the correction parameters include: a duty cycle correction parameter and a phase correction parameter.
[0059] The lookup table can be generated in advance by calibration. Specifically, after the correction circuit is built, the entire clock duty cycle correction feedback loop is simulated according to the actual application scenario, and the correction parameters under different conditions are simulated by a single variable method based on non-ideal parameters such as voltage and temperature.
[0060] Furthermore, for multi-channel clocks, each channel clock may be calibrated one by one, the correction parameters of the channel clock under different voltages and temperatures may be calibrated, and the calibration values may be written into the lookup table.
[0061] In practical applications, the lookup table may be written into a RAM (Random Access Memory).
[0062] Table 1 below is an example of a lookup table in an embodiment of the present invention.
[0063] Table 1
[0064]
[0065]
[0066] The above Table 1 is a lookup table corresponding to three-channel clocks. Of course, the embodiment of the present invention does not limit whether the clock is single-channel or multi-channel. Compared with a single-channel clock, in the correction application of multiple-channel clocks, it is only necessary to select each clock to be corrected and correct them separately.
[0067] It should be noted that one round of calibration means starting from the set initial calibration parameters, adjusting the calibration parameters according to certain rules until the calibration parameters are locked to the target values of the calibration parameters. The specific process is as follows:
[0068] (1) Determine the initial values of the correction parameters and the initial values of the adjustment step size for this round of correction.
[0069] If this round of calibration is an initial calibration, the user can set the initial values of the calibration parameters for this round or use the default values, and set the adjustment step length to the maximum adjustment step length; the default value can be, for example, the average value of all calibration calibration parameters.
[0070] If the current round of calibration is not an initial calibration, the initial values of the calibration parameters and the initial values of the adjustment step length are obtained from the lookup table.
[0071] The initial value of the correction parameter and the initial value of the adjustment step in the lookup table are calculated based on the correction parameters at the end of the previous round of correction, i.e., the target value and the calibrated correction parameter. For example, the initial value of the correction parameter can be the average value of the target value locked in the previous round of correction and the corresponding calibrated correction parameter; the initial value of the adjustment step can be determined based on the difference between the target value locked in the previous round of correction and the corresponding calibrated correction parameter.
[0072] (2) The distortion offset obtained by sampling clock signal detection.
[0073] The distortion offset can be obtained by a corresponding distortion detection circuit. The distortion detection circuit can use existing detection technology to detect the clock signal compensated based on the above correction parameters (including duty cycle correction parameters and phase correction parameters), and output the distortion offset. This embodiment of the present invention is not limited to this.
[0074] (3) adjusting the correction parameter and / or the adjustment step size according to a set rule until the current round of correction is determined to be completed based on the distortion offset.
[0075] The setting rule is to adjust the convergence mode of the step size from large to small, gradually increase or decrease the correction parameter, and after sampling the jump edge of the distortion offset, call back the correction parameter until the correction parameter is locked.
[0076] In the embodiment of the present invention, an adjustment step corresponding to different difference values can be set, and the difference value refers to the difference between the current correction parameter and the calibration correction parameter. The larger the difference value, the larger the corresponding adjustment step value; the smaller the difference value, the smaller the corresponding adjustment step value. The adjustment step value refers to the unit value of increasing or decreasing the correction parameter each time the adjustment is performed.
[0077] In order to lock the target value more quickly during the clock correction process, you can make a coarse adjustment with a large step size at the beginning to find the interval to which the target value belongs, and then converge from large to small. For example, you can follow the step size convergence rule of 8-4-2-1 and gradually reduce the adjustment step size for fine adjustment, so that you can lock the target value more quickly and efficiently.
[0078] Accordingly, the specific process of adjusting the correction parameters is as follows:
[0079] In a manner of adjusting the step size from large to small, the correction parameter of the current round is increased or decreased in sequence according to the set step size until a jump edge of the distortion offset is detected each time;
[0080] After the adjustment step is reduced to the minimum unit and the transition edge of the distortion offset is detected, it is determined that the current round of correction is finished.
[0081] It should be noted that each time the jump edge of the distortion offset is detected, the correction parameter needs to be adjusted in the opposite direction. For example, before the jump edge of the distortion offset is detected, the correction parameter is adjusted to increase. After the jump edge of the distortion offset is detected, the adjustment step size needs to be reduced, and the correction parameter is adjusted to decrease according to the adjusted step size. If the jump edge of the distortion offset is not detected, the original adjustment step size and the original operation direction (i.e., increase or decrease) are maintained until the jump edge of the distortion offset is detected.
[0082] The process of correcting the clock using the above method will be described in detail below with examples.
[0083] Step 202, after the calibration is completed, the initial values of the calibration parameters and the initial values of the adjustment step for the next round of calibration are determined using the locked target value and the corresponding calibrated calibration parameters in the lookup table, and the initial values of the calibration parameters and the initial values of the adjustment step are written into the lookup table.
[0084] The clock correction method provided by the embodiment of the present invention can quickly select an effective initial value in each round of correction by looking up a table, effectively shorten the locking time of the target value, and improve the correction efficiency. Furthermore, in the initial round of correction, the user sets the initial value of the correction parameter of this round or uses the default value, and sets the adjustment step length to the maximum adjustment step length; in the non-initial round of correction, the initial value of the correction parameter of this round is determined according to the correction parameter at the end of the previous round of correction and the calibration correction parameter, and the adjustment step length is determined according to the difference between the correction parameter at the end of the previous round of correction and the calibration correction parameter, so that the setting of the initial value of the correction parameter and the adjustment step length can be more reasonable, and the target value can be locked more quickly.
[0085] During the calibration process, the adjustment step size changes step by step from large to small, so as to better balance the calibration accuracy and calibration speed and improve the quality of the clock signal. An example is given below to illustrate this.
[0086] The following example illustrates the detailed process of correcting a clock using the clock correction method of the present invention.
[0087] In this embodiment, the adjustment step size converges according to the step size of 8-4-2-1. In addition, for the convenience of description, dcd_cmpr 1 is used to indicate that the corrected clock signal output after the current correction parameter is fed back to the correction circuit (including the duty cycle compensation circuit and the phase correction circuit) is still negatively deviated, that is, f(coden)<=f(codegoal), and dcd_cmpr 0 indicates that the clock signal after the current correction parameter is fed back to the correction circuit begins to deviate positively, that is, f(coden)>=f(codegoal). The specific correction process is as follows:
[0088] 1) At the initial moment, in order to find the target value of the correction parameter more quickly, a coarse adjustment with a large step length is required to find the target value interval more quickly. Assuming that f(coden)<=f(codegoal) at this time, the correction parameter is increased by +8.
[0089] 2) When the transition edge of the distortion offset is detected, the adjustment step size is adjusted from 8 to 4. Assuming that f(coden)>=f(codegoal) at this time, the correction parameter starts to be negative -4.
[0090] 3) When the transition edge of the distortion offset is detected again, the adjustment step size is adjusted from 4 to 2, and the correction parameter starts to increase in the positive direction by +2.
[0091] 4) When the distortion offset jump edge is detected again, the adjustment step is adjusted from 2 to 1, and the correction parameter starts to move negatively to -1.
[0092] 5) After that, the correction parameter is added or subtracted by 1 in the minimum step size and hovers around codegoal, that is, the correction parameter is locked to the target value codegoal. At this point, a correction phase ends.
[0093] When the initial correction parameters are far from the target value, it will still take a long time to lock even if the step size converges. However, the initial value of the correction parameter obtained through the lookup table is relatively closer to the target value because the initial value in the lookup table is determined based on the target value after the previous round of correction and the corresponding calibration parameters. In addition, combined with the adjustment method of gradually closing the step size, the correction parameter can be quickly locked to the target value, which greatly reduces the clock correction time and improves the correction efficiency.
[0094] The clock correction method provided in the embodiment of the present invention can be applied to the correction of a single clock or to the correction of multiple clocks. For example, the state machine can be used to ensure the orderly correction of each clock through jump. In addition, the correction state signal can be set to indicate whether the correction is completed. After the correction of each clock is completed, the correction state signal is set to be valid.
[0095] In addition, in the case of multi-channel correction multiplexing, although the same source clock is used in different scenarios and channels and the degree of distortion caused by voltage and temperature is different, the offset direction is consistent. The convergence step and correction parameter target value can be reused through the previous correction process for subsequent clock correction, thereby achieving more efficient and flexible rapid convergence and improving resource utilization in multi-channel use.
[0096] Accordingly, an embodiment of the present invention further provides a clock correction circuit, such as Figure 3 The figure shows a schematic diagram of the structure of the clock correction circuit.
[0097] The clock correction circuit 300 includes the following modules:
[0098] A lookup table module 301 is used to store a lookup table, wherein the lookup table is used to indicate the corresponding relationship between voltage, temperature and calibration correction parameters;
[0099] The logic control module 302 is used to perform multiple rounds of clock correction according to the distortion offset and the lookup table until the correction parameter reaches the lock target value and the correction ends;
[0100] The lookup table update module 303 is used to determine the initial value of the correction parameter and the initial value of the adjustment step for the next round of correction after the correction is completed using the locked target value and the corresponding calibrated correction parameters in the lookup table, and write the initial value of the correction parameter and the initial value of the adjustment step into the lookup table.
[0101] The logic control module 302 may specifically include the following units:
[0102] An initial value determination unit, used to determine the initial values of the current round of calibration parameters and the initial values of the adjustment step length. For example, when the current round of calibration is the initial calibration, the initial values of the current round of calibration parameters are set by the user or the default values are used, and the adjustment step length is set to the maximum adjustment step length; when the current round of calibration is not the initial calibration, the initial values of the calibration parameters are obtained from the lookup table;
[0103] A sampling unit, used for sampling the distortion offset detected by the clock signal;
[0104] A parameter adjustment unit is used to adjust the correction parameter and / or the adjustment step according to a set rule until the current round of correction is determined to be finished according to the distortion offset.
[0105] The adjustment method and process of the correction parameter and the adjustment step length by the parameter adjustment unit can refer to the description of the clock correction method of the present invention above, which will not be repeated here.
[0106] The clock correction circuit provided in the embodiment of the present invention can quickly select a valid initial value in each round of correction by means of a lookup table, effectively shorten the locking time of the target value, and improve the correction efficiency.
[0107] Furthermore, in another non-limiting embodiment of the clock correction circuit of the present invention, the clock has multiple channels, and the circuit may further include: a state machine (not shown) for sequentially selecting a channel of the clock to be calibrated.
[0108] In the case of multi-channel correction multiplexing, although the same source clock is used in different scenarios and channels and the degree of distortion caused by voltage and temperature is different, the offset direction is consistent. The convergence step and correction parameter target value can be reused through the previous correction process for subsequent clock correction, thereby achieving more efficient and flexible rapid convergence and improving resource utilization.
[0109] By utilizing the clock correction method and circuit provided in the embodiment of the present invention, a clock signal with any duty cycle can be corrected, thereby improving the practicality and compatibility of the solution.
[0110] Accordingly, an embodiment of the present invention further provides a clock correction device, such as Figure 4 The figure shows a structural diagram of the clock correction device.
[0111] Reference Figure 4 The clock correction device comprises: a duty cycle distortion compensation circuit 401, a phase correction circuit 402, a distortion detection circuit 403, and the clock correction circuit 300 described above. Wherein:
[0112] The duty cycle distortion compensation circuit 401 is used to perform duty cycle distortion compensation on the input clock signal according to the correction parameters output by the clock correction circuit;
[0113] The phase correction circuit 402 is used to perform phase correction on the compensated clock signal output by the duty cycle distortion compensation circuit 401, and output a corrected clock signal;
[0114] The distortion detection circuit 403 is used to perform distortion detection on the corrected clock signal and output a distortion offset;
[0115] The clock correction circuit 300 is used to sample the distortion offset, and feed back duty cycle correction parameters and phase correction parameters to the duty cycle distortion compensation circuit and the phase correction circuit respectively according to the distortion offset, and adjust the correction parameters to perform multiple rounds of clock correction until the correction parameters reach the locked target value and the correction is completed.
[0116] In this embodiment, the clock correction circuit 300 may be implemented by using FPGA and may have a built-in lookup table. The lookup table may be generated in advance by calibration to indicate the corresponding relationship between voltage, temperature and calibration correction parameters.
[0117] The specific process of performing clock correction according to the lookup table and the distortion offset may refer to the description in the above-mentioned method embodiment of the present invention, which will not be described in detail here.
[0118] In addition, in practical applications, the clock signal may have one or more channels. When multiple channels of clock signals need to be corrected, a state machine may be used to sequentially select each channel of clock signal for correction.
[0119] It should be noted that the multiple clocks can be homologous clocks or non-homologous time sources, which is not limited in the embodiments of the present invention. For homologous clocks, although different clocks are used in different scenarios and channels, and the degree of distortion caused by the influence of temperature and voltage is different, the offset direction is usually consistent. Using the scheme of the present invention, when correcting the homologous multiple clocks, the adjustment step size achieved by the previous correction process to achieve convergence can be used for subsequent clock corrections, so that the multiplexed clock correction circuit can achieve more efficient and flexible rapid convergence and improve resource utilization.
[0120] In a specific implementation, each module / unit included in each device or product described in the above embodiments may be a software module / unit or a hardware module / unit, or may be partly a software module / unit and partly a hardware module / unit.
[0121] For example, for each device or product applied to or integrated in a chip, each module / unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module / unit contained therein may be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.
[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A clock correction method, characterized in that: The method comprises: Perform multiple rounds of clock calibration according to the distortion offset and the lookup table until the calibration parameter reaches the locked target value and the calibration is completed. The lookup table is used to indicate the corresponding relationship between voltage, temperature and calibration calibration parameters. After the calibration is completed, the initial values of the calibration parameters and the initial values of the adjustment step length for the next round of calibration are determined using the locked target value and the corresponding calibrated calibration parameters in the lookup table, and the initial values of the calibration parameters and the initial values of the adjustment step length are written into the lookup table.
2. The method according to claim 1, characterized in that: The correction parameters include: a duty cycle correction parameter and a phase correction parameter.
3. The method according to claim 1, characterized in that The performing multiple rounds of correction on the clock according to the distortion offset and the lookup table until the correction parameter reaches the lock target value and the correction ends includes: Determine the initial values of the correction parameters and the initial values of the adjustment step length for this round of correction; The distortion offset obtained by sampling the clock signal detection; The correction parameter and / or the adjustment step size are adjusted according to the set rule until the current round of correction is determined to be finished according to the distortion offset.
4. The method according to claim 3, characterized in that The method further comprises: Setting the adjustment step corresponding to different difference values, wherein the difference value refers to the difference between the current correction parameter and the calibrated correction parameter; Determining the initial value of the correction parameter and the initial value of the adjustment step length for this round of correction includes: If this round of calibration is an initial calibration, the user sets the initial values of the calibration parameters or uses the default values, and sets the adjustment step length to the maximum adjustment step length; If the current round of calibration is not an initial calibration, the initial values of the calibration parameters and the initial values of the adjustment step length are obtained from the lookup table.
5. The method according to claim 1, characterized in that: The method of determining the initial value of the correction parameter and the initial value of the adjustment step length for the next round of correction by using the locked target value and the corresponding calibration correction parameter in the lookup table includes: The average of the locked target value and the corresponding calibration correction parameter in the lookup table is used as the initial value of the correction parameter for the next round of calibration; The initial value of the adjustment step length for the next round of calibration is determined according to the difference between the target value locked in the previous round of calibration and the corresponding calibrated calibration parameter.
6. The method according to claim 3, characterized in that: The step of adjusting the correction parameter and / or the adjustment step according to the set rule until the current round of correction is determined to be finished according to the distortion offset comprises: In a manner of adjusting the step size from large to small, the correction parameter of the current round is increased or decreased in sequence according to the set step size until a jump edge of the distortion offset is detected each time; After the adjustment step is reduced to the minimum unit and the transition edge of the distortion offset is detected, it is determined that the current round of correction is finished.
7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: The lookup table is established through simulation.
8. A clock correction circuit, characterized in that: The circuit comprises: A lookup table module, used to store a lookup table, wherein the lookup table is used to indicate a corresponding relationship between voltage, temperature and calibration correction parameters; A logic control module, used for performing multiple rounds of clock correction according to the distortion offset and the lookup table, until the correction parameter reaches the locked target value and the correction is completed; The lookup table updating module is used to determine the initial value of the correction parameter and the initial value of the adjustment step for the next round of correction after the correction is completed using the locked target value and the corresponding calibrated correction parameters in the lookup table, and write the initial value of the correction parameter and the initial value of the adjustment step into the lookup table.
9. The circuit according to claim 8, characterized in that The logic control module comprises: An initial value determination unit, used to determine the initial value of the current round of correction parameters and the initial value of the adjustment step length; A sampling unit, used for sampling the distortion offset detected by the clock signal; A parameter adjustment unit is used to adjust the correction parameter and / or the adjustment step according to a set rule until the current round of correction is determined to be finished according to the distortion offset.
10. The circuit according to claim 9, characterized in that The initial value determination unit is specifically used to set the initial value of the correction parameter of this round or use the default value when the current round of correction is the initial correction, and set the adjustment step to the maximum adjustment step; when the current round of correction is not the initial correction, obtain the initial value of the correction parameter from the lookup table.
11. The circuit according to any one of claims 8 to 10, characterized in that The clock includes multiple channels; the circuit also includes: The state machine is used to select a clock to be calibrated in sequence.
12. A clock correction device, characterized in that: The device comprises: a duty cycle distortion compensation circuit, a phase correction circuit, a distortion detection circuit, and a clock correction circuit as claimed in any one of claims 8 to 11; The duty cycle distortion compensation circuit is used to perform duty cycle distortion compensation on the input clock signal according to the correction parameter output by the clock correction circuit; The phase correction circuit is used to perform phase correction on the compensated clock signal output by the duty cycle distortion compensation circuit, and output the corrected clock signal; The distortion detection circuit is used to perform distortion detection on the corrected clock signal and output a distortion offset; The clock correction circuit is used to sample the distortion offset, and feed back duty cycle correction parameters and phase correction parameters to the duty cycle distortion compensation circuit and the phase correction circuit respectively according to the distortion offset, and adjust the correction parameters to perform multiple rounds of clock correction until the correction parameters reach the locked target value and the correction is completed.