Groove SiC MOSFET device integrated with reverse freewheeling diode and preparation method thereof

Abstract

The invention discloses a groove SiC MOSFET device integrated with a reverse freewheeling diode and a preparation method of the groove SiC MOSFET device, and relates to the technical field of semiconductors. Source polycrystalline silicon and a P-shield region form a heterojunction diode in an N-epitaxial layer, so that current flowing through a body diode during reverse conduction of the device is shared, and the risk of degradation of a PW region of the device is reduced. And meanwhile, the P-shield region is arranged below the gate oxide layer, so that the impact of gate oxide of a peak electric field can be inhibited, and the reliability problem of the gate oxide layer of the trench SiC MOSFET is improved. The overlapping area of the grid electrode and the drain electrode is reduced in structural design, so that the purpose of reducing the grid-drain capacitance is achieved, the Miller plateau time is shortened, the switching performance of the device is improved, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench SiC MOSFET device with an integrated reverse freewheeling diode and a preparation method thereof. Background Art

[0002] In traditional power conversion circuits, silicon-based MOSFETs are usually used when higher switching frequencies are required, while in high-power conversion applications, silicon-based IGBTs are the most common. As more and more power electronic devices are striving to improve efficiency and power density, silicon power devices are facing the performance dilemma of "voltage resistance" and "efficiency". Compared with silicon devices, SiC MOSFETs have lower on-resistance, higher efficiency, and smaller chip size, so they help power systems reduce the size of inductors, capacitors, power modules / devices, and heat sinks through high frequency, achieving miniaturization and thinness. For this reason, SiC MOSFETs are gradually replacing silicon MOSFETs and silicon IGBTs in the fields of new energy vehicles, solar charging and storage.

[0003] In the application of power electronic systems, the stability and reliability of devices is an important measurement indicator. When a power electronic system fails, if the protection circuit does not work, the SiC MOSFET will be impacted by the surge current. The current flows through the body diode of the SiC MOSFET. When the surge current exceeds the current capacity that the device can withstand, the device will experience gate-source short circuit and PW region degradation. Summary of the invention

[0004] In view of the above problems, the present invention provides a trench SiC MOSFET device with an integrated reverse freewheeling diode and a preparation method thereof, which reduces the risk of bipolar degradation of the device, thereby improving the reverse freewheeling capability of the device, suppresses the impact of the gate oxide of the peak electric field, and improves the reliability problem of the gate oxide layer of the trench SiC MOSFET.

[0005] The technical solution of the present invention is: A method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode comprises the following steps: S100, epitaxially growing an N-epitaxial layer on the N+ substrate layer (1), and forming a PW region on top of the N-epitaxial layer by ion implantation; S200, Al ions are implanted downward from the top of the PW region multiple times to form a P-shield region; S300, N ions are implanted multiple times in the PW region to form an N+ region; S400, Al ions are implanted multiple times in the PW region to form a P+ region; S500, etching is extended downward from the top of the P-shield region to form a source trench region; source polysilicon is deposited in the source trench region; S600, etching is extended downward from the top of the PW region to form a gate trench region; a gate oxide layer is grown on a far side wall and a bottom of the gate trench region; an isolation dielectric layer a is deposited on the other side wall of the gate trench region; and a Poly layer is formed in the gate trench region as a gate electrode lead; S700, sequentially preparing an isolation dielectric layer b, an ohmic contact alloy layer and a front electrode metal layer on the N-epitaxial layer.

[0006] Specifically, the PW region, the N+ region and the P+ region have the same potential.

[0007] Specifically, in step S600, a pair of gate trench regions are provided, which are respectively located on both sides of the source polysilicon, and the etching depth is equal to the depth of the source trench region.

[0008] Specifically, in step S600, the isolation dielectric layer a is connected to the source polysilicon, the top surface is connected to the N-epitaxial layer, and the bottom is connected to the gate oxide layer.

[0009] Specifically, in step S700, it is assumed that the isolation dielectric layer b is provided in pair, and two ends thereof are respectively placed on the upper end of the N+ region and the isolation dielectric layer a.

[0010] Specifically, the concentration range of the P+ region is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

[0011] Specifically, the etching depth of the source trench region is 1.8um-2um.

[0012] Specifically, the etching depth of the gate trench region is 1.8um-2um.

[0013] A trench SiC MOSFET device with an integrated reverse freewheeling diode comprises an N+ substrate layer, an N-epitaxial layer, a PW region, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; The PW area is provided with: A P-shield region extending downward from the top surface of the PW region into the N-epitaxial layer; A pair of N+ regions are provided, located on both sides of the P-shield region, respectively extending downward from the top surface of the PW region, and having a spacing from the bottom surface of the PW region; A pair of P+ regions are provided, each extending downward from the top surface of the PW region and connected to the N+ region; Source polysilicon extending downward from the top surface of the P-shield region; A pair of gate trench regions are provided, each of which is etched downward from the top surface of the PW region; A gate oxide layer, located at the side and bottom of the gate trench region, the side of which is respectively connected to the N+ region and the PW region, and the bottom of which is respectively connected to the P-shield region and the source polysilicon; An isolation dielectric layer a is located in the gate trench region, with a bottom surface connected to the gate oxide layer and a side surface connected to the source polysilicon; A Poly layer, filled between the gate oxide layer and the isolation dielectric layer a; A pair of isolation dielectric layers b are provided, and the bottom surfaces are respectively connected to the N+ region, the gate oxide layer, the Poly layer and the isolation dielectric layer a; The ohmic contact alloy layer is provided with a pair, which are respectively located at the sides of the isolation dielectric layer b, and the bottom surfaces are respectively connected to the N+ region and the P+ region; Specifically, the bottom surface of the front electrode metal layer is respectively connected to the ohmic contact alloy layer, the isolation dielectric layer b, the isolation dielectric layer a and the source polysilicon.

[0014] The heterojunction diode composed of the source polysilicon and the P-shield region of the present invention shares the current flowing through the body diode when the device is reversely conducted, reducing the freewheeling loss. The forward conduction voltage of the freewheeling diode is lower than that of the parasitic PN junction diode of the device, so the freewheeling diode will be turned on in advance, reducing the risk of bipolar degradation of the device, thereby improving the reverse freewheeling capability of the device. At the same time, the P-shield region is arranged below the gate oxide layer, which can suppress the impact of the gate oxide of the peak electric field and improve the reliability problem of the gate oxide layer of the trench SiC MOSFET. The structure of this case reduces the overlapping area of ​​the gate and the drain, thereby achieving the purpose of reducing the gate-drain capacitance, shortening the Miller platform time, and then improving the switching performance of the device and reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 , Figure 2 is a structural diagram of step S100 of the present invention; Figure 3 is a structural diagram of step S200 of the present invention; Figure 4 is a structural diagram of step S300 of the present invention; Figure 5 is a structural diagram of step S400 of the present invention; Figure 6 is a structural diagram of forming a source trench region in step S500 of the present invention; Figure 7 It is a structural diagram of forming source polysilicon in step S500 of the present invention; Figure 8 is a structural diagram of step S600 of the present invention; Fig. 9 It is a structural diagram of preparing a gate oxide layer in step S600 of the present invention; Fig.10 is a structural diagram of preparing the isolation dielectric layer a in step S600 of the present invention; Fig.11 It is a structural diagram of preparing a Poly layer in step S600 of the present invention; Fig.12 is a structural diagram of preparing the isolation dielectric layer b in step S700 of the present invention; Fig.13 is a structural diagram of preparing an ohmic contact alloy layer in step S700 of the present invention; Fig.14 is a structural diagram of preparing a front electrode metal layer in step S700 of the present invention; In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the PW region, 4 is the P-shield region, 5 is the N+ region, 6 is the P+ region, 7 is the source trench region, 8 is the source polysilicon, 9 is the gate trench region, 10 is the gate oxide layer, 11 is the isolation dielectric layer a, 12 is the Poly layer, 13 is the isolation dielectric layer b, 14 is the ohmic contact alloy layer, and 15 is the front electrode metal layer. DETAILED DESCRIPTION

[0016] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0017] A method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode comprises the following steps: S100, such as Figure 1 As shown, an N-epitaxial layer 2 is formed by epitaxial growth on an N+ substrate layer 1, and a PW region 3 is formed on the top of the N-epitaxial layer 2 by ion implantation; Specifically, the concentration range of PW zone 3 is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um, such as Figure 2 As shown; S200, such as Figure 3 As shown, Al ions are implanted downward from the top of the PW region 3 multiple times to form a P-shield region 4 with a concentration of 1E 18 -1E 19 cm -2, the injection depth is 2.2-2.5um; S300, such as Figure 4 As shown, SiO 2 As a mask, N ions are implanted multiple times in the PW region 3 to form an N+ region 5 with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um, and RCA cleaning is performed after the injection is completed; S400, such as Figure 5 As shown, SiO 2 As a mask, Al ions are implanted multiple times in the PW region 3 to form a P+ region 6 with a concentration range of 1E 18 cm -2 -1E 19 cm -2 The implantation depth is 0.4-0.8um. ​​After the implantation is completed, the mask is removed. Then a thin layer of graphite is deposited on the surface of the device as protection. It is annealed at a high temperature of 1650℃-1690℃ for 15 minutes to activate the implanted ions. The PW region 3, the N+ region 5 and the P+ region 6 have the same potential, which can enhance the voltage resistance and short-circuit tolerance of the device.

[0018] S500, such as Figure 6 As shown, etching is extended downward from the top of the P-shield region 4 to form a source trench region 7, and the etching depth is 1.8um-2um; Figure 7 As shown, a photoresist is used as a mask to deposit source polysilicon 8 in the source trench region 7; S600, such as Figure 8 As shown, etching is extended downward from the top of the PW region 3 to form a gate trench region 9, and the etching depth is 1.8um-2um; Fig. 9 As shown, a gate oxide layer 10 is grown on the far side wall and bottom of the gate trench region 9 by dry oxygen thermal oxidation method, with a growth thickness of 40-60nm, and annealed in a NO atmosphere at a temperature of 1250°C for 1H to improve the compactness of the gate oxide layer and reduce defects; as shown Fig.10 As shown, an isolation dielectric layer a11 is deposited on the other side wall of the gate trench region 9; Fig.11 As shown, polysilicon is then deposited in the gate trench region 9 by LPCVD to form a Poly layer 12, which is used as a gate electrode lead; A pair of gate trench regions 9 are provided, which are respectively located on both sides of the source polysilicon 8 , and the etching depth is equal to the depth of the source trench region 7 .

[0019] S700 , sequentially preparing an isolation dielectric layer b13 , an ohmic contact alloy layer 14 and a front electrode metal layer 15 on the N-epitaxial layer 2 .

[0020] A pair of isolation dielectric layers b13 are provided, and two ends thereof are respectively overlapped on the upper ends of the N+ region 5 and the isolation dielectric layer a11, and the overlap distance is adjusted according to the actual process.

[0021] Specifically, Fig.12 As shown, an isolation dielectric layer b13 is formed on the N-epitaxial layer 2 by depositing oxide; Fig.13 As shown, an ohmic metal layer is formed on the N-epitaxial layer 2 by Ni metal sputtering deposition, and then annealed at a high temperature of 1000° C. for 5 minutes to form an ohmic contact alloy layer 14, which forms an ohmic contact with the upper parts of the N+ region 5 and the P+ region 6; Fig.14 As shown, a front electrode metal layer 15 is formed on the N-epitaxial layer 2, the isolation dielectric layer b13 and the ohmic contact alloy layer 14 by Al metal sputtering to serve as a source electrode lead.

[0022] A trench SiC MOSFET device with an integrated reverse freewheeling diode comprises an N+ substrate layer 1, an N-epitaxial layer 2, a PW region 3, an ohmic contact alloy layer 14 and a front electrode metal layer 15 arranged in sequence from bottom to top; The PW area 3 is provided with: A P-shield region 4 extending downward from the top surface of the PW region 3 into the N-epitaxial layer 2; A pair of N+ regions 5 are provided, located on both sides of the P-shield region 4, respectively extending downward from the top surface of the PW region 3, and having a spacing from the bottom surface of the PW region 3; the depth of the N+ region 5 is less than the depth of the P-shield region 4; A pair of P+ regions 6 are provided, each extending downward from the top surface of the PW region 3 and connected to the N+ region 5; the depth of the N+ region 5 is equal to the depth of the P+ region 6; The source polysilicon 8 extends downward from the top surface of the P-shield region 4 and is spaced apart from the bottom surface of the P-shield region 4; the source polysilicon 8 is located in the P-shield region 4; A pair of gate trench regions 9 are provided, each of which is etched downward from the top surface of the PW region 3; The gate oxide layer 10 is located at the side and bottom of the gate trench region 9, and the side is respectively connected to the N+ region 5 and the PW region 3, and the bottom is respectively connected to the P-shield region 4 and the source polysilicon 8; An isolation dielectric layer a11 is located in the gate trench region 9, with its bottom surface connected to the gate oxide layer 10 and its side connected to the source polysilicon 8; Poly layer 12, filled between the gate oxide layer 10 and the isolation dielectric layer a11; The top surfaces of the gate oxide layer 10, the isolation dielectric layer a11 and the Poly layer 12 are respectively on the same plane; A pair of isolation dielectric layers b13 are provided, and the bottom surfaces are respectively connected to the N+ region 5, the gate oxide layer 10, the Poly layer 12 and the isolation dielectric layer a11; The ohmic contact alloy layer 14 is provided with a pair, which are respectively located at the sides of the isolation dielectric layer b13, and the bottom surfaces are respectively connected to the N+ region 5 and the P+ region 6; The bottom surface of the front electrode metal layer 15 is connected to the ohmic contact alloy layer 14, the isolation dielectric layer b13, the isolation dielectric layer a11 and the source polysilicon 8 respectively.

[0023] The heterojunction diode formed by the source polysilicon 8 and the P-shield region 4 of the present invention shares the current flowing through the body diode when the device is reversely conducted, reducing the freewheeling loss. The forward conduction voltage of the freewheeling diode is lower than that of the parasitic PN junction diode of the device, so the freewheeling diode will be turned on in advance, reducing the risk of bipolar degradation of the device, thereby improving the reverse freewheeling capability of the device. At the same time, the P-shield region 4 is arranged below the gate oxide layer 10, which can suppress the impact of the gate oxide of the peak electric field and improve the reliability problem of the gate oxide layer of the trench SiC MOSFET.

[0024] The structure of this case reduces the overlapping area between the gate and the drain, thereby achieving the purpose of reducing the gate-drain capacitance, shortening the Miller platform time, and further improving the switching performance of the device and reducing switching losses.

[0025] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode, characterized in that: The steps include: S100, epitaxially growing an N-epitaxial layer (2) on an N+ substrate layer (1), and forming a PW region (3) on top of the N-epitaxial layer (2) by ion implantation; S200, Al ions are implanted downward from the top of the PW region (3) multiple times to form a P-shield region (4); S300, N ions are implanted multiple times in the PW region (3) to form an N+ region (5); S400, Al ions are implanted multiple times in the PW region (3) to form a P+ region (6); S500, etching is performed downwardly from the top of the P-shield region (4) to form a source trench region (7); and source polysilicon (8) is deposited in the source trench region (7); S600, etching is performed downward from the top of the PW region (3) to form a gate trench region (9); a gate oxide layer (10) is grown on a far side wall and a bottom of the gate trench region (9); an isolation dielectric layer a (11) is deposited on the other side wall of the gate trench region (9); and a Poly layer (12) is formed in the gate trench region (9) to serve as a gate electrode lead; S700, sequentially preparing an isolation dielectric layer b (13), an ohmic contact alloy layer (14) and a front electrode metal layer (15) on the N-epitaxial layer (2).

2. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: The PW region (3), the N+ region (5) and the P+ region (6) have the same potential.

3. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: In step S600, a pair of gate trench regions (9) are provided, which are respectively located on two sides of the source polysilicon (8), and the etching depth is equal to the depth of the source trench region (7).

4. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: In step S600, the isolation dielectric layer a (11) is connected to the source polysilicon (8), the top surface is connected to the N-epitaxial layer (2), and the bottom is connected to the gate oxide layer (10).

5. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: In step S700, it is assumed that the isolation dielectric layer b (13) is provided in pair, with two ends thereof respectively resting on the upper ends of the N+ region (5) and the isolation dielectric layer a (11).

6. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: The concentration range of the P+ region (6) is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

7. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: The etching depth of the source trench region (7) is 1.8um-2um.

8. The method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to claim 1, characterized in that: The etching depth of the gate trench region (9) is 1.8um-2um.

9. A trench SiC MOSFET device with an integrated reverse freewheeling diode, prepared by the method for preparing a trench SiC MOSFET device with an integrated reverse freewheeling diode according to any one of claims 1 to 8, characterized in that: It comprises an N+ substrate layer (1), an N- epitaxial layer (2), a PW region (3), an ohmic contact alloy layer (14) and a front electrode metal layer (15) which are arranged in sequence from bottom to top; The PW area (3) is provided with: A P-shield region (4) extending downward from the top surface of the PW region (3) into the N-epitaxial layer (2); A pair of N+ regions (5) are provided, located on both sides of the P-shield region (4), respectively extending downward from the top surface of the PW region (3), and having a spacing with the bottom surface of the PW region (3); A pair of P+ regions (6) are provided, each extending downward from the top surface of the PW region (3) and connected to the N+ region (5); A source polysilicon (8) extending downward from the top surface of the P-shield region (4); A pair of gate trench regions (9) are provided, each of which is etched downward from the top surface of the PW region (3); A gate oxide layer (10) is located on the side and bottom of the gate trench region (9), the side being connected to the N+ region (5) and the PW region (3) respectively, and the bottom being connected to the P-shield region (4) and the source polysilicon (8) respectively; An isolation dielectric layer a (11), located in the gate trench region (9), with a bottom surface connected to the gate oxide layer (10) and a side surface connected to the source polysilicon (8); A Poly layer (12) filled between the gate oxide layer (10) and the isolation dielectric layer a (11); A pair of isolation dielectric layers b (13) are provided, and the bottom surfaces are respectively connected to the N+ region (5), the gate oxide layer (10), the Poly layer (12) and the isolation dielectric layer a (11); The ohmic contact alloy layer (14) is provided in pair and is respectively located on the side of the isolation dielectric layer b (13), and the bottom surfaces are respectively connected to the N+ region (5) and the P+ region (6).

10. The trench SiC MOSFET device with integrated reverse freewheeling diode according to claim 9, characterized in that: The bottom surface of the front electrode metal layer (15) is respectively connected to the ohmic contact alloy layer (14), the isolation dielectric layer b (13), the isolation dielectric layer a (11) and the source polysilicon (8).

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