CIM circuit for random computing and MAC circuit for machine learning training

Abstract

The present invention belongs to the field of integrated circuits, and specifically relates to a CIM circuit for random calculation and a MAC operation circuit suitable for machine learning training, the circuit comprising: a storage and calculation array, a random quantization circuit, and a peripheral circuit. Among them, the storage and calculation array adopts an SRAM array with data storage and logic operation functions. The random quantization circuit comprises a random voltage generator, a twin comparator array, a random accumulation circuit and a transcoding circuit. The random voltage generator generates a random voltage, the twin comparator array uses the random voltage to generate a random bit stream of the operation result output by the SRAM array, the random accumulation circuit realizes the accumulation of the product result in the random domain according to each random bit stream; the transcoding circuit transcodes the random bit stream of the final result into a corresponding numerical value. The present invention also introduces a transposition design to achieve more efficient full parallel operation. The present invention solves the problems of low area efficiency and high power consumption in various existing CIM circuits using full adders.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and specifically relates to a CIM circuit for random computing, a random quantization circuit, a MAC operation circuit suitable for machine learning training, and an accelerator chip. Background Art

[0002] With the continuous advancement and development of AI technology, edge computing devices (such as embedded systems, IoT devices, edge servers, etc.) are playing an increasingly important role in processing and analyzing data, making real-time intelligent decisions, etc. Edge computing devices can deploy computing resources and intelligent algorithms directly near the data source, reducing data transmission delays and bandwidth requirements, and improving system response speed and efficiency, which is crucial for many intelligent applications that require real-time processing (such as smart cities, autonomous driving, industrial automation, medical diagnosis, etc.).

[0003] The von Neumann architecture is the foundation of modern computer architecture. It divides the computing system into three main parts: the central processing unit (CPU), memory, and input / output devices (I / O devices). In this architecture, the CPU is responsible for executing instructions, while the data is stored in the memory. The CPU and memory are separated. When calculating, the CPU needs to continuously read data from the memory and process it, and then write the results back to the memory. However, with the increase in computing needs, frequent data migration has led to the bottleneck of the von Neumann architecture. Especially when facing big data and artificial intelligence applications, the problem of data movement cost and processor-memory speed mismatch has become more prominent.

[0004] In order to solve the problem caused by the von Neumann bottleneck, Computing In-Memory (CIM) came into being. Computing In-Memory is a technology that closely combines computing and storage. It performs computing tasks directly inside the memory instead of moving data back and forth between the processor and the memory. This method can effectively reduce the delay and energy consumption of data transmission and greatly improve computing efficiency, especially in application scenarios that require large amounts of data processing, such as artificial intelligence, big data analysis, and machine learning. By closely combining computing and storage, in-memory computing provides an effective solution that can greatly improve the performance, energy efficiency, and response speed of computing systems, and will become one of the important technical directions for future intelligent edge computing devices and efficient data processing.

[0005] Multiply-accumulate (MAC) operations are the most common type of logic operations in artificial intelligence algorithms. In the existing CIM architecture, the circuits that implement MAC operations are mainly divided into two technical paths, such as Figure 1As shown in the figure, they are analog in-memory computing (AnalogCIM) and digital in-memory computing (Digital CIM). In the analog in-memory computing circuit, in order to realize the multiplication and accumulation operation, the overhead brought by the adc part of the quantization circuit is too large. In digital in-memory computing, there is no need to use adc for quantization, but multiplication is realized through the bit operation of the unit, and then accumulation is performed through the addition tree. However, the adder tree composed of full adders occupies most of the area and power consumption in the circuit. It may even lead to a decrease in calculation accuracy. Summary of the invention

[0006] In order to solve the problem that the circuit of the existing CIM architecture relies on an adder tree composed of full adders when performing MAC operation, which leads to low area efficiency and high power consumption of the circuit, the present invention provides a CIM circuit for random calculation and a MAC operation circuit suitable for machine learning training.

[0007] The technical solution provided by the present invention is:

[0008] A CIM circuit for random calculation is designed based on an SRAM circuit and includes a storage and calculation array, a random quantization circuit, and a peripheral circuit. The storage and calculation array uses an SRAM array with data storage and logic operation functions; the storage and calculation array is composed of a plurality of storage and calculation unit arrays. Each storage and calculation unit in the storage and calculation array is used to perform multiplication operations, and the multiplication results are represented and outputted through the bit line voltage of the corresponding column.

[0009] The random quantization circuit includes a random voltage generator, a twin comparator array, a random accumulation circuit and a transcoding circuit. The random voltage generator is used to generate a random voltage SV; SV is a random step-shaped square wave signal containing the full range of the quantization result. The twin comparator array is composed of multiple groups of twin comparators; the twin comparator obtains the bit line voltage of the read bit line BL or BLB of each storage unit in the storage array, and compares it with the random voltage SV, thereby obtaining a random bit stream representing the multiplication result output by each storage unit in the storage array. The random bit stream is an n-bit binary signal, in which the probability of the high level contained corresponds to the value size. The random accumulation circuit uses the random bit streams of each multiplication result to perform accumulation operations in the random domain, thereby obtaining a random bit stream of the MAC operation result. The transcoding circuit is used to transcode the random bit stream of the MAC result into a corresponding value and output it.

[0010] The peripheral circuit includes other circuit modules related to realizing data storage and logic operation functions.

[0011] As a further improvement of the present invention, the random voltage generator is composed of a split capacitor voltage digital-to-analog converter CDAC, a linear feedback shift register LFSR, and a logic encoding circuit.

[0012] Among them, CDAC consists of 2n-2 pairs of capacitors with the value of 1:2:…:2 n-2 The upper plates of all capacitors are connected to the output signal line; one end of the output signal line is connected to the half-scale signal VCM through a switch, and the other end is used as the output port of the random signal SV. The n capacitor values ​​are arranged in the order of 1:2:…:2 n-2 The lower substrate of the distributed capacitor is connected to the first input signal line through n first transmission gates respectively; the other n capacitor values ​​are arranged in the order of 1:2:…:2 n-2 The lower substrate of the distributed capacitor is connected to the second input signal line through n second transmission gates. The first input signal line and the second input signal line are connected to the upper limit voltage VMAX and the lower limit voltage VMIN of the range respectively.

[0013] LFSR is used to scramble the order of the step voltages in the input random signal SV. <0> ~D <n-1>Generate a set of control code Q <0> ~Q <n-1>The logic coding circuit is used to control the Q <0> ~Q <n-1>n-1 pairs of mutually inverted control signals SP and SN for switching the switching states of the respective first transmission gates and second transmission gates are generated.

[0014] As a further improvement of the present invention, the linear feedback shift register is composed of n D flip-flops, a PMOS tube and 2n NMOS tubes. Among them, the PMOS tube is used as a control tube, and every two NMOS tubes constitute a branch tube. The D flip-flops are cascaded with each other, and the Q end of the higher-level D flip-flop is connected to the D end of the lower-level D flip-flop. The D end of the highest-level D flip-flop is connected to the power supply through the control tube, and the gate of the control tube is connected to the pre-charge signal PRE; the clock port of each D flip-flop is connected to the clock signal CLK. The branch tube corresponds to each D flip-flop one by one; each branch tube is composed of N1 and N2. In each branch tube, the drain of N1 is connected to the D end of the highest-level D flip-flop; the source of N1 is connected to the drain of N2; the source of N2 is grounded; the gate of N1 is respectively connected to the garbled D <0> ~D <n-1>; The gate of N2 is connected to the Q end of the D flip-flop of the corresponding stage.

[0015] As a further improvement of the present invention, the logic coding circuit is composed of n-1 groups of coding units; each coding unit is composed of an XOR gate and an inverter. The input end of the inverter is connected to the output end of the XOR gate; one of the inputs of the XOR gate of each coding unit is all Q <n-1>, and the other input is Q <0> ~Q <n-2>The output signal of the XOR gate in each coding unit is used as the control signal SP and connected to the gate of each first transmission gate in CDAC. The output signal of the inverter in each coding unit is used as the control signal SN and connected to the gate of each second transmission gate in CDAC.

[0016] As a further improvement of the present invention, the twin comparator is composed of a first-level preselector LineSwitch1 and two comparators COMP1 and COMP2. Two input terminals of LineSwitch1 are connected to SV, and the other two input terminals are connected to BL and BLB respectively. The four output terminals of LineSwitch1 are connected to the input terminals of COMP1 and COMP2 respectively.

[0017] In data storage mode, LineSwitch1 connects BL and BLB to COMP1, and connects two SVs to COMP2. At this time, COMP1 works and COMP2 does not work, thereby implementing a dual-bit-line read operation in COMP1. In logic operation mode, LineSwitch1 connects BL and SV to COMP1, and connects BLB and SV to COMP2, thereby using two comparators to read out product operation results with different signs output on different read bit lines.

[0018] As a further improvement of the present invention, the random accumulation circuit includes multiple XOR gates, multiple secondary preselectors LineSwitch2 and tertiary preselectors LineSwitch3, multiple multiple-to-one selectors MUX1, MUX2, MUX3, and a sign bit register array.

[0019] Among them, the sign bit register array is composed of multiple D flip-flops, and the D flip-flops correspond one-to-one to the twin comparators used in the circuit; the sign bit register array can be used to store the sign corresponding to each multiplication result output by the front-end twin comparator.

[0020] The two output ends of each twin comparator are connected to the input ends of an XOR gate, which is used to output the absolute value of the sum of the positive and negative results calculated on the connected read bit lines BL and BLB; the sign of the sum result is stored in a corresponding D flip-flop in the sign bit register array.

[0021] The outputs of some XOR gates are connected to the inputs of LineSwitch2; a part of the outputs of each LineSwitch2 is connected to the inputs of MUX1, and the other part of the outputs is connected to the inputs of MUX2. LineSwitch2 performs weighted accumulation of positive and negative values ​​in MUX1 and MUX2 respectively according to the signs of the operation results pre-stored in the sign bit register array, thereby realizing multi-bit multiplication;

[0022] The outputs of each MUX1 and MUX3 are connected to the input of LineSwitch3. The output of LineSwitch3 is connected to the transcoding circuit through some XOR gates to achieve transcoding output of the multi-bit multiplication results. On the other hand, it is connected to the transcoding circuit through MUX3 to accumulate the multi-bit multiplication results output by multiple LineSwitch2s and then transcode them for output, thus achieving multi-bit signed number MAC operation.

[0023] The present invention also includes a random quantization circuit, which uses all or part of the random voltage generator, twin comparator array, random accumulation circuit and transcoding circuit included in the random quantization circuit provided in the aforementioned random calculation CIM circuit.

[0024] The present invention also includes a MAC operation circuit suitable for machine learning training, which adopts the architecture of the CIM circuit of random calculation as described above. The SRAM array in the CIM circuit of random calculation is composed of a plurality of SRAM cell arrays, and each SRAM cell is an 8T-SRAM cell using a transposed split word line. Therefore, the SRAM array includes split word lines WLL, WLR and read bit lines BL, BLB; and transposed word lines TWLL, TWLR and transposed bit lines TBL, TBLB.

[0025] In the MAC operation circuit suitable for machine learning training, an independent random quantization circuit is set on the rows and columns of the SRAM array. In the inference task, the activation data is input horizontally through WLL and WLR and accumulated vertically through BL and BLB; in the training task, the loss value is input vertically through TWLL and TWLR and accumulated horizontally through TBL and TBLB.

[0026] In the MAC operation circuit suitable for machine learning training provided by the present invention, each 8T-SRAM unit of the transposed separated word line is composed of 2 PMOS tubes and 6 NMOS tubes. Among them, 2 PMOS tubes and 2 NMOS tubes are anti-coupled to form a latch structure with storage nodes Q and QB. The remaining 4 NMOS tubes are used to connect Q with BL, QB with BLB, Q with TBL, and QB with TBLB. The gates of each NMOS tube are connected to WLL, WLR, TWLL and TWLR.

[0027] As a further improvement of the present invention, each 8T-SRAM unit is used to perform a multiplication operation between a signed input number and a signed two-bit weight.

[0028] When performing a multiplication task, the sign bit of the weight is pre-read to determine which word line should be activated: if the weight is positive, WLL or TWLL is activated; if it is negative, WLR or TWLR is activated; the weight is pre-stored in the storage node in the form of an inverse code. The value of the input number is encoded by the pulse width of the activated WLL, TWLL, WLR or TWLR; when the input number has different signs, it is processed sequentially in two adjacent cycles. The product of the input number and the weight is reflected in the bit line voltage of BL, BLB, TBL or TBLB.

[0029] The present invention also includes an accelerator chip, which uses the MAC operation circuit suitable for machine learning training as described above.

[0030] The technical solution provided by the present invention has the following beneficial effects:

[0031] The present invention proposes a new CIM circuit architecture that uses random quantization technology to implement MAC operations. This new digital-analog hybrid TSCIM solution successfully combines the advantages of binary computing and random computing, achieving a balance between the two. This combination not only improves computing efficiency, but also significantly reduces the required hardware resources.

[0032] The present invention further optimizes the circuit design by using 8T-SRAM cells with transposed separated word lines and column-level random quantization circuits and row-level random quantization circuits, thereby enabling the circuit to support variable precision operations. In addition, combined with efficient sequential logic design, it ensures that the array realizes full parallel computing, achieves optimal performance, and avoids the delay and power consumption bottlenecks in traditional methods.

[0033] In addition, the circuit design scheme provided by the present invention can achieve higher data throughput and higher precision multiplication and accumulation operations. The random calculation introduced therein enables the circuit to reduce the PVT interference suffered by the analog calculation, thereby reducing the calculation error. The present invention also uses MOM capacitors as sampling circuits on the diagonal corners of the SRAM array to achieve multiplexing of a set of sampling capacitors in the horizontal and vertical directions to further reduce the area cost of the circuit.

[0034] The TSCIM circuit proposed in the present invention performs excellently in terms of energy efficiency and area utilization, and can therefore be used to accelerate the training and efficient reasoning of neural networks, providing strong support for edge devices and high-performance computing applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the analog in-memory computing and digital in-memory computing pointed out in the background technology figure of the present invention.

[0036] Figure 2 This is a comparison diagram of the quantization principle of the random quantization strategy adopted in Example 1 of the present invention and the existing SS-ADC and SAR-ADC.

[0037] Figure 3 This is a circuit schematic diagram of a random quantization circuit used in a CIM circuit for random calculation provided in Embodiment 1 of the present invention.

[0038] Figure 4 This is a circuit diagram of a random voltage generator provided in Example 1 of the present invention.

[0039] Figure 5 This is a comparison table of the logical functions of AND gates, XOR gates, and binary selectors in the random domain.

[0040] Figure 6 This is a circuit diagram of a word line driving circuit used in a CIM circuit for random calculation provided in Embodiment 1 of the present invention.

[0041] Figure 7 This is a circuit diagram of a random quantization circuit that can realize independent operation and is provided in Embodiment 2 of the present invention.

[0042] Figure 8 This is a circuit architecture diagram of a MAC operation circuit suitable for machine learning training provided in Embodiment 3 of the present invention.

[0043] Fig. 9 for Figure 8 Circuit diagram of an 8T-SRAM cell with transposed split word lines used in the circuit architecture shown.

[0044] Fig.10 A state diagram of the storage and calculation array of the circuit provided in Example 3 of the present invention performing logic operations.

[0045] Fig.11 This is a local layout design of a circuit module used in the accelerator chip provided in Example 3 of the present invention.

[0046] Fig.12 The figure is a variation curve between the discharge voltage △V and the discharge time of the solution of the present invention in a simulation test.

[0047] Fig.13 This is a variation curve between the discharge voltage △V and the number of activated rows in the solution of the present invention in a simulation test.

[0048] Fig.14 This is a comparison chart of the circuit scheme of the present invention and the control group using an adder tree of full adders in terms of area, power consumption and delay performance in a simulation test.

[0049] Fig.15 The figure is a diagram showing the relationship between the circuit energy efficiency of the solution of the present invention and the sparsity of the input in the simulation test.

[0050] Fig.16 The figure is a diagram showing the relationship between the circuit energy efficiency and the supply voltage of the solution of the present invention in a simulation test.

[0051] Fig.17 The figure is a signal timing diagram of the circuit of the present invention when implementing full array parallel computing in a simulation test. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] Example 1

[0054] In order to solve the problem that the MAC operation in the existing CIM architecture circuit is overly dependent on the adder tree composed of full adders, which leads to the problem that the power consumption and area efficiency of the circuit cannot reach the expected level. This embodiment provides a new architecture for processing MAC operations based on stochastic quantization. Specifically, the circuit provided in this embodiment no longer uses the SS-ADC or SAR-ADC in the traditional circuit to quantize the multiplication operation results of each unit in the storage array, but uses a new stochastic quantization circuit (Stochastic-ADC). Figure 2 As shown, the stochastic quantization circuit can quantize the analog signal of the multiplication result into a new digital signal type, namely, a stochastic bitstream. Next, this embodiment directly uses the stochastic bitstream to perform multiplication and accumulation operations, and finally converts the final MAC operation result from the stochastic bitstream into a common decimal number.

[0055] Specifically, the process of implementing the multiplication-accumulation operation of the new circuit architecture provided in this embodiment includes three stages: in the first stage, the multiplication result of each unit is stochastically quantized (Stochastic Computing, SC) to obtain a random bit stream. Stochastic computing is another approximate computing paradigm. In stochastic computing, the quantization result is a random bit stream, and the random bit stream represents the value through the probability of "1" appearing in the signal. In the second stage, the random bit stream of the product result implements the weighted accumulation operation; in the random domain, a simple logic gate circuit can be used to implement the relatively complex multiplication-accumulation operation in the digital domain. In the third stage, the random bit stream of the MAC result is transcoded into the corresponding decimal or binary number.

[0056] Compared with the MAC circuit of the traditional CIM architecture, the new circuit architecture of this embodiment will extend the clock cycle of task processing to a certain extent during the random quantization process in the first stage. However, in the second stage, the solution of this embodiment uses a full adder composed of a two-to-one selector and an XOR gate when performing weighted summation of multiple multiplication results using a random bit stream; instead of the adder tree composed of full adders that is relied upon when implementing weighted summation operations in conventional digital circuits. This makes the circuit area of ​​the part performing the accumulation operation in the circuit of this embodiment significantly smaller than that of the existing circuit, and the overall power consumption performance of the circuit of this embodiment is also better; therefore, when processing data processing tasks involving a large number of MAC operations, the technical solution provided by this embodiment has obvious advantages.

[0057] Specifically, the new CIM-based MAC operation circuit provided in this embodiment is called a random calculation CIM circuit, which is based on the SRAM circuit design, and the circuit includes: a storage and calculation array, a random quantization circuit, and a peripheral circuit. Among them, like most CIM circuits, the storage and calculation array in this circuit adopts an SRAM array with data storage and logic operation functions; the storage and calculation array is composed of a plurality of storage and calculation unit arrays. Each storage and calculation unit in the storage and calculation array is used to perform multiplication operations, and the multiplication results are characterized and output by the bit line voltage of the corresponding column. The peripheral circuit includes other circuit modules related to realizing data storage and logic operation functions; such as a mode switching unit, a precharge circuit, a word line drive circuit, an input coding unit, and the like.

[0058] like Figure 3 As shown, in the CIM circuit of random calculation provided in this embodiment, the random quantization circuit includes a stochastic voltage generator (SVG), a twin comparator array (TCA), a stochastic accumulator circuit (SAC) and a transcoding circuit (CNT).

[0059] The random voltage generator is used to generate a random voltage SV. Specifically, Figure 2 It can be found that SS-ADC quantizes the measured signal of the calculation result through a ramp signal. The ramp signal is a voltage signal with a fixed slope and continuous growth. When the ramp signal and the measured signal are input into the comparator at the same time, the output of the comparator will flip when the voltage of the ramp signal exceeds the measured signal, thereby completing the quantization. SAR-ADC quantizes the measured signal of the calculation result through a step signal with a gradient descent. When the step signal and the measured signal are input into the comparator at the same time, the output of the comparator will flip when the voltage of the ramp signal exceeds the measured signal, thereby completing the quantization. The random quantization process of this embodiment quantizes the measured signal of the calculation result through a random voltage SV. The random voltage SV is similar to the step signal used in SAR-ADC. Both contain multiple different level states corresponding to all quantization results of the full range. The difference is that the level state of the step signal in SAR-ADC is gradient descending (can also be designed as gradient ascending), that is, it appears sequentially, while the different level states in the random voltage SV appear out of order; in short, the random voltage SV is actually a disordered step-like square wave signal containing the full range of the quantization result.

[0060] A specific circuit implementation of the present embodiment that can generate the required random voltage SV is described below:

[0061] like Figure 4 As shown, the random voltage generator provided in this embodiment can be composed of a split capacitor voltage digital-to-analog converter CDAC, a linear feedback shift register LFSR, and a logic encoding circuit. Among them, CDAC is composed of 2n-2 pairs of capacitor values ​​according to 1:2:…:2 n-2 The distributed capacitors are composed of n and the number of bits of the random bit stream that needs to be quantized. For example, Figure 4 That is, the circuit is drawn based on the SV required to generate a 4-bit random bit stream. When n=4, the capacitor array in CDAC consists of 6 capacitors. The upper plates of all capacitors in CDAC are connected to the output signal line; one end of the output signal line is connected to the half-scale signal VCM through a switch, and the other end is used as the output port of the random signal SV. The n capacitor values ​​are in the order of 1:2:…:2 n -2 The lower substrate of the distributed capacitor is connected to the first input signal line through n first transmission gates respectively; the other n capacitor values ​​are arranged in the order of 1:2:…:2 n-2 The lower substrate of the distributed capacitor is connected to the second input signal line through n second transmission gates. The first input signal line and the second input signal line are connected to the upper limit voltage VMAX and the lower limit voltage VMIN of the range respectively.

[0062] Combining the circuit principle of the above CDAC, it can be known that when the lower plate of each capacitor switches between the first signal line or the second signal line, the SV port of the output signal line will be able to obtain outputs of different level states. The LFSR and logic encoding circuit in the random voltage generator are the relevant circuits for switching the connection relationship between the lower plate of the capacitor and the two input signal lines. Specifically, the LFSR is used to generate a random signal according to the scrambled code D representing the order of each step voltage in the input random signal SV. <0> ~D <n-1>Generate a set of control code Q <0> ~Q <n-1>The logic coding circuit is used to control the Q <0> ~Q <n-1>n-1 pairs of mutually inverted control signals SP and SN for switching the switching states of the respective first transmission gates and second transmission gates are generated.

[0063] In this embodiment, the scrambled code is a codeword that can be edited independently by a technician, and the codeword is used to determine the order in which each level state appears in the SV. In order to realize the generation of the corresponding control code using the scrambled code, a typical linear feedback shift register provided in this embodiment can be composed of n D flip-flops, a PMOS tube and 2n NMOS tubes. Among them, the PMOS tube is used as a control tube, and every two NMOS tubes constitute a branch tube. Each D flip-flop is cascaded with each other, and the Q end of the higher-level D flip-flop is connected to the D end of the lower-level D flip-flop. The D end of the highest-level D flip-flop is connected to the power supply through the control tube, and the gate of the control tube is connected to the pre-charge signal PRE; the clock port of each D flip-flop is connected to the clock signal CLK. The branch tube corresponds to each D flip-flop one by one; each branch tube is composed of N1 and N2. In each branch tube, the drain of N1 is connected to the D end of the highest-level D flip-flop; the source of N1 is connected to the drain of N2; the source of N2 is grounded; the gate of N1 is respectively connected to the scrambled code D <0> ~D <n-1>; The gate of N2 is connected to the Q end of the D flip-flop of the corresponding stage.

[0064] Correspondingly, the logic encoding circuit provided in this embodiment can be composed of n-1 groups of encoding units; each encoding unit is composed of an XOR gate and an inverter. The input end of the inverter is connected to the output end of the XOR gate; one of the inputs of the XOR gate of each encoding unit is all Q <n-1>, and the other input is Q <0> ~Q <n-2>The output signal of the XOR gate in each coding unit is used as the control signal SP and connected to the gate of each first transmission gate in CDAC. The output signal of the inverter in each coding unit is used as the control signal SN and connected to the gate of each second transmission gate in CDAC.

[0065] When additional emphasis is needed, Figure 4 The circuit diagram provided is only a typical circuit design for generating the required random voltage SV. In other embodiments, the technician may also adjust the circuit to obtain a circuit with the same function. For example, the technician may change the circuit design of the LFSR, and then adjust the generation logic of the scrambled code and the control code. The logic encoding circuit may also be adjusted to change the encoding rule from n control codes to the required 2n-2 mutually inverted control signal groups SP and SN.

[0066] In the random quantization technology of the present embodiment, the comparator compares the random voltage SV with the signal to be measured (i.e., the voltage of the read bit lines BL and BLB connected to the storage and calculation unit), and then obtains a digital signal representing the quantization result. In SS-ADC and SAR-ADC, the ramp signal and the step signal as the reference signal are sequentially changed, so when the output of the comparator is reversed, the size of the signal to be measured can be determined. However, in the random quantization technology of the present embodiment, the different level states in the random voltage appear in disorder, and the comparator compares the relationship between each level state in the random voltage and the level state of the signal to be measured in turn, and generates a corresponding code value, and when the SV random voltage ends, the corresponding random bit stream can be obtained. In the random bit stream, the proportion of high level "1" reflects the numerical value of the signal to be measured.

[0067] On this basis, this embodiment takes into account that each column of the storage and calculation array has two bit lines, and in most circuit designs with multiplication functions with signed numbers, the bit lines on both sides are usually used to output product results with different signs. Therefore, a twin comparator composed of two comparators is used in the random quantization circuit of this embodiment to achieve synchronous quantization of the bit lines BL and BLB on both sides. Therefore, the twin comparator array TCA of this embodiment is composed of multiple groups of twin comparators; the twin comparator obtains the bit line voltage of the read bit line BL or BLB of each storage and calculation unit in the storage and calculation array, and compares it with the random voltage SV, thereby obtaining a random bit stream representing the multiplication results output by each storage and calculation unit in the storage and calculation array. The random bit stream is an n-bit binary signal, and the number of high-level bits contained therein is the value of the corresponding decimal number.

[0068] For the twin comparator used only to realize the logic operation function, only two comparators are needed. One end of the two comparators is connected to BL and BLB respectively, and the other end is connected to the random voltage SV. At this time, the two comparators can randomly quantize the bit line voltages of BL and BLB respectively. However, considering that the thermal conductive CIM circuit of this embodiment needs to realize the data storage and logic operation functions at the same time, that is, the twin comparator not only needs to read out the logic operation result, but also needs to realize the reading of the data stored in the SRAM unit. In the data reading process, it is usually necessary to connect the bit lines BL and BLB on both sides to the same comparator.

[0069] Therefore, if Figure 3 As shown, in the more optimized solution of this embodiment, in order to take into account the data reading and logic operation functions, the twin comparator is composed of a first-level preselector LineSwitch1 and two comparators COMP1 and COMP2. The first-level preselector is a four-input and four-output preselector, which can flexibly adjust the connection relationship between each input terminal and each output terminal. Two of the input terminals of LineSwitch1 in this embodiment are connected to SV, and the other two input terminals are connected to BL and BLB respectively. The four output terminals of LineSwitch1 are connected to the input terminals of COMP1 and COMP2 respectively.

[0070] In actual application, the line division strategy of the first-level preselector LineSwitch1 is as follows:

[0071] In data storage mode, LineSwitch1 connects BL and BLB to COMP1, and connects two SVs to COMP2. At this time, COMP1 works and COMP2 does not work, thereby implementing a dual-bit-line read operation in COMP1. In logic operation mode, LineSwitch1 connects BL and SV to COMP1, and connects BLB and SV to COMP2, thereby using two comparators to read out the product operation results with different signs output on different read bit lines.

[0072] The random accumulation circuit SAC uses the random bit streams of each multiplication result to perform accumulation operations in the random domain, and then obtains the random bit stream of the MAC operation result. In the random domain, AND gates, XOR gates and two-choice selectors are the main devices used to implement logical operations. The logical function table of each device is as follows: Figure 5 shown. Figure 5 The random computation logic of AND and XOR gates is shown to be affected by random number correlation (SNC). For example, when SNC is zero, an AND gate can perform an OR operation on two inputs for approximate addition. However, if low sparsity and zero correlation are not ensured, the computation results may be significantly biased. In addition, when the correlation between the selector and the input is zero, the selector MUX can perform scaled random addition without controlling the correlation between the bit streams of multiple inputs.

[0073] In this embodiment, the globally adopted random voltage SV is generated by the same random voltage generator, which corresponds to the case of SNC=1. In this state, for the two input numbers a and b, the output of the XOR gate is the absolute value of (ab). That is, the XOR gate can calculate the absolute value of the subtraction between the two input numbers. In view of this feature, the random accumulation circuit designed in this embodiment is applied to add positive and negative numbers. For the two input numbers a and b, the output of the two-choice selector is a*c+b*(1-c), where c is an adjustable coefficient. In view of this feature, the random accumulation circuit designed in this embodiment sets c to 1 / 3 or 2 / 3, thereby realizing the weighted summation of a and b, so that the weight of one is twice that of the other, which can be applied to the weighted summation of the product results of different bits in the multi-bit number and multi-bit weight multiplication. In the design process of the random accumulation circuit of this embodiment, it is necessary to consider the separate processing of positive random bit streams and negative random bit streams, and the differentiated weighting of products with different weights. Therefore, the random accumulation circuit designed in this embodiment also uses various preselectors LineSwitch to divide the outputs of the twin comparators from different sources.

[0074] Specifically, Figure 3 As shown, the random accumulation circuit includes multiple XOR gates, multiple secondary preselectors LineSwitch2 and tertiary preselectors LineSwitch3, multiple multiple-to-one selectors MUX1, MUX2, MUX3, and a sign bit register array. The sign bit register array is composed of multiple D flip-flops, and the D flip-flops correspond one to one with the twin comparators used in the circuit. The sign bit register array can be used to store the sign corresponding to each multiplication result output by the front-end twin comparator.

[0075] The two output ends of each twin comparator are connected to the input ends of an XOR gate, which is used to output the absolute value of the sum of the positive and negative results calculated on the connected read bit lines BL and BLB; the sign of the sum result is stored in a corresponding D flip-flop in the sign bit register array. The output of each XOR gate is connected to the input end of LineSwitch2. One part of the output ends of each LineSwitch2 is connected to the input ends of MUX1, and the other part of the output ends is connected to the input ends of MUX2. LineSwitch2 performs weighted accumulation of positive and negative values ​​in MUX1 and MUX2 respectively according to the signs of the operation results pre-stored in the sign bit register array, thereby realizing multi-bit multiplication.

[0076] In this part, the XOR gate is used to add the positive and negative values ​​on BL and BLB output by the twin comparator, and the addition result still has positive and negative numbers. At this time, the secondary preselector LineSwitch2 divides these data into different multiple-select selectors MUX1 and MUX2 for weighted summation according to the signs recorded in the sign bit register array. For example, MUX1 can complete the weighted summation of all positive items, that is, the multi-bit multiplication of positive results; MUX2 can complete the weighted summation of all negative items, that is, the multi-bit multiplication of negative results.

[0077] The outputs of each MUX1 and MUX3 are connected to the input of LineSwitch3. The output of LineSwitch3 is connected to the transcoding circuit through some XOR gates to achieve transcoding output of the multi-bit multiplication results. On the other hand, it is connected to the transcoding circuit through MUX3 to accumulate the multi-bit multiplication results output by multiple LineSwitch2s and then transcode them for output, thus achieving multi-bit signed number MAC operation.

[0078] Finally, the transcoding circuit CNT is used to transcode the random bit stream of the MAC result into a corresponding numerical value and output it. The process of transcoding the random bit stream into a real numerical value includes three processes: statistics of high-level bits, calculation of high-level proportions, and mapping between high-level proportions and numerical values. This conversion process from a random bit stream to a corresponding numerical value belongs to common knowledge in the prior art, so it will not be repeated in this embodiment.

[0079] In the CIM circuit for random calculation provided in this embodiment, the word line driving circuit in the peripheral circuit can be adopted as follows: Figure 6 The circuit shown. Figure 6 The word line driver circuit shown, in read / write mode, PWM_IN is set to 0 and WL is controlled by WR_CTRL. In CIM mode, WR_CTRL is set to 0 and the multi-bit input is input through a pulse width modulation (PWM) signal. During CIM operation, WL is underdriven to extend the discharge time.

[0080] Example 2

[0081] Based on the scheme of Example 1, this embodiment provides a random quantization circuit, which adopts all or part of the circuits in the random voltage generator, twin comparator array, random accumulation circuit and transcoding circuit in the random quantization circuit provided in the CIM circuit of random calculation in Example 1. Figure 7 shows a circuit diagram of a typical random quantization circuit.

[0082] It should be noted that the random quantization circuit in the solution of Example 1 can be applied to the CIM circuit to implement the MAC operation in the random domain. However, in practical applications, this set of logic can also be applied to process other logical operations, such as single-bit multiplication, multi-bit multiplication, single-bit or multi-bit addition, etc.

[0083] In particular, in the random quantization circuit of this embodiment, when it comes to processing with a signed number, the twin comparator and the XOR gate in the random accumulation circuit need to be used. When it does not involve processing with a signed number, only one of the twin comparators can be used, and only the multiple-choice-one selector in the random accumulation circuit can be used.

[0084] For example, when processing single-bit multiplication, a random voltage generator and a twin comparator array can be used to generate a random bit stream based on the output signal voltage representing the result of the multiplication operation, and then the random bit stream can be transcoded into a decimal number using a transcoding circuit.

[0085] When processing multi-bit multiplication, a random voltage generator and a twin comparator array can be used to generate a random bit stream based on the output signal voltage representing the result of the multiplication operation. Then, the multi-selector in the random accumulation circuit realizes the weighted summation of the product results at different bits, and finally, the random bit stream of the final result is transcoded into a decimal number.

[0086] Example 3

[0087] Based on Embodiments 1 and 2, this embodiment also includes a MAC operation circuit suitable for machine learning training, which adopts the architecture of the CIM circuit of random calculation as in Embodiment 1. In particular, Figure 8 As shown, compared with the circuit scheme of Example 1, the MAC operation circuit suitable for machine learning training provided in this embodiment mainly includes two improvements:

[0088] First, in the solution of this embodiment, the SRAM array in the CIM circuit of random computing is composed of a plurality of SRAM cell arrays, and in particular, each SRAM cell is an 8T-SRAM cell using transposed split word lines.

[0089] Therefore, in the SRAM array of this embodiment, separate word lines WLL, WLR and read bit lines BL, BLB are included; as well as transposition word lines TWLL, TWLR and transposition bit lines TBL, TBLB. The above two groups of word lines and bit lines have the complete function of reading and writing data to the middle 8T-SRAM cells.

[0090] Specifically, Fig. 9 As shown, each 8T-SRAM cell of the transposed separated word line is composed of 2 PMOS tubes and 6 NMOS tubes. Among them, 2 PMOS tubes and 2 NMOS tubes are anti-coupled to form a latch structure with storage nodes Q and QB. The remaining 4 NMOS tubes are used to connect Q with BL, QB with BLB, Q with TBL, and QB with TBLB. The gates of each NMOS tube are connected to WLL, WLR, TWLL and TWLR.

[0091] Each 8T-SRAM cell is used to perform a multiplication operation between a signed input number and a signed two-bit weight. When performing a multiplication task, the sign bit of the weight is pre-read to determine which word line should be activated: if the weight is positive, WLL or TWLL is activated; if it is negative, WLR or TWLR is activated; the weight is pre-stored in the storage node in the form of an inverse code. The value of the input number is encoded by the pulse width of the activated WLL, TWLL, WLR or TWLR; when the input number has different signs, it is processed sequentially in two adjacent cycles. The product of the input number and the weight is reflected in the bit line voltage of BL, BLB, TBL or TBLB.

[0092] When performing a multiplication operation between the input number and the weight on each 8T-SRAM cell, the bit line voltage of the read bit lines on both sides will be precharged to a high level first. At this time, when the word line on one side inputs the corresponding input number through the transmission tube, the bit line on the corresponding side will form a discharge channel between the transmission tube and the storage node, which will cause the bit line voltage to drop. At the same time, the size of the input number is characterized by the pulse width of the word line. When the pulse width of the word line signal is different, it means that the discharge time of the bit line is different, that is, the voltage drop △V generated by the bit line is different. Therefore, by counting the discharge amount of the bit line on any side of the 8T-SRAM cell where the voltage drops, the value of the result of the multiplication operation can be obtained. And by distinguishing which side of the 8T-SRAM cell the bit line where the discharge occurs is located, the sign of the multiplication result can be determined.

[0093] In addition, for multiple 8T-SRAM cells in the same column, the discharge amounts generated by them will be accumulated on the same set of read bit lines, so the read bit lines can actually also realize the accumulation of multiple different multiplication results according to positive terms and negative terms respectively. Fig.10 The state diagram given reflects the typical state of implementing a multiplication operation using the SRAM array composed of 8T-SRAM cells provided in this embodiment.

[0094] Second, in the MAC operation circuit suitable for machine learning training, an independent random quantization circuit is provided on the rows and columns of the SRAM array, and the two can be used as row-level random quantization circuits and column-level random quantization circuits.

[0095] The foregoing describes that the MAC operation circuit suitable for machine learning training provided in this embodiment uses 8T-SRAM units to form the required SRAM array. Since the 8T-SRAM unit contains two sets of independent and complete functions, and two sets of word lines and bit lines that are transposed on the array. Therefore, each SRAM cell in the SRAM array can use the bit lines on the rows to read data and the bit lines on the columns to write data. Alternatively, the bit lines on the columns can be used to read data and the bit lines on the rows can be used to write data.

[0096] In view of the above-mentioned characteristics of the circuit supporting transposition operations, this embodiment provides an independent random quantization circuit on the rows and columns of the SRAM array. Therefore, when processing various machine learning data processing tasks, the circuit can realize that in the inference task, the activation data is input horizontally through WLL and WLR, and vertically accumulated through BL and BLB. In the training task, the loss value is input vertically through TWLL and TWLR, and horizontally accumulated through TBL and TBLB. This allows the circuit to process data processing tasks at different stages in parallel, thereby improving the circuit throughput and data processing efficiency; the circuit is more suitable for various edge AI devices.

[0097] In practical applications, Figure 8 The MAC operation circuit suitable for machine learning training shown in the figure can be designed as an accelerator chip, and the MAC operation circuit suitable for machine learning training as described above is used in the accelerator chip. Fig.11 In the layout design of the accelerator chip product of the present embodiment shown, the circuit layout can be further optimized considering the characteristic that the SRAM array supports transposition operation. The sampling capacitors of the present embodiment use MOM capacitors and are arranged diagonally above the array, so that a set of sampling capacitors can be reused in the horizontal and vertical directions without adding additional area overhead.

[0098] Simulation test

[0099] In order to verify the actual performance and advantages of the technical solution provided by the present invention, the technicians Figure 7 The MAC operation circuit suitable for machine learning training (TSCIM macro for short) shown in the figure is simulated and tested for performance. Among them, the 8T-SRAM cell in the SRAM is implemented using TSMC28nm process. The area of ​​the 8T cell is 0.91325 µm2. Adjacent bit cells are placed closely through a shared Dummy gate, thereby reducing area overhead. During the experiment, parasitic parameters are extracted from the Layout, and then the simulation results are obtained using Cadence Virtuoso and AMS simulators.

[0100] 1. Linearity

[0101] This experiment first measures the linearity of the TSCIM scheme of the present invention at different word line drive voltages. The experimental data obtained are as follows: Fig.12 and Fig.13 As shown, Fig.12 The curve reflects the relationship between the discharge voltage △V and the discharge time. Fig.13 The curve reflects the relationship between the discharge voltage △V and the number of activated rows.

[0102] Combination Fig.12 and Fig.13 From the data, we can find that when WL is powered by 0.7 V, the bit line voltage swings between 900 mV and 600 mV, which has good linear and quantifiable characteristics.

[0103] 2. Comparison of power consumption, area and delay

[0104] This experiment compares the performance of the TSCIM solution proposed in this embodiment with the traditional digital quantization solution (FA adder tree) in terms of normalized area, power consumption and calculation delay. The experimental data obtained are as follows: Fig.14 It is worth noting that Fig.14 The Y-axis for calculating delay uses an exponential scale axis.

[0105] Experimental results show that compared with the FA addition tree design, the TSCIM solution provided by the present invention reduces power consumption by 1.57 times and area by 7.73 times.

[0106] 3. Energy efficiency analysis

[0107] First, this experiment analyzes the energy efficiency of the TSCIM scheme designed by the present invention under different input sparsities of 50%, 75%, and 87.5%. When the circuit supply voltage is set to 0.9 V and WL is driven at 0.7 V, the experimental data obtained are as follows: Fig.15 Further, this experiment continues to analyze the energy efficiency of the TSCIM solution designed by the present invention under different power supply voltages of 0.7V, 0.8V, and 0.9V. The experimental data obtained are as follows Fig.16 shown.

[0108] Combination Fig.15 and Fig.16 It can be found that when the bit width of the input and weight is 4 bits, the peak energy efficiency of the circuit designed by the present invention is 63.02 TOPS / W, and the ideal supply voltage is 0.7 V. When the bit width of the input and weight is 8 bits, the peak energy efficiency is 18.57 TOPS / W.

[0109] 4. Performance comparison

[0110] This experiment further compares the performance of the solution of the present invention with many existing solutions of in-memory computing architecture. Fig.17 As shown; the final comparative test results of the circuit performance are shown in the following table:

[0111] Table 1: Performance comparison between the solution of the present invention and the existing solution

[0112]

[0113] By analyzing the data in the above table, it can be found that the area efficiency of the TSCIM solution designed by the present invention can reach 15.54 TOPS / mm², thanks to the compact array layout, fully parallel CIM operation mode and minimal SAC area overhead. In short, the circuit design provided by the present invention provides higher energy efficiency and better area efficiency than the existing CIM architecture.

[0114] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A CIM circuit for random computing, based on SRAM circuit design, characterized in that: It includes: The storage and computing array uses an SRAM array with data storage and logic operation functions; The storage and calculation array is composed of a plurality of storage and calculation unit arrays; each storage and calculation unit in the storage and calculation array is used to perform a multiplication operation, and the multiplication result is represented and outputted by a bit line voltage of a corresponding column; A random quantization circuit, comprising a random voltage generator, a twin comparator array, a random accumulation circuit and a transcoding circuit; the random voltage generator is used to generate a random voltage SV, SV is a random step-shaped square wave signal containing the full range of quantization results; the twin comparator array is composed of multiple groups of twin comparators; the twin comparator obtains the bit line voltage of the read bit line BL or BLB of each storage and calculation unit in the storage and calculation array, and compares it with the random voltage SV, thereby obtaining a random bit stream representing the multiplication results output by each storage and calculation unit in the storage and calculation array; the random bit stream is an n-bit binary signal, in which the probability of the high level contained corresponds to the value size; the random accumulation circuit uses the random bit streams of each multiplication result to perform accumulation operation in a random domain, thereby obtaining a random bit stream of the MAC operation result; the transcoding circuit is used to transcode the random bit stream of the MAC result into a corresponding value and output it; as well as Peripheral circuits include other circuit modules related to realizing data storage and logic operation functions.

2. The CIM circuit for random computing as claimed in claim 1, characterized in that: The random voltage generator is composed of a split capacitor voltage digital-to-analog converter CDAC, a linear feedback shift register LFSR, and a logic encoding circuit; Among them, CDAC consists of 2n-2 pairs of capacitors with the value of 1:2:…:2 n-2 The distributed capacitors are composed of the upper plates of all capacitors connected to the output signal line; one end of the output signal line is connected to the half-scale signal VCM through a switch, and the other end is used as the output port of the random signal SV; the n capacitor values ​​are arranged in the order of 1:2:…:2 n-2 The lower substrate of the distributed capacitor is connected to the first input signal line through n first transmission gates respectively; the other n capacitor values ​​are arranged in the order of 1:2:…:2 n-2 The lower substrate of the distributed capacitor is connected to the second input signal line through n second transmission gates; the first input signal line and the second input signal line are connected to the upper limit voltage VMAX and the lower limit voltage VMIN of the range respectively; LFSR is used to scramble the order of the step voltages in the input random signal SV. <0> ~D <n-1>Generate a set of control code Q <0> ~Q <n-1>The logic encoding circuit is used according to the control code Q <0> ~Q <n-1> n-1 pairs of mutually inverted control signals SP and SN for switching the switching states of the respective first transmission gates and second transmission gates are generated.

3. The CIM circuit for random computing as claimed in claim 2, characterized in that: The linear feedback shift register is composed of n D flip-flops, a PMOS tube and 2n NMOS tubes; wherein the PMOS tube is used as a control tube, and every two NMOS tubes form a branch tube; each D flip-flop is cascaded, and the Q end of the higher-level D flip-flop is connected to the D end of the lower-level D flip-flop; the D end of the highest-level D flip-flop is connected to the power supply through the control tube, and the gate of the control tube is connected to the pre-charge signal PRE; the clock port of each D flip-flop is connected to the clock signal CLK; the branch tube corresponds to each D flip-flop one by one; each branch tube is composed of N1 and N2; in each branch tube, the drain of N1 is connected to the D end of the highest-level D flip-flop; the source of N1 is connected to the drain of N2; the source of N2 is grounded; the gate of N1 is connected to the garbled D <0> ~D <n-1> ; The gate of N2 is connected to the Q end of the D flip-flop of the corresponding stage.

4. The CIM circuit for random computing as claimed in claim 3, characterized in that: The logic coding circuit is composed of n-1 groups of coding units; each coding unit is composed of an XOR gate and an inverter; the input end of the inverter is connected to the output end of the XOR gate; one of the inputs of the XOR gate of each coding unit is Q <n-1>, and the other input is Q <0> ~Q <n-2> One of them; the output signal of the XOR gate in each coding unit is used as the control signal SP and is connected to the gate of each first transmission gate in CDAC; the output signal of the inverter in each coding unit is used as the control signal SN and is connected to the gate of each second transmission gate in CDAC.

5. The CIM circuit for random computing as claimed in claim 1, characterized in that: The twin comparator is composed of a first-level preselector LineSwitch1 and two comparators COMP1 and COMP2; two input terminals of LineSwitch1 are connected to SV, and the other two input terminals are connected to BL and BLB respectively; four output terminals of LineSwitch1 are connected to the input terminals of COMP1 and COMP2 respectively; In the data storage mode, LineSwitch1 connects BL and BLB to COMP1, and connects two SVs to COMP2. At this time, COMP1 works and COMP2 does not work, thereby realizing a read operation based on dual bit lines. In the logic operation mode, LineSwitch1 connects BL and SV to COMP1, and connects BLB and SV to COMP2, and then uses two comparators to read out the product operation results with different signs output on different read bit lines.

6. The CIM circuit for random computing as claimed in claim 1, characterized in that: The random accumulation circuit includes a plurality of XOR gates, a plurality of secondary preselectors LineSwitch2 and tertiary preselectors LineSwitch3, a plurality of multiple-to-one selectors MUX1, MUX2, MUX3, and a sign bit register array; The sign bit register array is composed of a plurality of D flip-flops, and the D flip-flops correspond one to one with the twin comparators used in the circuit; the sign bit register array is used to store the sign corresponding to each multiplication result output by the front-end twin comparator; The two output ends of each twin comparator are connected to the input end of an XOR gate, and the XOR gate is used to output the absolute value of the sum of the positive and negative results calculated on the connected read bit lines BL and BLB; the sign of the sum result is stored in a corresponding D flip-flop in the sign bit register array; The outputs of some XOR gates are connected to the inputs of LineSwitch2; a part of the outputs of each LineSwitch2 is connected to the inputs of MUX1, and the other part of the outputs is connected to the inputs of MUX2; LineSwitch2 performs weighted accumulation of positive values ​​and negative values ​​in MUX1 and MUX2 respectively according to the signs of the operation results pre-stored in the sign bit register array, thereby realizing multi-bit multiplication; The output ends of each MUX1 and MUX3 are connected to the input end of LineSwitch3; the output end of LineSwitch3 is connected to the transcoding circuit through an XOR gate, thereby realizing transcoding output of the multi-bit multiplication operation result; on the other hand, it is connected to the transcoding circuit through MUX3, thereby accumulating the operation results of multiple multi-bit multiplications and then transcoding and outputting them, that is, realizing the MAC operation of multi-bit signed numbers.

7. A random quantization circuit, characterized in that: It adopts all or part of the random voltage generator, twin comparator array, random accumulation circuit and transcoding circuit contained in the random quantization circuit of the CIM circuit of random calculation as described in any one of claims 1-6.

8. A MAC operation circuit suitable for machine learning training, characterized in that: It adopts the architecture of the random calculation CIM circuit as claimed in any one of claims 1 to 6; the SRAM array in the random calculation CIM circuit is arranged by a plurality of 8T-SRAM cell arrays using transposed separated word lines; the SRAM array includes separated word lines WLL, WLR and read bit lines BL, BLB; and transposed word lines TWLL, TWLR and transposed bit lines TBL, TBLB; In the MAC operation circuit suitable for machine learning training, an independent random quantization circuit is provided on the rows and columns of the SRAM array; in the inference task, the activation data is horizontally input through WLL and WLR and vertically accumulated through BL and BLB; on the contrary, in the training task, the loss value is vertically input through TWLL and TWLR and horizontally accumulated through TBL and TBLB.

9. The MAC operation circuit suitable for machine learning training according to claim 8, characterized in that: Each 8T-SRAM cell of the transposed split word line is composed of 2 PMOS tubes and 6 NMOS tubes; among them, 2 PMOS tubes and 2 NMOS tubes are anti-phase coupled to form a latch structure with storage nodes Q and QB; the remaining 4 NMOS tubes are used to connect Q with BL, QB with BLB, Q with TBL, and QB with TBLB; the gates of each NMOS tube are connected to WLL, WLR, TWLL and TWLR; and / or Each 8T-SRAM cell is used to perform a multiplication operation between a signed input number and a signed two-bit weight; When performing a multiplication task, the sign bit of the weight is pre-read to determine which word line should be activated: if the weight is positive, WLL or TWLL is activated; if it is negative, WLR or TWLR is activated; the weight is pre-stored in the storage node in the form of an inverse code; the value of the input number is encoded by the pulse width of the activated WLL, TWLL, WLR or TWLR; when the input numbers have different signs, they are processed sequentially in two adjacent cycles; the product of the input number and the weight is reflected in the bit line voltage of BL, BLB, TBL or TBLB.

10. An accelerator chip, characterized in that: It adopts the MAC operation circuit suitable for machine learning training as described in claim 8.

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