Image bilinear interpolation parallel optimization algorithm, system, device and medium

Abstract

The invention provides an image bilinear interpolation parallel optimization algorithm, system and device and a medium, and the algorithm comprises the steps: setting four storage regions which can be read at the same time in a clock period in an FPGA, carrying out the conversion according to the coordinates of an original pixel point, and obtaining a storage region and a storage address corresponding to the pixel point, and writing the image information corresponding to the original pixel point into the address to complete the storage of the original image. According to the coordinates of the transformed pixel points subjected to geometric transformation, storage areas and storage addresses corresponding to four original pixel points around each transformed pixel point are obtained, and image information stored in the four areas is read at the same time to complete bilinear interpolation operation; according to the method, image information is stored in a reasonable odd-even mode, it is guaranteed that four adjacent pixel points needed by interpolation calculation are located in four storage areas respectively, the operation efficiency is improved through the parallel characteristic, and reading and operation of the four pixel points are completed in each clock period.

Description

Technical Field

[0001] The present application relates to the technical field of bilinear interpolation, and in particular to an image bilinear interpolation parallel optimization algorithm, system, device and medium. Background Art

[0002] At present, infrared imaging devices are widely used. The enlargement and rotation of infrared images require image interpolation operations, among which the most commonly used interpolation algorithm is bilinear interpolation.

[0003] Traditional bilinear interpolation operations are mostly completed in DSP, but the forward calculation characteristics of DSP make the calculation take a long time. The interpolation operation of a 1024*1024 16-bit infrared image usually takes milliseconds, which is unacceptable for the delay caused by real-time tracking and search systems. In recent years, there have been precedents for using FPGA for bilinear interpolation, but the implementation method is either the same sequential calculation method as DSP, which cannot shorten the calculation time, or shorten the calculation time by increasing the clock frequency. However, for image data streams with high image pixel clocks, a 4-fold calculation clock is usually used, and the calculation clock can reach 400MHZ, which is difficult to achieve for FPGA and difficult to converge the timing. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, the present application aims to provide an image bilinear interpolation parallel optimization algorithm, system, device and medium.

[0005] In a first aspect, the present application proposes an image bilinear interpolation parallel optimization algorithm, comprising the following steps:

[0006] S100 initializes the FPGA, so that the FPGA includes four storage areas, each of which has a unique storage area number, and the FPGA can simultaneously read the storage contents of the four storage areas in one clock cycle;

[0007] S200. Acquire an original image information set of an original image and a transformed image information set of a transformed image, wherein the original image information set includes original pixel coordinates corresponding to each original pixel and original image information, and the transformed information set includes transformed pixel coordinates corresponding to each transformed pixel, wherein the transformed image is obtained by geometrically transforming the original image;

[0008] S300. According to the original pixel coordinates, a storage information set is obtained, wherein the storage information set includes a storage area number corresponding to each of the original pixel points, recorded as an original storage number, and a storage area address of the storage area corresponding to the original storage area number, recorded as an original storage address; wherein the original storage numbers corresponding to the pixel points around each of the transformed pixel points are different;

[0009] S400. Storing the original image information in a storage area corresponding to the original storage address;

[0010] S500. According to the transformed pixel coordinates of the transformed pixel, in accordance with the coordinate transformation strategy, the storage addresses of the four original pixel points around each transformed pixel are obtained and recorded as transformed storage addresses;

[0011] S600. According to the transformed storage address, simultaneously retrieve the four original image information corresponding to the transformed storage address;

[0012] S700. Traverse the transformed image information set, and repeat steps S500-S700 to obtain original image information of four original pixel points corresponding to all the transformed pixel points.

[0013] According to the technical solution provided in the embodiment of the present application, step S300 includes the following steps:

[0014] S310. According to the original pixel coordinates and storage classification strategy, the original storage number is obtained, and a storage area distribution map is obtained;

[0015] S320. According to the original pixel coordinates and storage address strategy, obtain the original storage address corresponding to each original storage number;

[0016] S330. Obtain the storage information set according to all the original storage numbers and the original storage addresses corresponding thereto.

[0017] According to the technical solution provided in the embodiment of the present application, the storage area includes a first storage area, a second storage area, a third storage area and a fourth storage area, the storage area distribution diagram includes a plurality of storage area sets arranged along a vertical distribution, each of the storage area sets includes a plurality of storage subsets arranged along a horizontal distribution, each of the storage subsets includes two first storage subsets and a second storage subset arranged along a vertical distribution, the first storage subset includes the first storage area and the second storage area arranged along a horizontal distribution, and the second storage subset includes the third storage area and the fourth storage area arranged along a horizontal distribution.

[0018] According to the technical solution provided in the embodiment of the present application, the storage classification strategy includes the following steps:

[0019] S311. Obtaining the column coordinates and row coordinates of the original pixel coordinates of each original pixel, recorded as original row coordinates and original column coordinates;

[0020] S312. Convert the original row coordinates and the original column coordinates into binary to obtain original binary row coordinates and original binary column coordinates;

[0021] S313. Determine whether the last bit of the original binary column coordinate and the original binary row coordinate is an odd number or an even number. When both are even numbers, execute step S314; when the last bit of the original binary row coordinate is an even number and the last bit of the original binary column coordinate is an odd number, execute step S315; when the last bit of the original binary row coordinate is an odd number and the last bit of the original binary column coordinate is an even number, execute step S316; when both are odd numbers, execute step S317;

[0022] S314. Using the number of the first storage area as the original storage number;

[0023] S315. Using the number of the second storage area as the original storage number;

[0024] S316. Using the number of the third storage area as the original storage number;

[0025] S317. Use the number of the fourth storage area as the original storage number.

[0026] According to the technical solution provided in the embodiment of the present application, the storage address strategy includes the following steps:

[0027] S321. Remove the last bit of the original binary column coordinate and the original binary row coordinate to obtain a transformed binary row coordinate and a transformed binary column coordinate;

[0028] S322. Combine the transformed binary row coordinate and the transformed binary column coordinate to form the original storage address.

[0029] According to the technical solution provided in the embodiment of the present application, each of the storage subsets has the same transformed binary row coordinates and the same transformed binary column coordinates.

[0030] According to the technical solution provided in the embodiment of the present application, the coordinate transformation strategy includes the following steps:

[0031] S510. Obtain the row coordinates and column coordinates of the transformed pixel point coordinates, recorded as transformed row coordinates and transformed column coordinates;

[0032] S520. Rounding the transformed row coordinates and the transformed column coordinates to obtain interpolated row coordinates and interpolated column coordinates;

[0033] S530. Determine the parity of the interpolated row coordinates and the interpolated column coordinates. When the interpolated row coordinates and the interpolated column coordinates are both even numbers, execute step S540; when the interpolated column coordinates are odd numbers and the interpolated row coordinates are even numbers, execute step S550; when the interpolated column coordinates are even numbers and the interpolated row coordinates are odd numbers, execute step S560; when the interpolated row coordinates and the interpolated column coordinates are both odd numbers, execute step S570;

[0034] S540. Using the original storage addresses of the four original pixel points around the transformed pixel point as the transformed storage addresses;

[0035] S550. The transformed binary row coordinates of the original pixel points stored in the first storage area and the third storage area around the transformed pixel point remain unchanged, and the transformed binary column coordinates are added by one to obtain the transformed storage addresses corresponding to the first storage area and the third storage area; the original storage addresses of the original pixel points stored in the second storage area and the fourth storage area around the transformed pixel point are used as the transformed storage addresses corresponding to the second storage area and the fourth storage area;

[0036] S560. The transformed binary column coordinates of the original pixel points stored in the first storage area and the second storage area around the transformed pixel point remain unchanged, and the transformed binary row coordinates are added by one to obtain the transformed storage addresses corresponding to the first storage area and the second storage area; the original storage addresses of the original pixel points stored in the third storage area and the fourth storage area around the transformed pixel point are used as the transformed storage addresses corresponding to the third storage area and the fourth storage area;

[0037] S570. Add one to the transformed binary row coordinates and the transformed binary column coordinates of the original pixel points stored in the first storage area around the transformed pixel points to obtain the transformed storage address corresponding to the first storage area; the transformed binary column coordinates stored in the second storage area around the transformed pixel points remain unchanged, and the transformed binary row coordinates are added by one to obtain the transformed storage address corresponding to the second storage area; the transformed binary row coordinates stored in the third storage area around the transformed pixel points remain unchanged, and the transformed binary column coordinates are added by one to obtain the transformed storage address corresponding to the third storage area; the original storage coordinates stored in the fourth storage area around the transformed pixel points are used as the transformed storage address corresponding to the fourth storage area.

[0038] In a second aspect, the present application proposes an image bilinear interpolation parallel optimization system for implementing the above-mentioned image bilinear interpolation parallel optimization algorithm, the system comprising:

[0039] A configuration module, wherein the configuration module is configured to initialize the FPGA, so that the FPGA includes four storage areas, each of which has a unique storage area number, and the FPGA can simultaneously read the storage contents of the four storage areas in one clock cycle;

[0040] an acquisition module, the acquisition module being configured to acquire an original image information set of an original image and a transformed image information set of a transformed image, the original image information set comprising original pixel point coordinates corresponding to each original pixel point and original image information, the transformed information set comprising transformed pixel point coordinates corresponding to each transformed pixel point, wherein the transformed image is obtained by geometrically transforming the original image;

[0041] a first calculation module, the first calculation module being configured to obtain a storage information set according to the original pixel point coordinates, the storage information set comprising a storage area number corresponding to each of the original pixel points, recorded as an original storage number, and a storage area address of the storage area corresponding to the original storage area number, recorded as an original storage address; wherein the original storage numbers corresponding to the pixel points around each of the transformed pixel points are all different;

[0042] A storage module, wherein the storage module is configured to store the original image information in a storage area corresponding to the original storage address;

[0043] A second calculation module, the second calculation module is configured to obtain storage addresses of four original pixel points around each of the transformed pixel points according to the transformed pixel point coordinates of the transformed pixel points and in accordance with the coordinate transformation strategy, and record them as transformed storage addresses;

[0044] A calling module, wherein the calling module is configured to call, according to the transformed storage address, four pieces of original image information corresponding to the transformed storage address at the same time;

[0045] An output module is configured to traverse the transformed image information set, and repeatedly execute steps S500-S700 to obtain original image information of four original pixel points corresponding to all the transformed pixel points.

[0046] In a third aspect, the present application proposes a terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the image bilinear interpolation parallel optimization algorithm as described above when executing the computer program.

[0047] In a fourth aspect, the present application proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the image bilinear interpolation parallel optimization algorithm as described above are implemented.

[0048] In summary, the present application proposes a parallel optimization algorithm for bilinear interpolation of an image. By setting four storage areas that can be read simultaneously in one clock cycle in the FPGA, the storage area and storage address corresponding to the pixel point are converted according to the coordinates of the original pixel point, and the image information corresponding to the original pixel point is written into the address; then, according to the coordinates of the transformed pixel point after the geometric transformation, the storage area and transformation storage address of the four original pixel points around each transformed pixel point are obtained, and the image information stored in the area is read according to the transformation storage address, and then the value of the original pixel points around the transformed pixel point is obtained; and then the interpolation operation of the entire image is completed through the above steps. Compared with the DSP interpolation operation, the present application can improve the operation efficiency by utilizing the parallel characteristics in the FPGA, and can complete one operation per clock cycle. And by storing the image information in a reasonable parity method, it is ensured that the 4 adjacent pixel points required for the interpolation calculation are respectively located in 4 storage areas, that is, the image information of the required 4 pixel points can be read in one clock cycle, and real-time operation can be achieved without increasing the calculation clock frequency, and good timing convergence can be guaranteed for all types of FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Flowchart of the image bilinear interpolation parallel optimization algorithm provided in the embodiment of the present application

[0050] Figure 2 A schematic diagram of the layout of the storage area distribution diagram provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of a layout including pixel transformation provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of the structure of the terminal device provided for this application.

[0053] The text annotations in the figure represent:

[0054] 700. Computer system; 701. CPU; 702. ROM; 703. RAM; 704. Bus; 705. I / O interface; 706. Input part; 707. Output part; 708. Storage part; 709. Communication part; 710. Drive; 711. Removable media. DETAILED DESCRIPTION

[0055] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0056] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0057] Example 1

[0058] As mentioned in the background technology, the present application proposes an image bilinear interpolation parallel optimization algorithm, comprising the following steps:

[0059] S100 initializes the FPGA, so that the FPGA includes four storage areas, each of which has a unique storage area number, and the FPGA can simultaneously read the storage contents of the four storage areas in one clock cycle;

[0060] Among them, the solution of the present application is executed by FPGA, and the storage area includes a first storage area, a second storage area, a third storage area and a fourth storage area, and the corresponding storage areas are numbered 1, 2, 3, and 4.

[0061] S200. Acquire an original image information set of an original image and a transformed image information set of a transformed image, wherein the original image information set includes original pixel coordinates corresponding to each original pixel and original image information, and the transformed information set includes transformed pixel coordinates corresponding to each transformed pixel, wherein the transformed image is obtained by geometrically transforming the original image;

[0062] The original pixels are all the pixels in the original image. Figure 2 As shown, the circle represents the original pixel point, the coordinates of the original pixel point in the upper left corner are (0,0), and the transformed pixel point is obtained by rotating or enlarging the original pixel point through geometric transformation. After the geometric transformation, the row coordinates and column coordinates of the transformed pixel point are both decimals, that is, the transformed pixel point is placed between the original pixel points, such as Figure 3 As shown, ABCD is the transformed pixel point. Optionally, the coordinates of the transformed pixel point are (0.5, 0.5), (1.5, 0.5), (1.5, 0.5), and (1.5, 1.5) respectively.

[0063] S300. According to the original pixel coordinates, a storage information set is obtained, wherein the storage information set includes a storage area number corresponding to each of the original pixel points, recorded as an original storage number, and a storage area address of the storage area corresponding to the original storage area number, recorded as an original storage address; wherein the original storage numbers corresponding to the pixel points around each of the transformed pixel points are different;

[0064] The steps include:

[0065] S310. According to the original pixel coordinates and storage classification strategy, the original storage number is obtained, and a storage area distribution map is obtained;

[0066] Further, the storage area distribution diagram includes a plurality of storage area sets arranged along a vertical distribution, each of the storage area sets includes a plurality of storage subsets arranged along a horizontal distribution, each of the storage subsets includes a first storage subset and a second storage subset arranged along a vertical distribution, the first storage subset includes the first storage area and the second storage area arranged along a horizontal distribution, and the second storage subset includes the third storage area and the fourth storage area arranged along a horizontal distribution.

[0067] Please refer to Figure 2 As shown, the numbers in the circle are the original storage numbers. As shown in the figure, the original storage numbers of the storage subset in the upper left corner are 1 and 2 from left to right in the first row, and 3 and 4 from left to right in the second row. Please refer to Figure 3 As shown, the transformed pixel point will fall between the original pixel points, and the original storage numbers around it are 1, 2, 3 and 4, which are all different.

[0068] Furthermore, the storage classification strategy includes the following steps:

[0069] S311. Obtaining the column coordinates and row coordinates of the original pixel coordinates of each original pixel, recorded as original row coordinates and original column coordinates;

[0070] Specifically, the coordinates of the original pixel points can be expressed as (column coordinate, row coordinate). Taking the four original pixel points in the upper left corner as an example, the coordinates of the two original pixel points in the first row are (0, 0) and (1, 0), respectively, and the coordinates of the two original pixel points in the second row are (0, 1) and (1, 1), respectively.

[0071] S312. Convert the original row coordinates and the original column coordinates into binary to obtain original binary row coordinates and original binary column coordinates;

[0072] Then the original binary row coordinates and the original binary column coordinates of the two original pixel points in the first row are (…0000,…0001), (…0000,…0000), and the original binary column coordinates of the two original pixel points in the second row are (…0000,…0001), (…0001,…0001), respectively.

[0073] S313. Determine whether the last bit of the original binary column coordinate and the original binary row coordinate is an odd number or an even number. When both are even numbers, execute step S314; when the last bit of the original binary row coordinate is an even number and the last bit of the original binary column coordinate is an odd number, execute step S315; when the last bit of the original binary row coordinate is an odd number and the last bit of the original binary column coordinate is an even number, execute step S316; when both are odd numbers, execute step S317;

[0074] S314. Using the number of the first storage area as the original storage number;

[0075] Taking the first original pixel point coordinate of the first row as an example, the last bit of its original binary row coordinate is 0, which is an even number, and the last bit of its original binary column coordinate is 0, which is an even number, and is stored in the first storage area;

[0076] S315. Using the number of the second storage area as the original storage number;

[0077] Taking the second original pixel point coordinate of the first row as an example, the last bit of its original binary row coordinate is 0, which is an even number, and the last bit of its original binary column coordinate is 1, which is an odd number, and it is stored in the second storage area;

[0078] S316. Using the number of the third storage area as the original storage number;

[0079] Taking the first original pixel point coordinate of the second row as an example, the last bit of its original binary row coordinate is 1, which is an odd number, and the last bit of its original binary column coordinate is 0, which is an even number, and is stored in the third storage area;

[0080] S317. Using the number of the fourth storage area as the original storage number;

[0081] Among them, taking the second original pixel point coordinate of the second row as an example, the last bit of its original binary row coordinate is 1, which is an odd number, and the last bit of the original binary column coordinate is 1, which is an odd number, and it is stored in the fourth storage area.

[0082] In summary, for example, if the size of the original image is 1024*1024, the row and column count bit widths of each storage area are 10 respectively, which is written as [9:0] in FPGA; the lowest bit [0] of the row and column count of the storage area is used as the write enable signal, and the control table of the write enable signal is shown in Table-1 below:

[0083] Table-1

[0084] Storage Area Write enable control signal valid condition 1 Row count[0] is 0 and column count[0] is 0 2 Row count[0] is 0 and column count[0] is 1 3 Row count[0] is 1 and column count[0] is 0 4 Row count[0] is 1 and column count[0] is 1

[0085] S320. According to the original pixel coordinates and storage address strategy, obtain the original storage address corresponding to each original storage number;

[0086] The storage address strategy comprises the following steps:

[0087] S321. Remove the last bit of the original binary column coordinate and the original binary row coordinate to obtain a transformed binary row coordinate and a transformed binary column coordinate;

[0088] Here, taking the four original pixel points in the upper left corner as an example, the transformed binary row coordinates and the transformed binary column coordinates of the four original pixel points are both ...000;

[0089] Therefore, each of the storage subsets has the same transformed binary row coordinates and the same transformed binary column coordinates. Figure 3 As shown,

[0090] The original pixel points in the dotted line box have the same column address, and the original pixel points in the solid line box have the same row address.

[0091] S322. Combine the transformed binary row coordinate and the transformed binary column coordinate to form the original storage address.

[0092] Among them, the original storage address is obtained by splicing the transformed binary row coordinates and the transformed binary column coordinates, so the original storage addresses of the four original pixel points in the upper left corner are all (…0000,…0000); the original storage address forms the write enable signal of the FPGA.

[0093] S330. Obtain the storage information set according to all the original storage numbers and the original storage addresses corresponding thereto.

[0094] That is, taking the fourth original pixel in the upper left corner as an example, the storage information set is shown in Table 2:

[0095] Table-2

[0096] Storage Area Original storage number Original storage address First row first First storage area 1 (…0000,…0000) The first row, the second Second storage area 2 (…0000,…0000) The first one in the second row The third storage area 3 (…0000,…0000) The second row, the second Fourth storage area 4 (…0000,…0000)

[0097] It can be seen from Table-2 that the original storage addresses of the four original pixels in the upper left corner are the same, but the storage areas are different.

[0098] S400. Storing the original image information in a storage area corresponding to the original storage address;

[0099] After the write enable signal is obtained, the original image information is stored in a storage area corresponding to the storage address under the storage area obtained above; wherein the original image information includes the grayscale information of each original pixel point, etc.

[0100] S500. According to the transformed pixel coordinates of the transformed pixel, in accordance with the coordinate transformation strategy, the storage addresses of the four original pixel points around each transformed pixel are obtained and recorded as transformed storage addresses;

[0101] The coordinate transformation strategy includes the following steps:

[0102] S510. Obtain the row coordinates and column coordinates of the transformed pixel point coordinates, recorded as transformed row coordinates and transformed column coordinates;

[0103] Among them, taking the transformed pixel point A as an example, its transformed column coordinate and the transformed row coordinate are 0.5 and 0.5 respectively; taking the transformed pixel point B as an example, its transformed column coordinate and the transformed row coordinate are 1.5 and 0.5 respectively; taking the transformed pixel point C as an example, its transformed column coordinate and the transformed row coordinate are 0.5 and 1.5 respectively; taking the transformed pixel point D as an example, its transformed column coordinate and the transformed row coordinate are 1.5 and 1.5 respectively;

[0104] S520. Rounding the transformed row coordinates and the transformed column coordinates to obtain interpolated row coordinates and interpolated column coordinates;

[0105] Taking the transformed pixel point A as an example, its interpolated column coordinates and interpolated row coordinates are 0 and 0 respectively; taking the transformed pixel point B as an example, its interpolated column coordinates and interpolated row coordinates are 1 and 0 respectively; taking the transformed pixel point C as an example, its interpolated column coordinates and interpolated row coordinates are 0 and 1 respectively; taking the transformed pixel point D as an example, its interpolated column coordinates and interpolated row coordinates are 1 and 1 respectively;

[0106] S530. Determine the parity of the interpolated row coordinates and the interpolated column coordinates. When the interpolated column coordinates and the interpolated row coordinates are both even numbers, execute step S540; when the interpolated column coordinates are odd numbers and the interpolated row coordinates are even numbers, execute step S550; when the interpolated column coordinates are even numbers and the interpolated row coordinates are odd numbers, execute step S560; when the interpolated column coordinates and the interpolated row coordinates are both odd numbers, execute step S570;

[0107] S540. Using the original storage addresses of the four original pixel points around the transformed pixel point as the transformed storage addresses;

[0108] If the interpolated row coordinates and the interpolated column coordinates of the transformed pixel point A are both 0, which is an even number, then the transformed storage addresses of the first storage area, the second storage area, the third storage area and the fourth storage area around the transformed pixel point A are all the original storage addresses (…0000,…0000).

[0109] S550. The transformed binary row coordinates of the original pixel points stored in the first storage area and the third storage area around the transformed pixel point remain unchanged, and the transformed binary column coordinates are added by one to obtain the transformed storage addresses corresponding to the first storage area and the third storage area; the original storage addresses of the original pixel points stored in the second storage area and the fourth storage area around the transformed pixel point are used as the transformed storage addresses corresponding to the second storage area and the fourth storage area;

[0110] If the interpolated column coordinate of the transformed pixel point B is 1, which is an odd number, and the interpolated row coordinate is 0, which is an even number, then the transformed storage addresses of the second storage area and the fourth storage area are the original storage addresses (…0000,…0000), and the transformed storage addresses of the first storage area and the third storage area are (…0001,…0000);

[0111] S560. The transformed binary column coordinates of the original pixel points stored in the first storage area and the second storage area around the transformed pixel point remain unchanged, and the transformed binary row coordinates are added by one to obtain the transformed storage addresses corresponding to the first storage area and the second storage area; the original storage addresses of the original pixel points stored in the third storage area and the fourth storage area around the transformed pixel point are used as the transformed storage addresses corresponding to the third storage area and the fourth storage area;

[0112] If the interpolation column coordinate of the transformed pixel point C is 0, which is an even number, and the interpolation row coordinate is 1, which is an odd number, then the transformed storage addresses of the first storage area and the second storage area are (…0000,…0001); the transformed storage addresses of the third storage area and the fourth storage area are (…0000,…0000);

[0113] S570. Add one to the transformed binary row coordinates and the transformed binary column coordinates of the original pixel points stored in the first storage area around the transformed pixel points to obtain the transformed storage address corresponding to the first storage area; keep the transformed binary column coordinates stored in the second storage area around the transformed pixel points unchanged, add one to the transformed binary row coordinates to obtain the transformed storage address corresponding to the second storage area; keep the transformed binary row coordinates stored in the third storage area around the transformed pixel points unchanged, add one to the transformed binary column coordinates to obtain the transformed storage address corresponding to the third storage area; use the original storage coordinates stored in the fourth storage area around the transformed pixel points as the transformed storage address corresponding to the fourth storage area;

[0114] If the interpolation row coordinates and the interpolation column coordinates of the transformed pixel point D are both 1, which is an odd number, then the transformed storage address of the first storage area is (…0001,…0001); the transformed storage address of the second storage area is (…0000,…0001); the transformed storage address of the third storage area is (…0001,…0000); and the transformed storage address of the fourth storage area is the original storage address (…0000,…0000).

[0115] S600. According to the transformed storage address, simultaneously retrieve the four original image information corresponding to the transformed storage address;

[0116] Among them, the 4 values ​​read out from the 4 storage areas are the values ​​of 4 adjacent pixel points required for bilinear interpolation calculation, and are read out simultaneously within one clock cycle. The interpolation operation can be completed according to the bilinear interpolation calculation formula; the calculation process is existing technology and will not be repeated here.

[0117] S700. Traverse the transformed image information set, repeat steps S500-S700, and obtain the original image information of four original pixels corresponding to all the transformed pixels;

[0118] The above steps are a bilinear interpolation calculation method for the transformed pixel points. Similarly, the interpolation operation of the entire image can be completed by following the above steps.

[0119] In summary, the parallel calculation of bilinear interpolation can be completed based on the above steps, which makes full use of the characteristics of FPGA parallel storage. The image information is stored in an even-even manner in the image rows and columns, so that four adjacent pixels can be read in one clock cycle, which greatly improves the operation efficiency. The operation clock only needs to be consistent with the image pixel clock, and there is no need for frequency multiplication.

[0120] Compared with DSP interpolation operations, the parallel characteristics can be used to improve the operation efficiency in FPGA, and one operation can be completed in each clock cycle. In addition, the image information is stored in a reasonable parity manner to ensure that the four adjacent pixels required for interpolation calculation are located in four storage areas, so that the image information of the required four pixels can be read in one clock cycle, and real-time operation can be achieved without increasing the calculation clock frequency, which can ensure good timing convergence for all types of FPGAs.

[0121] Example 2

[0122] Based on Example 1, the present application proposes an FPGA-based image bilinear interpolation parallel optimization system for implementing the image bilinear interpolation parallel optimization algorithm described above, the system comprising:

[0123] A configuration module, wherein the configuration module is configured to initialize the FPGA, so that the FPGA includes four storage areas, each of the storage areas has a unique storage area number, and the FPGA can read out four storage areas simultaneously in one clock cycle;

[0124] an acquisition module, the acquisition module being configured to acquire an original image information set of an original image and a transformed image information set of a transformed image, the original image information set comprising original pixel point coordinates corresponding to each original pixel point and original image information, the transformed information set comprising transformed pixel point coordinates corresponding to each transformed pixel point, wherein the transformed image is obtained by geometrically transforming the original image;

[0125] a first calculation module, the first calculation module being configured to obtain a storage information set according to the original pixel point coordinates, the storage information set comprising a storage area number corresponding to each of the original pixel points, recorded as an original storage number, and a storage area address of the storage area corresponding to the original storage area number, recorded as an original storage address; wherein the original storage numbers corresponding to the pixel points around each of the transformed pixel points are all different;

[0126] A storage module, wherein the storage module is configured to store the original image information in a storage area corresponding to the original storage address;

[0127] A second calculation module, the second calculation module is configured to obtain storage addresses of four original pixel points around each of the transformed pixel points according to the transformed pixel point coordinates of the transformed pixel points and in accordance with the coordinate transformation strategy, and record them as transformed storage addresses;

[0128] A calling module, wherein the calling module is configured to call, according to the transformed storage address, four pieces of original image information corresponding to the transformed storage address at the same time;

[0129] An output module is configured to traverse the transformed image information set, and repeatedly execute steps S500-S700 to obtain original image information of four original pixel points corresponding to all the transformed pixel points.

[0130] Example 3

[0131] like Figure 4 As shown, the computer system 700 of the terminal device includes a CPU 701, which can perform various appropriate actions and processes according to the program stored in the ROM 702 or the program loaded from the storage part 708 to the RAM 703. In the RAM 703, various programs and data required for system operation are also stored. The CPU 701, the ROM 702 and the RAM 703 are connected to each other through the bus 704. The I / O interface 705 is also connected to the bus 704. The following components are connected to the I / O interface 705: an input part 706 including a keyboard, a mouse, etc.; an output part 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage part 708 including a hard disk, etc.; and a communication part 709 including a network interface card such as a LAN card, a modem, etc. The communication part 709 performs communication processing via a network such as the Internet. The drive is also connected to the I / O interface 705 as needed. A removable medium 711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is mounted on the drive 710 as needed, so that a computer program read therefrom is installed into the storage section 708 as needed.

[0132] In particular, according to the embodiments of the present application, the above reference process Figure 1 The described process can be implemented as a computer software program. For example, embodiment 3 of the present application includes a computer program product, which includes a computer program carried on a computer readable medium, and the computer program contains program code for executing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by CPU 701, the above-mentioned functions defined in the present computer system 700 are executed.

[0133] It should be noted that the computer-readable medium shown in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0134] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments 3 of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0135] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the image bilinear interpolation parallel optimization algorithm as described in the above embodiment.

[0136] For example, the electronic device may implement Figure 1 As shown in: S100. Initialize FPGA, make FPGA include four storage areas, each storage area has a unique storage area number, and the FPGA can read out four storage areas at the same time in one clock cycle; S200. Obtain the original image information set of the original image and the transformed image information set of the transformed image, the original image information set includes the original pixel point coordinates corresponding to each original pixel point and the original image information, the transformed information set includes the transformed pixel point coordinates corresponding to each transformed pixel point, wherein the transformed image is obtained by geometric transformation of the original image; S300. According to the original pixel point coordinates, obtain the storage information set, the storage information set includes the storage area number corresponding to each original pixel point, recorded as the original storage number, and the original storage area The storage area address of the storage area corresponding to the number is recorded as the original storage address; wherein, the original storage numbers corresponding to the pixel points around each of the transformed pixel points are different; S400. The original image information is stored in the storage area corresponding to the original storage address; S500. According to the transformed pixel point coordinates of the transformed pixel point, according to the coordinate transformation strategy, the storage addresses of the four original pixel points around each of the transformed pixel points are obtained, which are recorded as transformed storage addresses; S600. According to the transformed storage address, the four original image information corresponding to the transformed storage address are retrieved at the same time; S700. The transformed image information set is traversed, and steps S500-S700 are repeated to obtain the original image information of the four original pixel points corresponding to all the transformed pixel points.

[0137] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments disclosed in the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0138] In addition, although the steps of the method in the present application are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0139] Through the description of the above implementations, those skilled in the art can easily understand that the example implementations described here can be implemented by software, or by combining software with necessary hardware.

[0140] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A parallel optimization algorithm for image bilinear interpolation, characterized in that: The steps include: S100 initializes the FPGA, so that the FPGA includes four storage areas, each of which has a unique storage area number, and the FPGA can simultaneously read the storage contents of the four storage areas in one clock cycle; S200. Acquire an original image information set of an original image and a transformed image information set of a transformed image, wherein the original image information set includes original pixel coordinates corresponding to each original pixel and original image information, and the transformed information set includes transformed pixel coordinates corresponding to each transformed pixel, wherein the transformed image is obtained by geometrically transforming the original image; S300. According to the original pixel coordinates, a storage information set is obtained, wherein the storage information set includes a storage area number corresponding to each of the original pixel points, recorded as an original storage number, and a storage area address of the storage area corresponding to the original storage area number, recorded as an original storage address; wherein the original storage numbers corresponding to the pixel points around each of the transformed pixel points are different; S400. Storing the original image information in a storage area corresponding to the original storage address; S500. According to the transformed pixel coordinates of the transformed pixel, in accordance with the coordinate transformation strategy, the storage addresses of the four original pixel points around each transformed pixel are obtained and recorded as transformed storage addresses; S600. According to the transformed storage address, simultaneously retrieve the four original image information corresponding to the transformed storage address; S700. Traverse the transformed image information set, and repeat steps S500-S700 to obtain original image information of four original pixel points corresponding to all the transformed pixel points.

2. The image bilinear interpolation parallel optimization algorithm according to claim 1, characterized in that: Step S300 includes the following steps: S310. According to the original pixel coordinates and storage classification strategy, the original storage number is obtained, and a storage area distribution map is obtained; S320. According to the original pixel coordinates and storage address strategy, obtain the original storage address corresponding to each original storage number; S330. Obtain the storage information set according to all the original storage numbers and the original storage addresses corresponding thereto.

3. The image bilinear interpolation parallel optimization algorithm according to claim 2, characterized in that: The storage area includes a first storage area, a second storage area, a third storage area and a fourth storage area, the storage area distribution diagram includes a plurality of storage area sets arranged along a vertical distribution, each of the storage area sets includes a plurality of storage subsets arranged along a horizontal distribution, each of the storage subsets includes two first storage subsets and a second storage subset arranged along a vertical distribution, the first storage subset includes the first storage area and the second storage area arranged along a horizontal distribution, the second storage subset includes the third storage area and the fourth storage area arranged along a horizontal distribution.

4. The image bilinear interpolation parallel optimization algorithm according to claim 3 is characterized in that: The storage classification strategy includes the following steps: S311. Obtaining the column coordinates and row coordinates of the original pixel coordinates of each original pixel, recorded as original row coordinates and original column coordinates; S312. Convert the original row coordinates and the original column coordinates into binary to obtain original binary row coordinates and original binary column coordinates; S313. Determine whether the last bit of the original binary column coordinate and the original binary row coordinate is an odd number or an even number. When both are even numbers, execute step S314; when the last bit of the original binary row coordinate is an even number and the last bit of the original binary column coordinate is an odd number, execute step S315; when the last bit of the original binary row coordinate is an odd number and the last bit of the original binary column coordinate is an even number, execute step S316; when both are odd numbers, execute step S317; S314. Using the number of the first storage area as the original storage number; S315. Using the number of the second storage area as the original storage number; S316. Using the number of the third storage area as the original storage number; S317. Use the number of the fourth storage area as the original storage number.

5. The image bilinear interpolation parallel optimization algorithm according to claim 4, characterized in that: The storage address strategy comprises the following steps: S321. Remove the last bit of the original binary column coordinate and the original binary row coordinate to obtain a transformed binary row coordinate and a transformed binary column coordinate; S322. Combine the transformed binary row coordinate and the transformed binary column coordinate to form the original storage address.

6. The image bilinear interpolation parallel optimization algorithm according to claim 5, characterized in that: Each of the storage subsets has the same transformed binary row coordinates and the same transformed binary column coordinates.

7. The image bilinear interpolation parallel optimization algorithm according to claim 3, characterized in that: The coordinate transformation strategy includes the following steps: S510. Obtain the row coordinates and column coordinates of the transformed pixel point coordinates, recorded as transformed row coordinates and transformed column coordinates; S520. Rounding the transformed row coordinates and the transformed column coordinates to obtain interpolated row coordinates and interpolated column coordinates; S530. Determine the parity of the interpolated row coordinates and the interpolated column coordinates. When the interpolated row coordinates and the interpolated column coordinates are both even numbers, execute step S540; when the interpolated column coordinates are odd numbers and the interpolated row coordinates are even numbers, execute step S550; when the interpolated column coordinates are even numbers and the interpolated row coordinates are odd numbers, execute step S560; when the interpolated row coordinates and the interpolated column coordinates are both odd numbers, execute step S570; S540. Using the original storage addresses of the four original pixel points around the transformed pixel point as the transformed storage addresses; S550. The transformed binary row coordinates of the original pixel points stored in the first storage area and the third storage area around the transformed pixel point remain unchanged, and the transformed binary column coordinates are added by one to obtain the transformed storage addresses corresponding to the first storage area and the third storage area; Using the original storage addresses of the original pixel points stored in the second storage area and the fourth storage area around the transformed pixel point as the transformed storage addresses corresponding to the second storage area and the fourth storage area; S560. The transformed binary column coordinates of the original pixel points stored in the first storage area and the second storage area around the transformed pixel point remain unchanged, and the transformed binary row coordinates are added by one to obtain the transformed storage addresses corresponding to the first storage area and the second storage area; Using the original storage addresses of the original pixel points stored in the third storage area and the fourth storage area around the transformed pixel point as the transformed storage addresses corresponding to the third storage area and the fourth storage area; S570. Add one to the transformed binary row coordinates and the transformed binary column coordinates of the original pixel points stored in the first storage area around the transformed pixel points to obtain the transformed storage address corresponding to the first storage area; the transformed binary column coordinates stored in the second storage area around the transformed pixel points remain unchanged, and the transformed binary row coordinates are added by one to obtain the transformed storage address corresponding to the second storage area; the transformed binary row coordinates stored in the third storage area around the transformed pixel points remain unchanged, and the transformed binary column coordinates are added by one to obtain the transformed storage address corresponding to the third storage area; the original storage coordinates stored in the fourth storage area around the transformed pixel points are used as the transformed storage address corresponding to the fourth storage area.

8. An image bilinear interpolation parallel optimization system, used to implement the image bilinear interpolation parallel optimization algorithm according to any one of claims 1 to 7, characterized in that: The system comprises: A configuration module, wherein the configuration module is configured to initialize the FPGA, so that the FPGA includes four storage areas, each of which has a unique storage area number, and the FPGA can simultaneously read the storage contents of the four storage areas in one clock cycle; an acquisition module, the acquisition module being configured to acquire an original image information set of an original image and a transformed image information set of a transformed image, the original image information set comprising original pixel point coordinates corresponding to each original pixel point and original image information, the transformed information set comprising transformed pixel point coordinates corresponding to each transformed pixel point, wherein the transformed image is obtained by geometrically transforming the original image; a first calculation module, the first calculation module being configured to obtain a storage information set according to the original pixel point coordinates, the storage information set comprising a storage area number corresponding to each of the original pixel points, recorded as an original storage number, and a storage area address of the storage area corresponding to the original storage area number, recorded as an original storage address; wherein the original storage numbers corresponding to the pixel points around each of the transformed pixel points are all different; A storage module, wherein the storage module is configured to store the original image information in a storage area corresponding to the original storage address; A second calculation module, the second calculation module is configured to obtain storage addresses of four original pixel points around each of the transformed pixel points according to the transformed pixel point coordinates of the transformed pixel points and in accordance with the coordinate transformation strategy, and record them as transformed storage addresses; A calling module, wherein the calling module is configured to call, according to the transformed storage address, four pieces of original image information corresponding to the transformed storage address at the same time; An output module is configured to traverse the transformed image information set, and repeatedly execute steps S500-S700 to obtain original image information of four original pixel points corresponding to all the transformed pixel points.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the image bilinear interpolation parallel optimization algorithm as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the image bilinear interpolation parallel optimization algorithm as described in any one of claims 1 to 7 are implemented.

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