Light emitting diode well layer control method and system based on ESD impedance matching

Abstract

The invention discloses a light-emitting diode well layer control method and system based on ESD impedance matching, and the method comprises the steps: adjusting the doping concentration of an N-type well layer and the doping concentration of a P-type well layer, changing the conductivity and carrier flow of the well layers, so as to improve the impedance of an ESD protection device, and adjusting the depth and width of the well layers, so as to improve the ESD protection device. The invention provides a light-emitting diode well layer control system based on ESD impedance matching to further optimize the impedance of an ESD protection device, the breakdown voltage and the leakage current in parameters of the ESD protection device can be optimized by verifying the influence of a well layer on current carrier flow and impedance so as to achieve the optimal impedance matching, and in addition, the invention further provides a light-emitting diode well layer control system based on ESD impedance matching. Comprising a doping concentration adjusting module, a well layer verification module, a carrier dynamic module and an impedance matching module, can automatically adjust and optimize the well layer structure, and meets the requirements of the IEC 61000-4-2 standard.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a light emitting diode well layer control method and system based on ESD impedance matching. Background Art

[0002] In the prior art, a diode well layer refers to a layer used to isolate different doped regions in a bipolar junction transistor (BJT) or a field effect transistor (FET). Its conductivity is between adjacent high-doped regions, thereby isolating and controlling the flow of carriers.

[0003] The name: Electrostatic Discharge Device is disclosed in Chinese Patent Publication No.: CN109103178B. The ESD device mentioned in the invention document includes multiple p-type regions and n-type regions, as well as shallow trench isolation (STI) regions. These structures will occupy a large silicon area. The document does not explain how the silicon area consumption of the ESD device is, nor does it compare with other ESD devices.

[0004] The ESD (Electrostatic Discharge) electrostatic protection technology in semiconductor diodes still has compatibility issues between the protection device and the protected device in the existing technology. There is impedance mismatch: the impedance characteristics of the ESD protection device do not match the impedance characteristics of the protected device (such as a diode), resulting in a large voltage spike during ESD discharge, causing damage to the protected device. The compatibility of the protection device and the protected device: the existing ESD protection technology cannot be effectively compatible with the protected device. For example, when protecting a diode, it will affect the performance of the diode or increase the silicon area consumption.

[0005] The light emitting diode well layer control method based on ESD impedance matching proposed in the present invention can effectively solve the difficult problems of ESD protection technology in the prior art, including impedance mismatch and compatibility problems between the protection device and the protected device. Summary of the invention

[0006] In order to solve the above-mentioned technical problems, the present invention provides a light emitting diode well layer control method and system based on ESD impedance matching.

[0007] The technical solution of the present invention is implemented as follows: a light emitting diode well layer control method and system based on ESD impedance matching, including a light emitting diode well layer control method based on ESD impedance matching: S1, by adjusting the doping concentration of the N-type well layer, changing the conductivity of the well layer, adjusting the carrier flow, increasing the doping concentration to reduce the conductivity of the well layer, adjusting the doping concentration of the P-type well layer, changing the conductivity of the well layer, and reducing the doping concentration to reduce the conductivity of the well layer; S2, adjusting the depth of the well layer, changing the distance between the well layer and the N-type and P-type regions, reducing the flow of carriers, and changing the area of ​​the well layer by adjusting the width of the well layer to improve the resistance of the ESD protection device; S3, verify the influence of the well layer on carrier flow and resistance; S4. Adjust the breakdown voltage and leakage current in the ESD protection device parameters to optimize impedance matching.

[0008] The light-emitting diode well layer control system based on ESD impedance matching includes a doping concentration adjustment module, a well layer verification module, a carrier dynamic module, and an impedance matching module; The doping concentration adjustment module is connected to the well layer verification module and the carrier dynamic module, and is used to calculate the carrier concentration of the N-type well layer and the conductivity of the doping concentration of the P-type well layer, and output the calculated values ​​to the well layer verification module; The well layer verification module is connected to the doping concentration adjustment module and the carrier dynamic module, and is used to adjust the depth and width of the well layer to improve the resistance of the ESD protection device after calculating the conductivity of the N-type well layer and the P-type well layer; The carrier dynamic module is connected with the doping concentration adjustment module, the well layer verification module, and the impedance matching module, and is used to simulate the carrier flow and impedance at different depths and widths, and compare the differences in carrier flow and impedance at different depths and widths; The impedance matching module is connected to the carrier dynamic module and is used to calculate the optimal combination of breakdown voltage and leakage current.

[0009] Furthermore, in the step S1, it is determined that the material can introduce holes to adjust the carrier concentration of the N-type well layer or the P-type well layer. First, the hole concentration is calculated. Based on the ratio of the hole concentration to the doping concentration, the molar fraction of the doping material is expressed. Then, the molar fraction of the doping material is calculated. The molar fraction is then substituted into the hole concentration formula to calculate the hole concentration. Then, the carrier concentration is evaluated, and the electron concentration The conductivity is calculated from the electron affinity and hole concentration, and finally from the carrier concentration and carrier mobility.

[0010] Furthermore, after calculating the conductivity of the N-type well layer and the P-type well layer, the S2 step improves the resistance of the ESD protection device by adjusting the depth and width of the well layer. The reference conductivity is calculated using the known conductivity data of the N-type well layer and the P-type well layer. According to the target resistance requirement IEC 61000-4-2 (electrostatic discharge immunity), the new well layer depth d and width w are determined. The calculated m and n values ​​are used in combination with the known reference conductivity. 0, calculate the new conductivity If it does not meet the requirements, the values ​​of d and w need to be readjusted.

[0011] Furthermore, in the S3 step, the influence of the well layer on the carrier flow and resistance is verified, and a simulation model of the N-type well layer and the P-type well layer is established. The model should include the depth, width, and doping concentration parameters of the well layer, and simulate the carrier flow and resistance at different depths and widths. The key parameters include conductivity, carrier concentration, and resistance. The differences in carrier flow and resistance at different depths and widths are compared, and the influence of the depth and width of the well layer on the carrier flow and resistance is determined to adjust the depth and width.

[0012] Furthermore, in the step S4, the breakdown voltage and leakage current in the ESD protection device parameters are adjusted to optimize the impedance matching, the optimal breakdown voltage and leakage current combination is calculated and selected to achieve the best impedance matching, and the breakdown voltage and leakage current are checked to see whether they meet the electrostatic discharge immunity requirements. If the breakdown voltage is less than Or the leakage current is greater than , it is necessary to readjust the values ​​of breakdown voltage and leakage current.

[0013] Beneficial Effects The light emitting diode well layer control method based on ESD impedance matching proposed in the present invention aims to solve the problems of ESD protection technology in the prior art, including impedance mismatch and compatibility problems between the protection device and the protected device, and has the following beneficial effects: Improve impedance matching performance: By adjusting the doping concentration of the N-type well layer and the P-type well layer, as well as the depth and width of the well layer, the present invention can optimize the impedance matching between the ESD protection device and the light-emitting diode, reduce the voltage spike caused by impedance mismatch, and thus protect the light-emitting diode from damage; Enhanced protection effect: By optimizing the parameters of the ESD protection device, such as breakdown voltage and leakage current, the present invention can improve the protection effect of the ESD protection device, so that it can better resist the damage caused by electrostatic discharge; Saving silicon area consumption: By precisely controlling the doping concentration, depth and width of the well layer, the present invention can reduce silicon area consumption and improve chip integration and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The light emitting diode well layer control system based on ESD impedance matching in the embodiment of the present invention The structural diagram of Figure 2 A light emitting diode well layer control method based on ESD impedance matching in an embodiment of the present invention Flow chart of the steps; Figure 3 is a flowchart describing the doping process in step S1 in an embodiment of the present invention; Figure 4 This is a flowchart of the steps of adjusting the depth and width of the well layer to improve the resistance of the ESD protection device in step S2 in an embodiment of the present invention; Figure 5 This is a flow chart of the steps of optimizing impedance matching in step S4 in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the objects and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with embodiments; it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0016] The preferred implementation methods of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these implementation methods are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0017] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0018] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0019] See also Figure 1-5 As shown, a light emitting diode well layer control method and system based on ESD impedance matching include a light emitting diode well layer control method based on ESD impedance matching: S1, by adjusting the doping concentration of the N-type well layer, changing the conductivity of the well layer, adjusting the carrier flow, increasing the doping concentration to reduce the conductivity of the well layer, adjusting the doping concentration of the P-type well layer, changing the conductivity of the well layer, and reducing the doping concentration to reduce the conductivity of the well layer; S2, adjusting the depth of the well layer, changing the distance between the well layer and the N-type and P-type regions, reducing the flow of carriers, and changing the area of ​​the well layer by adjusting the width of the well layer to improve the resistance of the ESD protection device; S3, verify the influence of the well layer on carrier flow and resistance; S4. Adjust the breakdown voltage and leakage current in the ESD protection device parameters to optimize impedance matching.

[0020] The light-emitting diode well layer control system based on ESD impedance matching includes a doping concentration adjustment module, a well layer verification module, a carrier dynamic module, and an impedance matching module; The doping concentration adjustment module is connected to the well layer verification module and the carrier dynamic module, and is used to calculate the carrier concentration of the N-type well layer and the conductivity of the doping concentration of the P-type well layer, and output the calculated values ​​to the well layer verification module; The well layer verification module is connected to the doping concentration adjustment module and the carrier dynamic module, and is used to adjust the depth and width of the well layer to improve the resistance of the ESD protection device after calculating the conductivity of the N-type well layer and the P-type well layer; The carrier dynamic module is connected with the doping concentration adjustment module, the well layer verification module, and the impedance matching module, and is used to simulate the carrier flow and impedance at different depths and widths, and compare the differences in carrier flow and impedance at different depths and widths; The impedance matching module is connected to the carrier dynamic module and is used to calculate the optimal combination of breakdown voltage and leakage current.

[0021] Furthermore, in the step S1, it is determined that the material can introduce holes to adjust the carrier concentration of the N-type well layer or the P-type well layer. First, the hole concentration is calculated. Based on the ratio of the hole concentration to the doping concentration, the molar fraction of the doping material is expressed. Then, the molar fraction of the doping material is calculated. The molar fraction is then substituted into the hole concentration formula to calculate the hole concentration. Then, the carrier concentration is evaluated, and the electron concentration The conductivity is calculated from the electron affinity and hole concentration, and finally from the carrier concentration and carrier mobility.

[0022] Specifically, in step S1, the doping concentration of the N-type well layer is adjusted to change the conductivity of the well layer: S101. To determine whether the material can introduce holes and thus increase the carrier concentration of the N-type well layer, a mathematical calculation formula is required to describe the doping process: The formula for hole concentration (hole carrier concentration) is:

[0023] in: is the hole concentration (hole carrier concentration); is the doping concentration (the doping concentration of the N-type well layer); x is the ratio of the hole concentration to the doping concentration, expressed as the mole fraction of the doping material; S102. Calculate the molar fraction of doping material: Phosphorus (P) is selected as the doping material by default, and its molar mass is 30.97 g / mol; The total mass of the doping material is assumed to be The mass of phosphorus is , then the molar fraction x of phosphorus is:

[0024] Where: 1000 is the conversion of mass units from g to kg, 30.97 is the molar mass of phosphorus; S103, calculate the hole concentration: Substituting the mole fraction x into the hole concentration formula, we can calculate the hole concentration. ; S104, evaluating the carrier concentration of the N-type well layer: Total carrier concentration in the N-type well layer is the sum of the hole concentration and the electron concentration; Electron concentration Calculated from electron affinity and hole concentration; Electron concentration The formula is:

[0025] in: is the doping concentration, x is the ratio of the hole concentration to the doping concentration; S105. Calculate the conductivity of the N-type well layer: Conductivity Calculated by carrier concentration and carrier mobility; The formula for conductivity is:

[0026] in: is the carrier mobility of the N-type well layer; At the same time, when adjusting the doping concentration of the P-type well layer to change the conductivity of the well layer, boron (B) is selected as the doping material in calculating the molar fraction of the doping material. Its molar mass is 10.81 g / mol. In calculating the conductivity of the P-type well layer, is the carrier mobility of the P-type well layer.

[0027] Furthermore, after calculating the conductivity of the N-type well layer and the P-type well layer, the S2 step improves the resistance of the ESD protection device by adjusting the depth and width of the well layer. The reference conductivity is calculated using the known conductivity data of the N-type well layer and the P-type well layer. According to the target resistance requirement IEC 61000-4-2 (electrostatic discharge immunity), the new well layer depth d and width w are determined. The calculated m and n values ​​are used in combination with the known reference conductivity. 0, calculate the new conductivity If it does not meet the requirements, the values ​​of d and w need to be readjusted.

[0028] Specifically, after calculating the conductivity of the N-type well layer and the P-type well layer, the S2 step improves the resistance of the ESD protection device by adjusting the depth and width of the well layer: S201, the relationship between the conductivity of the well layer and the depth and width is expressed as:

[0029] in: is the conductivity of the well layer; 0 is the reference conductivity; is the depth of the well layer; is the reference depth; is the width of the well layer; is the reference width; m and n are material-dependent constants used to describe the effects of depth and width on conductivity; S202, calculating the reference conductivity using the known conductivity data of the N-type well layer and the P-type well layer, and calculating the values ​​of m and n by the least square method or other fitting methods; S203. Determine the new well depth d and width w according to the target impedance requirement IEC 61000-4-2 (electrostatic discharge immunity), using the calculated m and n values, combined with the known reference conductivity 0, calculate the new conductivity ; S204. Verify by calculation whether the new well layer depth and width meet the impedance requirements of IEC 61000-4-2 (electrostatic discharge immunity). If not, readjust the values ​​of d and w and repeat the above calculation and verification process.

[0030] Furthermore, in the S3 step, the influence of the well layer on the carrier flow and resistance is verified, and a simulation model of the N-type well layer and the P-type well layer is established. The model should include the depth, width, and doping concentration parameters of the well layer, and simulate the carrier flow and resistance at different depths and widths. The key parameters include conductivity, carrier concentration, and resistance. The differences in carrier flow and resistance at different depths and widths are compared, and the influence of the depth and width of the well layer on the carrier flow and resistance is determined to adjust the depth and width.

[0031] Specifically, the S3 step verifies the effect of the well layer on carrier flow and resistance: Establish simulation models of N-type well layer and P-type well layer. The model should include the depth, width and doping concentration parameters of the well layer, simulate the carrier flow and resistance at different depths and widths, and the key parameters include conductivity, carrier concentration and resistance. Compare the differences in carrier flow and resistance at different depths and widths, determine the influence of well layer depth and width on carrier flow and resistance, and adjust the depth and width; Preset parameters: N-type well layer doping concentration

[0032] P-type well layer doping concentration

[0033] Reference doping concentration

[0034] Reference doping concentration

[0035] Reference conductivity

[0036] Reference conductivity

[0037] Carrier mobility

[0038] Carrier mobility

[0039] Electric field strength

[0040] Calculate the conductivity of the N-type well layer and the P-type well layer:

[0041]

[0042] Since a=b=1, the simplified formula is:

[0043]

[0044]

[0045]

[0046] Calculate the total carrier concentration of the N-type well layer and the P-type well layer:

[0047]

[0048]

[0049]

[0050] Calculate the resistance of the N-type well layer and the P-type well layer:

[0051]

[0052]

[0053] Adjust the well depth and width: The test well layer depth d=100 nm and the well layer width w=50 nm were preset. The depth and width were changed to observe the change in conductivity. The formula was used to calculate the conductivity, total carrier concentration and resistance at different depths and widths. Then, these parameters were compared to determine the impact of the well layer depth and width on carrier flow and resistance.

[0054] Furthermore, in the step S4, the breakdown voltage and leakage current in the ESD protection device parameters are adjusted to optimize the impedance matching, the optimal breakdown voltage and leakage current combination is calculated and selected to achieve the best impedance matching, and the breakdown voltage and leakage current are checked to see whether they meet the electrostatic discharge immunity requirements. If the breakdown voltage is less than Or the leakage current is greater than , it is necessary to readjust the values ​​of breakdown voltage and leakage current.

[0055] Specifically, the adjustment of the breakdown voltage and leakage current in the ESD protection device parameters in step S4 to optimize the impedance matching is achieved by the following mathematical calculation formula: The optimal combination of breakdown voltage and leakage current is selected by calculation based on the preset data of IEC 61000-4-2 (electrostatic discharge immunity) to achieve the best impedance matching; Define the parameters: Reference breakdown voltage

[0056] Reference leakage current

[0057] Reference constant k=1 Electrostatic discharge immunity requirements

[0058] Electrostatic discharge immunity requirements

[0059] Calculate the optimal breakdown voltage and leakage combination: S401. Determine the breakdown voltage according to the electrostatic discharge immunity requirements , determine the breakdown voltage ; The calculation formula is as follows:

[0060] Since k=1, the formula simplifies to:

[0061] Substitute the preset parameters to calculate the breakdown voltage:

[0062] S402, determine the leakage current: According to the electrostatic discharge immunity requirements , determine the leakage current ; The calculation formula is as follows:

[0063] Substitute the preset parameters to calculate the leakage current:

[0064]

[0065]

[0066] S403, verify optimization results: Check whether the breakdown voltage and leakage current meet the ESD immunity requirements; If the breakdown voltage is less than Or the leakage current is greater than , then it is necessary to readjust the breakdown voltage and leakage current values; Through the above process, the optimal combination of breakdown voltage and leakage current is determined to achieve the best impedance matching, which helps to improve the performance of ESD protection devices and meet the requirements of IEC 61000-4-2 standard.

[0067] Specifically, ESD protection devices refer to devices used to protect light-emitting diodes from damage by electrostatic discharge (ESD). These devices include the following types: TVS diode (Transient Voltage Suppressor): TVS diode is a fast-response voltage protection device that can quickly absorb or suppress voltage spikes when an ESD event occurs. It is used to protect integrated circuits from overvoltage caused by ESD. MOSFET (Metal Oxide Semiconductor Field Effect Transistor): MOSFET has a fast drain current rise time and is used as an ESD protection device to provide good ESD protection performance while having a small leakage current; GDT (Gas Discharge Tube): GDT is a high voltage ESD protection device that can discharge quickly when an ESD event occurs. It is suitable for high voltage applications and can provide protection for equipment. SCR (Thyristor): SCR turns on quickly when an ESD event occurs, thereby protecting the circuit. It is used in high current applications and can provide effective ESD protection. BJT (Bipolar Junction Transistor): BJTs are used as ESD protection devices, although their response speed may not be as fast as MOSFETs or TVS diodes, they are suitable for applications that do not require high response speed; In practical applications, by optimizing the parameters of ESD protection devices, such as breakdown voltage and leakage current, their protection performance can be improved to ensure that the light-emitting diode can be effectively protected when an ESD event occurs.

[0068] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and rules of the present invention shall be included in the protection scope of the present invention.

Claims

1. A light emitting diode well layer control method based on ESD impedance matching, characterized in that: S1, by adjusting the doping concentration of the N-type well layer, adjusting the conductivity of the well layer and the flow of carriers, adjusting the doping concentration to reduce the conductivity of the well layer, and adjusting the doping concentration of the P-type well layer to change the conductivity of the well layer; S2, adjusting the depth of the well layer, changing the distance between the well layer and the N-type and P-type regions, to reduce the flow of carriers, and changing the area of ​​the well layer by adjusting the width of the well layer for impedance adjustment of the ESD protection device; S3, verify the influence of the well layer on carrier flow and resistance; S4. Adjust the breakdown voltage and leakage current in the ESD protection device parameters to optimize impedance matching.

2. The light emitting diode well layer control method based on ESD impedance matching according to claim 1, characterized in that: In the step S1, the carrier concentration of the N-type well layer or the P-type well layer is adjusted. First, the hole concentration is calculated. Based on the ratio of the hole concentration to the doping concentration, the molar fraction of the doping material is expressed. Then, the molar fraction of the doping material is calculated. Then, the molar fraction is substituted into the hole concentration formula to calculate the hole concentration. Then, the carrier concentration is evaluated, where the electron concentration N e The conductivity is calculated from the electron affinity and hole concentration, and finally from the carrier concentration and carrier mobility.

3. The light emitting diode well layer control method based on ESD impedance matching according to claim 2, characterized in that: The process of changing the conductivity of the well layer by doping concentration in step S1 is as follows: The formula for hole concentration is: in: is the hole concentration; is the doping concentration; x is the ratio of the hole concentration to the doping concentration, expressed as the mole fraction of the doping material; Calculate the mole fraction of doping material: Phosphorus was selected as the doping material, with a molar mass of 30.97 g / mol; Assuming the total mass of the doping material is Mg and the mass of phosphorus is mg, the molar fraction x of phosphorus is: Where: 1000 is the conversion of mass units from g to kg, 30.97 is the molar mass of phosphorus; Calculate the hole concentration: Substituting the mole fraction x into the hole concentration formula, we can calculate the hole concentration. ; Evaluate the carrier concentration in the N-type well layer: Electron concentration The formula is: in: is the doping concentration, x is the ratio of the hole concentration to the doping concentration; Calculate the conductivity of the N-type well layer: The formula for conductivity is: in: is the carrier mobility of the N-type well layer; At the same time, when adjusting the doping concentration of the P-type well layer to change the conductivity of the well layer, boron is selected as the doping material in calculating the molar fraction of the doping material, and its molar mass is 10.81 g / mol. In calculating the conductivity of the P-type well layer, μn is the carrier mobility of the P-type well layer.

4. The light emitting diode well layer control method based on ESD impedance matching according to claim 1, characterized in that: In step S2, after calculating the conductivity of the N-type well layer and the P-type well layer, the impedance of the ESD protection device is adjusted by adjusting the depth and width of the well layer. The reference conductivity is calculated using the known conductivity data of the N-type well layer and the P-type well layer. According to the target impedance requirement IEC 61000-4-2, the new well layer depth d and width w are determined. The calculated m and n values ​​are used in combination with the known reference conductivity. 0, calculate the new conductivity If it does not meet the requirements, the values ​​of d and w need to be readjusted.

5. The light emitting diode well layer control method based on ESD impedance matching according to claim 4, characterized in that: In step S2, after calculating the conductivity of the N-type well layer and the P-type well layer, the resistance of the ESD protection device is adjusted by adjusting the depth and width of the well layer; The relationship between the well layer conductivity and depth and width is expressed as: in: is the conductivity of the well layer; is the reference conductivity; d is the depth of the well layer; is the reference depth; w is the width of the well layer; is the reference width; m and n are material constants that describe the effect of depth and width on conductivity.

6. The light emitting diode well layer control method based on ESD impedance matching according to claim 1, characterized in that: In the step S3, the influence of the well layer on the carrier flow and resistance is verified, and a simulation model of the N-type well layer and the P-type well layer is established. The model should include the depth, width, and doping concentration parameters of the well layer, and simulate the carrier flow and resistance at different depths and widths. The key parameters include conductivity, carrier concentration, and resistance. The differences in carrier flow and resistance at different depths and widths are compared, and the influence of the depth and width of the well layer on the carrier flow and resistance is determined to adjust the depth and width.

7. The light emitting diode well layer control method based on ESD impedance matching according to claim 6, characterized in that: In the step S3, the influence of the depth and width of the well layer on the carrier flow and resistance is determined to adjust the depth and width. First, the conductivity of the N-type well layer and the P-type well layer is calculated. Since a=b=1, the formula is simplified, and then the total carrier concentration of the N-type well layer and the P-type well layer is calculated. The resistance of the N-type well layer and the P-type well layer is further calculated, and finally the depth and width of the well layer are adjusted.

8. The light emitting diode well layer control method based on ESD impedance matching according to claim 1, characterized in that: In the step S4, the breakdown voltage and leakage current in the ESD protection device parameters are adjusted to optimize the impedance matching, the optimal breakdown voltage and leakage current combination is calculated and selected, and the breakdown voltage and leakage current are checked to see whether they meet the electrostatic discharge immunity requirements. If the breakdown voltage is less than Or the leakage current is greater than , it is necessary to readjust the values ​​of breakdown voltage and leakage current.

9. The light emitting diode well layer control method based on ESD impedance matching according to claim 8, characterized in that: In the step S4, the breakdown voltage and leakage current combination are calculated and selected for impedance matching. First, the breakdown voltage is determined according to the electrostatic discharge immunity requirements. , determine the breakdown voltage , The calculation formula is as follows: Secondly, determine the leakage current according to the ESD immunity requirements , determine the leakage current ; The calculation formula is as follows: If the breakdown voltage is less than Or the leakage current is greater than , then it is necessary to readjust the breakdown voltage and leakage current values; Among them, define the parameters: Reference breakdown voltage Reference leakage current Reference constant k=1 Electrostatic discharge immunity requirements Electrostatic discharge immunity requirements . The light emitting diode well layer control system based on ESD impedance matching is characterized by: It includes doping concentration adjustment module, well layer verification module, carrier dynamic module and impedance matching module; The doping concentration adjustment module is connected to the well layer verification module and the carrier dynamic module, and is used to calculate the carrier concentration of the N-type well layer and the conductivity of the doping concentration of the P-type well layer, and output the calculated values ​​to the well layer verification module; The well layer verification module is connected to the doping concentration adjustment module and the carrier dynamic module, and is used to adjust the depth and width of the well layer after calculating the conductivity of the N-type well layer and the P-type well layer; The carrier dynamic module is connected with the doping concentration adjustment module, the well layer verification module, and the impedance matching module, and is used to simulate the carrier flow and impedance at different depths and widths, and compare the differences in carrier flow and impedance at different depths and widths; The impedance matching module is connected to the carrier dynamic module and is used to calculate the optimal combination of breakdown voltage and leakage current.

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