Chip testing method, system and equipment and storage medium

Abstract

The invention provides a chip test method, system and device and a storage medium, the chip test device comprises a main control board, a digital test board and a cooperation test board which are mutually connected through a backboard, and the digital test board and the cooperation test board are test board cards of different types. The test operation data of the cooperation test board and the time sequence of the test vector of the digital test board are synchronized; and the main control board synchronously triggers the digital test board and the matching test board through the test instruction, so that the matching test board executes a test operation according to the test operation data, and the digital test board synchronously executes the test operation according to the test vector so as to synchronously test the chip to be tested. The main control board can control different types of board cards to execute tests in a software instruction triggering mode, and due to the fact that the test operation data are synchronous with the time sequence of the test vectors, synchronous matching can be achieved when the digital test board and the matching test board execute the test operation according to the test data of the digital test board and the matching test board. And the synchronization precision of different types of board cards during chip testing is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip technology, and in particular to a chip testing method, system, equipment and storage medium. Background Art

[0002] With the increasing complexity of System on Chip (SoC) chips, a functional test of SoC chips often requires different types of channel input signals to cooperate with each other, and then capture and analyze different types of output signals. Therefore, unlike digital testers that can complete chip testing through a single digital test board, SoC chip testing requires not only digital test boards, but also other types of boards to meet the different testing requirements of SoC chips, such as high-voltage boards that provide high-voltage signals and mixed-signal boards that provide various types of analog signals.

[0003] Since the signals of different test boards are interrelated during the chip testing process, each test needs to be synchronized during the chip testing, otherwise it will affect the timing of the chip testing. However, due to the design and signal transmission distance, there are deviations in the signal outputs of different types of test boards during the testing process, resulting in low synchronization accuracy of different types of boards. Summary of the invention

[0004] The present invention provides a chip testing method, system, device and storage medium to solve the problem that signal outputs of different types of boards and cards in the existing testing process have deviations, resulting in low synchronization accuracy of different types of boards and cards.

[0005] In a first aspect, an embodiment of the present application provides a chip testing method, which is applied to a chip testing device, wherein the chip testing device includes a main control board, a digital test board, and a matching test board connected to each other through a backplane, wherein the digital test board and the matching test board are test boards of different types; the digital test board stores a pre-generated test vector, and the matching test board stores a pre-generated test operation data, and the test operation data is synchronized with the test vector timing; the method includes:

[0006] The main control board synchronously triggers the digital test board and the matching test board through test instructions, so that the matching test board performs test operations according to the test operation data, and the digital test board synchronously performs test operations according to the test vector, so as to perform synchronous testing on the chip to be tested.

[0007] Optionally, the main control board synchronously triggers the digital test board and the matching test board through the test instruction, so that the matching test board performs the test operation according to the test operation data, and the digital test board synchronously performs the test operation according to the test vector, so as to perform synchronous testing on the chip to be tested, including:

[0008] The main control board sends a test instruction so that the digital test board and the matching test board respond to the test instruction to wait for a trigger pulse signal, and the trigger pulse signal is used to synchronously trigger the digital test board and the matching test board to perform a test operation;

[0009] The main control board sends a trigger pulse signal synchronously so that the cooperative test board performs a test operation according to the test operation data after receiving the trigger pulse signal, and the digital test board performs a test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform synchronous testing on the chip to be tested.

[0010] Optionally, the cooperation test board performs a test operation according to the test operation data after receiving the trigger pulse signal, and the digital test board performs a test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform synchronous testing on the chip to be tested, including:

[0011] After receiving the trigger pulse signal, the cooperation test board performs delay adjustment according to the first delay time, and performs the test operation according to the test operation data after the delay adjustment, so as to trigger and output the analog signal to the chip to be tested, and / or trigger the sampling operation of the output signal of the chip to be tested;

[0012] After receiving the trigger pulse signal, the digital test board performs delay adjustment according to the second delay time, and performs a test operation according to the test vector after the delay adjustment, so as to generate and synchronously output a test signal to the chip under test, and / or trigger a sampling operation of the output signal of the chip under test, so as to realize synchronous testing of the chip under test;

[0013] Among them, the first delay time and the second delay time are respectively used to perform delay calibration on the signals output by the matching test board and the digital test board to ensure that the matching test board and the digital test board can output signals synchronously.

[0014] Optionally, the test operation data includes analog signal data and signal trigger data, the signal trigger data is synchronized with the timing of the test vector, the delay adjustment is performed according to the first delay time, and the test operation is performed according to the test operation data to trigger and output the analog signal to the chip under test, including:

[0015] After the first delay time is delayed, the cooperation test board determines the trigger time of each analog signal in the analog signal data according to the signal trigger data;

[0016] Cooperate with the test board to trigger and output the corresponding analog signal to the chip under test at the trigger time of each analog signal.

[0017] Optionally, the chip testing device further includes a calibration board, the digital test board and the matching test board are respectively connected to the calibration board, and the first delay time and the second delay time are calibrated in the following manner:

[0018] The main control board synchronously triggers the digital test board and the matching test board, so that the digital test board and the matching test board output signals to the calibration board respectively, and controls the calibration board to receive the signal and record the receiving time;

[0019] The main control board receives the first receiving time and the second receiving time fed back by the calibration board, and calibrates the first delay time and the second delay time according to the first receiving time and the second receiving time;

[0020] Among them, the first receiving time is the time when the calibration board receives the output signal of the matching test board, and the second receiving time is the time when the calibration board receives the output signal of the digital test board.

[0021] Optionally, the chip testing device includes a data generating device, the test operation data includes analog signal data of the chip to be tested and signal trigger data for triggering analog signal output, and the test operation data of the test board is obtained in the following manner:

[0022] The data generating device determines the analog signal data output by the matching test board to the chip to be tested according to the test task, and determines the corresponding relationship between the signal triggering time of the digital test board and the matching test board to obtain the triggering time corresponding relationship;

[0023] The data generating device generates signal trigger data of the matching test board which is synchronized with the test vector timing according to the corresponding relationship between the test vector and the trigger time.

[0024] Optionally, according to the corresponding relationship between the test vector and the trigger time, generating signal trigger data of the matching test board synchronized with the test vector timing includes:

[0025] The data generating device reads the test vector of the digital test board, obtains a plurality of test vector rows arranged in time sequence in the test vector, and the test vector rows are used to indicate the test operation of the digital test board on the chip to be tested at the current time point;

[0026] The data generating device generates trigger information for triggering the test board to output analog signals according to each test vector row, obtains multiple trigger information arranged in time sequence, and outputs the obtained signal trigger data.

[0027] Optionally, the trigger information is represented by a trigger flag bit, and according to each test vector row, trigger information for triggering the test board to output an analog signal is generated accordingly, a plurality of trigger information arranged in time sequence is obtained, and signal trigger data is output, including:

[0028] When it is determined that the cooperation test board needs to output an analog signal at a time point of the test vector row, a trigger flag of the analog signal is generated at a corresponding position of the test vector row to obtain multiple trigger information;

[0029] When it is determined that the cooperation test board does not need to output an analog signal at a time point of the test vector row, a preset value is generated at a corresponding position of the test vector row to obtain a plurality of preset values, and the preset value is different from the trigger flag bit;

[0030] According to the timing information of the test vector, multiple trigger information and preset values ​​are output to obtain signal trigger data.

[0031] In a second aspect, an embodiment of the present application provides a chip testing device, including a main control board, a digital test board, and a matching test board interconnected through a backplane, wherein the digital test board and the matching test board are test boards of different types;

[0032] The digital test board stores pre-generated test vectors, and the matching test board stores pre-generated test operation data, and the test operation data is synchronized with the test vectors in timing;

[0033] The main control board synchronously triggers the digital test board and the matching test board through test instructions, so that the matching test board performs test operations according to the test operation data, and the digital test board synchronously performs test operations according to the test vector, so as to perform synchronous testing on the chip to be tested.

[0034] In a third aspect, an embodiment of the present application provides a chip testing system, including a chip to be tested and a chip testing device, wherein the chip testing device includes a main control board, a digital test board, and a matching test board interconnected through a backplane, wherein the digital test board and the matching test board are test boards of different types; the digital test board stores pre-generated test vectors, and the matching test board stores pre-generated test operation data, and the test operation data is synchronized with the timing of the test vectors;

[0035] The main control board synchronously triggers the digital test board and the matching test board through test instructions, so that the matching test board performs test operations according to the test operation data, and the digital test board synchronously performs test operations according to the test vector, so as to perform synchronous testing on the chip to be tested.

[0036] In a fourth aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned chip testing method when executing the computer program.

[0037] In a fifth aspect, an embodiment of the present application provides a readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned chip testing method are implemented.

[0038] In a scheme provided by the above chip testing method, system, equipment and storage medium, the chip testing equipment includes a main control board, a digital test board and a matching test board connected to each other through a backplane, and the digital test board and the matching test board are test boards of different types; the digital test board stores pre-generated test vectors, and the matching test board stores pre-generated test operation data, and the test operation data is synchronized with the test vector; the main control board synchronously triggers the digital test board and the matching test board through a test instruction, so that the matching test board performs a test operation according to the test operation data, and the digital test board performs a test operation synchronously according to the test vector, so as to perform a synchronous test on the chip to be tested. In this embodiment, the main control board and different types of boards are connected through a backplane, so that the main control board can control different types of boards to perform tests by triggering software instructions, and because the test operation data is synchronized with the test vector, the digital test board and the matching test board can perform synchronous cooperation when performing test operations according to their respective test data, so as to achieve the purpose of chip synchronization test, and based on the high-precision synchronization mechanism of the digital test board test vector, the operations of other matching test boards are synchronized, and the synchronization accuracy of different types of boards during chip testing is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0040] Figure 1 is a schematic structural diagram of a chip in one embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of a test process of a chip test in one embodiment of the present invention;

[0042] Figure 3 is a schematic structural diagram of a chip testing system in one embodiment of the present invention;

[0043] Figure 4 yes Figure 3 A schematic diagram of the structure of a chip testing device;

[0044] Figure 5 is a schematic diagram of a process of a chip testing method in one embodiment of the present invention;

[0045] Figure 6 It is a schematic diagram of a function realization process of a digital test board and a matching test board in one embodiment of the present invention;

[0046] Figure 7is a schematic diagram of generating signal trigger data in test operation data in one embodiment of the present invention;

[0047] Figure 8 is another schematic diagram of generating signal trigger data in test operation data in one embodiment of the present invention;

[0048] Fig. 9 yes Figure 5 A schematic diagram of an implementation process of step S10;

[0049] Fig.10 It is a schematic diagram of output signals of a digital test board and a matching test board in one embodiment of the present invention;

[0050] Fig.11 It is a schematic diagram of another function realization process of the digital test board and the matching test board in one embodiment of the present invention;

[0051] Fig.12 It is a structural schematic diagram of an electronic device in one embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or their collections. It should also be understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0054] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0055] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0056] It should be understood that the order of execution of the steps in the following embodiments does not imply a precedence of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0057] In order to illustrate the technical solution of the present invention, specific embodiments are provided below for illustration.

[0058] It should be understood that as the scale of chips increases, the number of pins of a single chip increases. For example, high-performance control chips have reached more than 100 pins. In order to make full use of the resources of the test equipment, the pins of the same chip may be assigned to different test boards for testing. For digital chips, digital test boards can be used to complete their testing work. The digital test board generates a test analog signal and outputs it to the chip. The digital test board captures the test output of the chip and compares it with the expected signal. However, the testing of some chips (such as SoC chips) requires not only a digital test board, but also other types of boards to meet the different testing requirements of SoC chips, such as high-voltage boards that provide high-voltage signals and mixed-signal boards that provide various types of analog signals. Take the analog-to-digital converter (ADC) test of the SoC chip as an example. Usually, a digital board and a mixed-signal board are required to complete the test together. The mixed-signal board gives various single-tone signals, and the digital board controls the synchronous sampling of the ADC in the SoC chip through test vectors, and analyzes the sampled digital signals to obtain the static and dynamic indicators of the ADC. For example Figure 1, a SoC chip includes a digital circuit (digitalcircuit), an operational amplifier OP, an analog-to-digital converter ADC, a power supply (power), a high-voltage driver circuit (HV driver) and a high-speed interface (serdes). The test boards required to test the SoC chip may include a power board DPS (Device PowerSupply), a measurement board PMU (Parameter Measurement Unit), a digital test board DIG (digital testboard), a mixed signal board MIX, a high-voltage test board (HV source), and a high-speed interface (High Speed ​​Interface, HSIF) board. Among them, the power supply is provided by the power board DPS; the operational amplifier OP requires the measurement board PMU to provide a reference source. The digital circuit provides an analog signal through the digital test board DIG; the ADC test requires the mixed signal board MIX to provide a high-purity single-tone signal for coordinated testing; during the current test, the high-voltage driver circuit requires a high-voltage test board (HV source) to provide high voltage and large current, and to cooperate with the digital test board for testing; the high-speed interface requires the HSIF test board to provide an analog signal, and to cooperate with the digital test board for testing.

[0059] During the test process, since the signals of different test boards are interrelated during the chip test process, each test needs to be synchronized during the chip test, otherwise it will affect the timing of the chip test. Due to the design and signal transmission distance, there is a time deviation in the signal output of different types of test boards during the test process, resulting in low synchronization accuracy of different types of boards, affecting the chip test effect. For some high-speed test vector patterns, for example, a 100MHz frequency means a test cycle of 10ns, and the synchronization accuracy between the test board channels must reach the ps level to ensure that the generated waveform meets the timing requirements of the chip. In order to avoid the situation of signal synchronization between different boards, it is usually necessary to design additional synchronization protocols or introduce additional hardware circuits, such as connecting each board through a cable, and laying out the routing of each board to form a synchronization line, so as to complete the synchronization between different types of boards. However, the synchronization test method that requires the introduction of additional synchronization protocols or hardware circuits is costly and difficult to apply to the existing chip test architecture. In order to solve this problem, in the traditional solution, the synchronization between different types of boards is usually achieved by software instruction triggering, that is, multiple sets of test instructions are used to trigger the corresponding test boards at each trigger node, so that each test board performs the test operation according to the test instructions. However, this method requires multiple instruction triggering, which increases the triggering time cost, slows the test speed, and leads to low chip test efficiency.

[0060] Take ADC testing as an example. In order to obtain the performance indicators of ADC such as integral nonlinearity (INL) and differential nonlinearity (DNL), it is necessary to provide a high-precision voltage signal as a sampling point for the ADC of the chip under test through a mixed signal board. The digital test board runs the test vector to input the test signal to trigger the ADC to perform signal sampling and digital conversion, and capture the conversion code output by the ADC. For a 10-bit ADC, the mixed signal board needs to provide 1024 different voltage signals; if the voltage input range of the ADC is 5V, 5V / 1024=5mV, then the mixed signal board outputs 1024 voltage signals that increase by 5mV in sequence. The digital test board outputs the test signal (such as a digital waveform) at the corresponding time to trigger the ADC to perform voltage sampling. After sampling the voltage signal, the ADC performs digital conversion and outputs it. The digital test board runs the test vector to capture the conversion code (digital output) output by the ADC. Figure 2 As shown. Among them, Figure 2 The 0mV, 5mV, 10mV...10V on the left side of the middle represent the voltage signals triggered and output by the mixed signal board at different times; Figure 2 The array on the right side 0000000000, 0000000001, 0000000010...1111111111 represents the conversion code captured by the digital test board. If the traditional software trigger method is used, the host computer first sends a software instruction to let the mixed signal board generate a high-precision voltage signal, and then sends a software instruction to let the digital test board run the test vector output to trigger the sampled test signal and obtain the ADC conversion code. This process needs to be repeated 1024 times to complete the test of all sampling points. The test speed is slow, resulting in low chip test efficiency.

[0061] In view of the above problems, the chip testing method provided by the embodiment of the present invention can be applied in Figure 3 In the chip testing system shown, the chip testing system includes a chip testing device and a chip to be tested. The chip testing device is connected to the pins of the chip to be tested. The chip to be tested may be a SoC chip.

[0062] The chip test equipment includes a backplane, a main control board, a digital test board and a matching test board connected to each other through the backplane, and the digital test board and the matching test board are test boards of different types. Figure 4As shown, a plurality of mounting slots are provided on the back panel of the chip testing equipment, and the mounting slots on the back panel can be used to install the main control card, different types of test boards and necessary resource boards. Different types of test boards include at least a digital test board DIG and a mixed signal board MIX. The resource board includes a power board DPS and a measurement board PMU. In other embodiments, the matching test board for chip testing in cooperation with the digital test board, that is, other test boards can also be HSIF test boards or high-voltage test boards. Among them, the main control card and different types of boards can be connected via the high-speed serial bus PCle on the back panel. The back panel is also provided with a power supply for powering the main control card and each board, and a clock for subsequent synchronization testing of the test board.

[0063] Wherein, before executing the test task of the chip to be tested through the chip testing equipment, it is necessary to generate the test vector of the digital test board and the test operation data of the matching test board in advance according to the test task; the test vector of the digital test board is the test execution data of the digital test board to execute the test task, and the execution of the test vector can complete the test task of the chip to be tested; the test operation data of the matching test board is the data required to complete the test operation steps when the matching test board executes the test task, and the matching test board executes the test operation data to complete the test task of the chip to be tested. Wherein, the test operation data of the matching test board is synchronized with the timing of the test vector of the digital test board. Then, the test vector of the digital test board is downloaded and entered into the digital test board, and the test operation data of the matching test board is downloaded and entered into the matching test board, so that the digital test board stores the pre-generated test vector, and the matching test board stores the pre-generated test operation data. Wherein, the test vector and the test operation data can be sent to the digital test board and the matching test board respectively through the main control card. When the chip testing equipment is used to execute the test task of the chip to be tested, the main control board synchronously triggers the digital test board and the matching test board through the test instructions, so that the matching test board performs the test operation according to the test operation data, and the digital test board synchronously performs the test operation according to the test vector, so as to realize the synchronous testing of the chip to be tested.

[0064] It should be understood that different test tasks and different test operations performed by the test board will result in different test operation data of the test board; correspondingly, the test operations performed by the digital test board are also different, and the test vectors performed by the digital test board are different.

[0065] In one embodiment, the test operation data of the matching test board includes analog signal data output by the matching test board to the chip to be tested, and signal trigger data for triggering each analog signal in the analog signal data output by the matching test board, that is, the analog signal data includes multiple analog signals output to the chip to be tested at different time points, and the signal trigger data is the trigger time of each analog signal (that is, the time when the trigger analog signal is generated and output). The test operation data is synchronized with the timing of the test vector, that is, the trigger time in the signal trigger data is synchronized with the trigger time of each signal in the test vector. The main control board synchronously triggers the digital test board and the matching test board through the test instruction; after receiving the test instruction, the matching test board determines the trigger time of each analog signal in the analog signal data according to the signal trigger data, and generates and outputs each analog signal to the chip to be tested at the corresponding trigger time. After receiving the test instruction, the digital test board synchronously executes the test vector to generate and output the test signal to the chip to be tested at different trigger times, so that the chip to be tested converts and outputs the analog signal output by the matching test board, and the digital test board also triggers and executes the sampling operation of the output signal of the chip to be tested according to the test vector, thereby realizing synchronous testing of the chip to be tested. For a matching test board (non-digital test board) that originally does not support test vectors, by creating a virtual trigger channel, signal trigger data and analog signal data can be run on the virtual trigger channel, so that the matching test board can realize analog signal triggering on the virtual trigger channel and output the corresponding analog signal to the chip under test, thereby achieving synchronization with the relevant test operations of the digital test board.

[0066] In other embodiments, the test operation data of the matching test board includes trigger time data (including multiple trigger times) for sampling the output signal of the chip to be tested. At this time, the matching test board is pre-set with a sampling operation step for sampling the output signal of the chip to be tested in response to the trigger time. Correspondingly, the test vector of the digital test board is used to instruct the digital test board to generate and output test signals to the chip to be tested at different trigger times, and the test operation data is synchronized with the timing of the test vector. The main control board synchronously triggers the digital test board and the matching test board through the test instruction; after receiving the test instruction, the digital test board runs the test vector to generate and output each test signal to the chip to be tested at different trigger times, so as to trigger the chip to be tested to convert and output the test signal. After receiving the test instruction, the matching test board synchronously executes the test operation data to trigger and execute the sampling operation of the output signal of the chip to be tested at the corresponding time, so as to realize synchronous testing of the chip to be tested.

[0067] In other embodiments, depending on the test task, the test operation data of the test board may also include analog signal data output by the test board to the chip to be tested, signal trigger data for triggering each analog signal in the analog signal data output by the test board, and trigger time for sampling the output signal of the chip to be tested. Correspondingly, the test operation of the digital test board indicated by the test vector of the digital test board is different, and the test operation data of the test board is the same as the timing of the test vector. The specific test process is referred to above and will not be repeated here.

[0068] In the present embodiment, the main control board and different types of test boards are connected through a backplane, so that the main control board can control different types of boards to perform tests by means of software instruction triggering, and because the test operation data is synchronized with the test vector, the digital test board and the matching test board can be synchronized when performing test operations according to their respective test data, thereby achieving the purpose of chip synchronization test. On the one hand, only one software instruction is required to trigger the digital test board and the matching test board, and the high-precision synchronization mechanism of the test vector in the digital test board can be used to synchronize the operations of other matching test boards, which not only improves the synchronization accuracy of different types of boards during chip testing, but also improves chip testing efficiency. On the other hand, by software synchronization triggering different types of test boards, the high-precision synchronization between different types of test boards can be achieved to run their own test data to perform test operations, without adding additional hardware circuits or private synchronization protocols, the synchronization test between different types of boards can be achieved on the traditional test machine architecture, reducing the test cost and improving the applicability of chip testing.

[0069] In one embodiment, if Figure 5 As shown, a chip testing method is provided, which is applied in Figure 4 The chip test in is taken as an example to illustrate, including the following steps:

[0070] S10: The main control board synchronously triggers the digital test board and the matching test board through the test instruction, so that the matching test board performs the test operation according to the test operation data, and the digital test board synchronously performs the test operation according to the test vector, so as to perform synchronous testing on the chip to be tested.

[0071] Among them, the main control board synchronously sends test instructions to the trigger digital test board and the cooperation test board. After receiving the test instructions, the cooperation test board performs test operations on the chip to be tested according to the test operation data. After receiving the test instructions, the digital test board synchronously performs test operations on the chip to be tested according to the test vector.

[0072] Specifically, before executing the test task of the chip to be tested through the chip testing equipment, it is necessary to generate the test vector of the digital test board and the test operation data of the matching test board in advance according to the test task, wherein the test operation data of the matching test board is synchronized with the timing of the test vector of the digital test board. Then, the test vector of the digital test board is downloaded and entered into the digital test board, and the test operation data of the matching test board is downloaded and entered into the matching test board, so that the digital test board stores the pre-generated test vector, and the matching test board stores the pre-generated test operation data. Among them, the test vector and the test operation data can be sent to the digital test board and the matching test board respectively through the main control card.

[0073] Among them, the test operation data of the matching test board may include the analog signal data output by the matching test board to the chip to be tested, and the signal trigger data for triggering each analog signal in the analog signal data output by the matching test board; the trigger timing of the signal trigger data is synchronized with the timing of the test vector of the digital test board. The main control board synchronously triggers the digital test board and the matching test board through the test instruction; after receiving the test instruction, the matching test board determines the trigger time of each analog signal in the analog signal data according to the signal trigger data, and outputs each analog signal to the chip to be tested at the corresponding trigger time. After receiving the test instruction, the digital test board synchronously executes the first test vector to generate and output the test signal at different trigger times, so that the chip to be tested converts and outputs the analog signal output by the matching test board, and the digital test board also triggers and executes the sampling operation of the output signal of the chip to be tested according to the test vector, thereby performing synchronous testing on the chip to be tested. The main control board synchronously triggers the digital test board and the matching test board through the test instruction to perform the test operation according to the test vector and the test operation data, so as to realize the synchronous testing of the chip to be tested. For the matching test board that originally does not support test vectors, by running signal trigger data and analog signal data, the trigger channel of the matching test board can be virtualized, so that the matching test board can realize analog signal triggering on the virtual trigger channel, and then output the corresponding analog signal to the chip under test, thereby achieving synchronization with the relevant operations of the digital test board.

[0074] Taking the ADC test of the chip to be tested as an example, the ADC test task includes a digital test board DIG and a mixed signal board MIX, that is, the mixed signal board MIX is a matching test board. Before executing the test task of the chip to be tested through the chip testing equipment, it is necessary to generate the test vector of the digital test board and the test operation data of the mixed signal board in advance according to the test task. Among them, the test operation data includes analog signal data and signal trigger data, the analog signal data includes multiple analog signals, and the signal trigger data includes the trigger time of each analog signal in the analog signal data; the trigger time in the signal trigger data is synchronized with the trigger time of each signal in the test vector. The test vector includes multiple vector rows arranged in time sequence, such as Figure 6 As shown in the figure, multiple vector rows are multiple lines of strings on the lower left side of the figure; each trigger information (trigger time) of the signal trigger data is as follows Figure 6 The 1 and 0 on the right side of the lower middle indicate that 1 triggers the high-precision voltage output, and 0 indicates no operation. Figure 6 As shown, each line of character string is sorted in time sequence, and each trigger information of the signal trigger data corresponds to each line of character string (each vector line) one by one, so that the signal trigger time of the matching test board and the digital test board can be synchronized, that is, the trigger time of the signal trigger data is synchronized with the test operation of the test vector of the digital test board. When the test task of the chip to be tested is performed by the chip testing equipment, the test vector of the digital test board is downloaded and entered into the digital test board, and the test operation data of the mixed signal board is downloaded and entered into the mixed signal board, so that the digital test board stores the pre-generated test vectors, and the mixed signal board stores the pre-generated test operation data. Then, the main control board synchronously triggers the digital test board and the matching test board through the test instructions, such as Figure 6 As shown, after receiving the test instruction, the processor FPGA (Field-Programmable Gate Array) of the mixed signal board MIX will determine the trigger time of each analog signal in the analog signal data according to the signal trigger data, and trigger its own digital-to-analog converter DAC (Digital-to-Analog Converter) to generate an analog signal (such as the voltage signal of the voltage reference source) at the corresponding trigger time, and output the voltage signal to the chip to be tested through the peripheral circuit. After receiving the test instruction, the digital test board performs file parsing (symbol parsing) on ​​the test vector, and then synthesizes the corresponding digital waveform according to the predetermined conversion timing and parsing data, and outputs the digital waveform to the chip to be tested through the PE bus to trigger the ADC conversion of the chip to be tested to cooperate with the analog signal conversion and output of the test board. The digital test board will also trigger and perform the sampling operation of the output signal of the chip to be tested according to the test vector to capture the signal output by the ADC of the chip to be tested. Since the trigger timing of each analog signal of the mixed signal board MIX is synchronized with the timing of the test vector of the digital test board, when the two synchronously trigger and execute the corresponding data, the synchronous test of the chip to be tested can be realized.

[0075] Taking the above-mentioned ADC test as an example, the test operation data is executed on the mixed signal board MIX. When the trigger information in the signal trigger data is read as 1, it indicates that a high-precision voltage signal (voltage sampling point) is triggered to output. At the same time, the test vector is executed in conjunction with the digital test board to capture the ADC conversion code at the corresponding time point. In this way, the ADC index test can be completed quickly. Generally speaking, a voltage sampling point test takes a few microseconds (us), while in the traditional software trigger method, each voltage sampling point sampling takes at least a dozen milliseconds (ms), which greatly increases the test speed.

[0076] In other embodiments, the test operation data of the matching test board includes trigger time data (including multiple trigger times) for sampling the output signal of the chip to be tested. At this time, the matching test board is pre-set with a sampling operation step for sampling the output signal of the chip to be tested in response to the trigger time. Correspondingly, the test vector of the digital test board is used to instruct the digital test board to generate and output test signals to the chip to be tested at different trigger times, and the test operation data is synchronized with the timing of the test vector. The main control board synchronously triggers the digital test board and the matching test board through the test instruction; after receiving the test instruction, the digital test board runs the test vector to generate and output each test signal to the chip to be tested at different trigger times, so as to trigger the chip to be tested to convert and output the test signal. After receiving the test instruction, the matching test board synchronously executes the test operation data to trigger and execute the sampling operation of the output signal of the chip to be tested at the corresponding time, so as to realize synchronous testing of the chip to be tested.

[0077] Taking the DAC test of the chip to be tested as an example, the DAC test task of the chip to be tested includes a digital test board DIG and a mixed signal board MIX, that is, the mixed signal board MIX serves as a matching test board. Before executing the test task of the chip to be tested through the chip testing equipment, it is necessary to generate the test vector of the digital test board and the test operation data of the mixed signal board in advance according to the test task. Among them, the test operation data includes the trigger time of the mixed signal board MIX to perform a sampling operation on the output signal of the chip to be tested; the test operation data is synchronized with the trigger time of each signal in the test vector. For example, the test vector includes multiple vector rows arranged in time sequence, and the trigger time in the test operation data can be represented by multiple trigger information arranged in time sequence; participate in Figure 6The vector rows and trigger information in the test operation data correspond to each vector row of the test vector one by one, so that the trigger time of the cooperation test board and the digital test board can be synchronized, that is, the trigger time of the test operation data and the test operation of the test vector of the digital test board can be synchronized. The main control board synchronously triggers the digital test board and the cooperation test board through the test instruction. After receiving the test instruction, the digital test board performs file parsing (symbol parsing) on ​​the test vector, and then synthesizes the corresponding digital waveform according to the predetermined conversion timing and parsing data, and outputs the digital waveform to the chip to be tested through the PE bus, so that the DAC of the chip to be tested converts and outputs the digital waveform; and after receiving the test instruction, the processor FPGA of the mixed signal board MIX triggers and executes the acquisition operation of the output signal of the chip to be tested at the corresponding time point according to the trigger time of the test operation data, so as to capture the signal output by the DAC of the chip to be tested. Since the trigger time of the mixed signal board MIX is synchronized with the signal trigger time of the test vector of the digital test board, when the two synchronously trigger and execute the corresponding data, the synchronous test of the chip to be tested can be realized.

[0078] In the present embodiment, the main control board and different types of test boards are connected through a backplane, so that the main control board can control different types of boards to perform tests by means of software instruction triggering, and because the test operation data is synchronized with the test vector, the digital test board and the matching test board can be synchronized when performing test operations according to their respective test data, thereby achieving the purpose of chip synchronization test. On the one hand, only one software instruction is required to trigger the digital test board and the matching test board, and the high-precision synchronization mechanism of the test vector in the digital test board can be used to synchronize the operations of other matching test boards, which not only improves the synchronization accuracy of different types of boards during chip testing, but also improves chip testing efficiency. On the other hand, by software synchronization triggering different types of test boards, the high-precision synchronization between different types of test boards can be achieved to run their own test data to perform test operations, without adding additional hardware circuits or private synchronization protocols, the synchronization test between different types of boards can be achieved on the traditional test machine architecture, reducing the test cost and improving the applicability of chip testing.

[0079] In one embodiment, the chip testing device includes a data generating device, which is used to generate test operation data synchronized with the timing of the test vector according to the test task and the test vector of the digital test board. The test operation data includes analog signal data of the chip to be tested and signal trigger data that triggers the output of the analog signal. The test operation data of the test board is obtained by:

[0080] S01: The data generating device determines the analog signal data of the matching test board for the chip to be tested according to the test task, and determines the corresponding relationship between the signal triggering time of the digital test board and the matching test board to obtain the triggering time corresponding relationship.

[0081] S02: The data generating device generates signal trigger data for the test board that is synchronized with the test vector timing according to the corresponding relationship between the test vector and the trigger time.

[0082] The data generation device determines the analog signal data of the chip to be tested (such as the voltage signal data of the mixed signal board MIX) of the matching test board according to the test task, and determines the corresponding relationship between the signal trigger time of the digital test board and the signal trigger time of the matching test board to obtain the trigger time corresponding relationship. The data generation device generates the signal trigger data of the matching test board synchronized with the test vector timing according to the corresponding relationship between the test vector and the trigger time.

[0083] In this embodiment, the data generating device determines the analog signal data of the matching test board for the chip to be tested according to the test task, determines the corresponding relationship between the operation trigger time of the digital test board and the signal trigger time of the matching test board, obtains the trigger time corresponding relationship, and then generates the signal trigger data of the matching test board synchronized with the test vector timing according to the test vector and the trigger time corresponding relationship. It can ensure that the timing of the signal trigger data is synchronized with the test vector, thereby utilizing the high-precision synchronization mechanism of the test vector to ensure the subsequent synchronous testing of other test boards and the digital test board, thereby achieving test synchronization of all test boards.

[0084] In one embodiment, step S02, that is, generating signal trigger data of a matching test board synchronized with the test vector timing according to the corresponding relationship between the test vector and the trigger time, specifically includes the following steps:

[0085] S021: The data generating device reads the test vector of the digital test board to obtain a plurality of test vector rows arranged in time sequence in the test vector.

[0086] The data generating device reads the test vector of the digital test board and obtains a plurality of test vector rows arranged in time sequence in the test vector, wherein the test vector row is used to indicate the test operation of the digital test board on the chip to be tested at the current time point, and the test operation includes the output test signal, the trigger time of the test signal and other information.

[0087] S022: The data generating device generates trigger information for triggering the test board to output an analog signal according to each test vector row, obtains a plurality of trigger information arranged in time sequence, and outputs the obtained signal trigger data.

[0088] Then, according to each test vector row, trigger information for triggering the test board to output an analog signal is generated accordingly, multiple trigger information arranged in time sequence are obtained, and signal trigger data is output.

[0089] It is important to understand that the trigger information in the signal trigger data and its corresponding time information (time point) are combined to represent the trigger time of the analog signal of the test board. At the corresponding time point of the test vector row, the trigger information (such as trigger or not trigger) of the analog signal output by the test board is generated, ensuring that the trigger time of the analog signal is synchronized with the time point of the corresponding test vector row, ensuring the timing synchronization of the signal trigger data and the test vector, so that the subsequent analog signal input operation of the test board is synchronized with the test operation of the digital test board on the chip to be tested.

[0090] In this embodiment, the data generating device reads the test vector of the digital test board and obtains a plurality of test vector rows arranged in time sequence in the test vector, the test vector rows are used to indicate the test operation of the digital test board on the chip to be tested at the current time point, and according to each test vector row, generates corresponding trigger information for triggering the test board to output an analog signal, obtains a plurality of trigger information arranged in time sequence, and outputs the obtained signal trigger data, thereby improving the timing synchronization between the signal trigger data and the test vector, and ensuring that the subsequent analog signal input operation of the test board is synchronized with the test operation of the digital test board on the chip to be tested.

[0091] In one embodiment, the trigger information in the signal trigger data is represented by a trigger flag, that is, the trigger time in the signal trigger data is represented by a trigger flag at a corresponding time point. In step S022, that is, according to each test vector row, trigger information for triggering the test board to output an analog signal is generated, a plurality of trigger information arranged in time sequence is obtained, and the signal trigger data is output, which specifically includes the following steps:

[0092] SA0221: When it is determined that the cooperation test board needs to output an analog signal at a time point of the test vector row, the data generating device generates a trigger flag of the analog signal at a corresponding position of the test vector row to obtain multiple trigger information;

[0093] SA0222: When it is determined that the cooperation test board does not need to output an analog signal at a time point of the test vector row, the data generating device generates a preset value at a corresponding position of the test vector row to obtain a plurality of preset values, and the preset value is different from the trigger flag bit;

[0094] SA0223: The data generating device outputs multiple trigger information and preset values ​​to obtain signal trigger data according to the timing information of the test vector.

[0095] like Figure 7As shown, the character string on the left side of the figure, from top to bottom, represents multiple test vector rows arranged in time sequence in the test vector of the digital test board. The digital test board triggers and performs test operations in sequence according to the test vector rows in the figure. When it is determined that the matching test board needs to output an analog signal at the time point corresponding to the test vector row, the data generating device generates a trigger flag bit of the analog signal at the corresponding position of the test vector row (such as Figure 7 The number 1 on the right can indicate triggering a high-precision voltage output) to obtain multiple trigger information; when it is determined that the matching test board does not need to output an analog signal at the time point corresponding to the test vector row, the data generating device generates a preset value (such as Figure 7 The number 0 on the right side) obtains multiple preset values. The preset value is different from the trigger flag. Finally, the data generating device outputs multiple trigger information and preset values ​​according to the timing information of the test vector to obtain signal trigger data, that is, in the signal trigger data, multiple trigger information and preset values ​​are arranged according to the timing information of the test vector. The trigger information is represented by the trigger flag, which is convenient for subsequent test operation triggering, which is simple and convenient.

[0096] In other embodiments, when it is determined that the test board does not need to output an analog signal at the time point of the test vector row, the data generating device sets a null value (i.e., no number is set) at the corresponding position of the test vector row, and arranges and outputs multiple trigger information according to the timing information of the test vector to obtain signal trigger data, thereby reducing the amount of signal trigger data.

[0097] In this embodiment, when it is determined that the test board needs to output an analog signal at the time point of the test vector row, a trigger flag of the analog signal is generated at the corresponding position of the test vector row to obtain multiple trigger information; when it is determined that the test board does not need to output an analog signal at the time point of the test vector row, a preset value is generated at the corresponding position of the test vector row to obtain multiple preset values, and the preset value is different from the trigger flag; according to the timing information of the test vector, multiple trigger information and preset values ​​are arranged and output to obtain signal trigger data. Using trigger flags arranged in time sequence to represent signal trigger data is convenient for subsequent test operation triggering, which is simple and convenient.

[0098] In one embodiment, the trigger information is represented by microinstructions, that is, the trigger time in the signal trigger data is represented by the microinstructions at the corresponding time point. In step S022, according to each test vector row, trigger information for triggering the test board to output an analog signal is generated, a plurality of trigger information arranged in time sequence is obtained, and the signal trigger data is output, which specifically includes the following steps:

[0099] SB0221: When it is determined that the matching test board needs to output an analog signal at a time point of the test vector row, the data generating device generates a microinstruction for triggering the analog signal at a corresponding position of the test vector row to obtain a plurality of trigger information;

[0100] SB0222: When it is determined that the matching test board does not need to output an analog signal at a time point of the test vector row, the data generating device sets a null value at a corresponding position of the test vector row;

[0101] SB0223: The data generating device outputs a plurality of trigger information according to the timing information of the test vector to obtain signal trigger data.

[0102] like Figure 8 As shown, the character string on the left side of the figure, from top to bottom, represents multiple test vector rows arranged in time sequence in the test vector of the digital test board. The test vector rows in the digital test board installation diagram trigger and execute test operations in sequence. When it is determined that the matching test board needs to output an analog signal at the time point corresponding to the test vector row, the data generation device generates a microinstruction (such as ) that triggers the analog signal at the corresponding position of the test vector row. Figure 8 The TRIG microinstruction on the right can indicate triggering a high-precision voltage output) and obtain multiple trigger information; when it is determined that the test board does not need to output an analog signal at the time point corresponding to the test vector row, a null value is set at the corresponding position of the test vector row, that is, the corresponding position of the test vector row is empty. Finally, the data generation device outputs multiple trigger information to obtain signal trigger data according to the timing information of the test vector. Representing the trigger information in the form of microinstructions is simple and convenient for subsequent test operation triggering.

[0103] In other embodiments, when it is determined that the matching test board does not need to output an analog signal at the time point corresponding to the test vector row, a preset value (such as 0) is generated at the corresponding position of the test vector row to obtain multiple preset values. Finally, the data generation device outputs multiple trigger information according to the timing information of the test vector to obtain signal trigger data.

[0104] In this embodiment, when it is determined that the cooperation test board needs to output an analog signal at the time point of the test vector row, a microinstruction for triggering the analog signal is generated at the corresponding position of the test vector row to obtain multiple trigger information; when it is determined that the cooperation test board does not need to output an analog signal at the time point of the test vector row, a null value is set at the corresponding position of the test vector row; multiple trigger information is output according to the timing information of the test vector to obtain signal trigger data. Using microinstructions arranged in time sequence to represent signal trigger data facilitates subsequent test operation triggering and execution according to the microinstructions, which is simple and convenient.

[0105] In other embodiments, the test operation data includes trigger time data (including multiple trigger times) for sampling the output signal of the chip to be tested, and the test operation data of the test board is obtained in the following manner: the data generating device determines the corresponding relationship between the signal trigger time of the digital test board and the trigger time of the sampling operation of the test board according to the test task, and obtains the trigger time corresponding relationship; according to the test vector and the trigger time corresponding relationship, the trigger time data of the sampling operation synchronized with the test vector timing is generated. It can ensure that the operation trigger timing of the test operation data is synchronized with the signal trigger timing of the test vector, so as to utilize the high-precision synchronization mechanism of the test vector to ensure the subsequent synchronization test of other test boards and the digital test board, thereby realizing the test synchronization of all test boards.

[0106] Among them, the specific process of obtaining the trigger time data is as follows: the data generating device reads the test vector of the digital test board to obtain a plurality of test vector rows arranged in time sequence in the test vector; according to each test vector row, a corresponding trigger information is generated to trigger the sampling operation of the cooperation test board, and a plurality of trigger information arranged in time sequence is obtained, and the trigger time data is output, which improves the timing synchronization between the trigger time data and the test vector, and ensures that the subsequent sampling operation of the cooperation test board on the chip to be tested is synchronized with the test operation of the digital test board on the chip to be tested.

[0107] Specifically, the trigger time data (i.e., the test operation data) can be generated in the following manner: when it is determined that the test board needs to sample the output signal of the chip to be tested at the time point of the test vector row, the data generating device generates a trigger flag (such as 1) of the sampling operation at the corresponding position of the test vector row, and obtains multiple trigger information; when it is determined that the test board does not need to sample the output signal of the chip to be tested at the time point of the test vector row, the data generating device generates a calibration value (or null value) at the corresponding position of the test vector row, and obtains multiple calibration values ​​(such as 0), and the calibration value is different from the trigger flag; finally, the data generating device outputs multiple trigger information and calibration values ​​according to the timing information of the test vector to obtain the trigger time data. The use of trigger flags arranged in time sequence to represent the trigger time data is convenient for subsequent test operation triggering, which is simple and convenient.

[0108] In other embodiments, the trigger time data (i.e., test operation data) can also be generated in the following manner: when it is determined that the test board needs to sample the output signal of the chip to be tested at the time point of the test vector row, the data generation device generates a microinstruction for the sampling operation at the corresponding position of the test vector row to obtain multiple trigger information; when it is determined that the test board does not need to sample the output signal of the chip to be tested at the time point of the test vector row, the data generation device sets a null value at the corresponding position of the test vector row; finally, the data generation device outputs multiple trigger information according to the timing information of the test vector to obtain signal trigger data. Using microinstructions arranged in time sequence to represent signal trigger data facilitates subsequent test operation triggering and execution according to the microinstructions, which is simple and convenient.

[0109] In one embodiment, Fig. 9 As shown, in step S10, the main control board synchronously triggers the digital test board and the matching test board through the test instruction, so that the matching test board performs the test operation according to the test operation data, and the digital test board synchronously performs the test operation according to the test vector, so as to perform synchronous testing on the chip to be tested, which specifically includes the following steps:

[0110] S11: The main control board sends a test instruction to the digital test board and the matching test board, so that the digital test board and the matching test board respond to the test instruction to wait for a trigger pulse signal;

[0111] S12: The main control board synchronously sends a trigger pulse signal, so that the cooperative test board performs a test operation according to the test operation data after receiving the trigger pulse signal, and the digital test board performs a test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform synchronous testing on the chip to be tested.

[0112] Among them, the main control board, the digital test board and the matching test board are connected through a serial bus. The digital test board and the matching test board may not be synchronized in receiving the test instructions. In order to increase the trigger synchronization accuracy of the digital test board and the matching test board, a pulse signal can be used to trigger the digital test board and the matching test board to execute the corresponding test operations.

[0113] Specifically, the main control board sends a test instruction to the digital test board and the matching test board. The test instruction is used to instruct the digital test board and the matching test board to wait for the trigger pulse signal of the main control board. The trigger pulse signal is a pulse signal used to synchronously trigger the digital test board and the matching test board to perform a test operation. After receiving the test instruction, the digital test board and the matching test board wait for the trigger pulse signal of the main control board respectively and prepare for the test (such as setting it to a test state). After the main control board sends the preset duration of the test instruction, the main control board synchronously sends a trigger pulse signal to the digital test board and the matching test board. After receiving the trigger pulse signal, the test board performs a test operation according to the test operation data to complete the test operation of the chip to be tested; after synchronously receiving the trigger pulse signal, the digital test board performs a test operation according to the test vector to complete the synchronous test of the chip to be tested.

[0114] In this embodiment, the main control board sends a test instruction so that the digital test board and the matching test board respond to the test instruction to wait for the trigger pulse signal, and then the main control board sends a trigger pulse signal synchronously so that the matching test board performs a test operation according to the test operation data after receiving the trigger pulse signal, and the digital test board performs a test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform a synchronous test on the chip to be tested. The test board is triggered by the trigger pulse signal, which improves the trigger progress of the digital test board and the matching test board, facilitates the subsequent synchronous execution of the test vector and the test operation data, and further improves the synchronization accuracy of different types of boards during chip testing.

[0115] In one embodiment, step S12, that is, the cooperation test board performs the test operation according to the test operation data after receiving the trigger pulse signal, and the digital test board performs the test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform synchronous testing on the chip to be tested, specifically includes the following steps:

[0116] S121: After receiving the trigger pulse signal, the cooperation test board performs delay adjustment according to the first delay time, and performs the test operation according to the test operation data after the delay adjustment, triggers and outputs the analog signal to the chip to be tested, and / or triggers the sampling operation of the output signal of the chip to be tested.

[0117] It should be understood that due to the different signal links of different test boards, the signal link delays of different types of test boards are different, which ultimately leads to time deviations in the output signals of different types of test boards. Fig.10As shown in the figure, the upper part represents the waveform signal output by the digital test board, and the solid black dots below represent the voltage signal output by the mixed signal board MIX. Even if the digital test board and the mixed signal board are triggered synchronously, there is a deviation in the output time of the two types of signals due to the different signal links of the digital test board and the mixed signal board. Therefore, it is necessary to perform delay compensation calibration on different test boards to ensure that the matching test board and the digital test board can output signals synchronously.

[0118] After the main control board sends the test instructions to the digital test board and the matching test board, the main control board will also obtain the first delay time of the matching test board and the second delay time of the digital test board, and send the first delay time to the matching test board and the second delay time to the digital test board. The first delay time and the second delay time are determined in advance according to the output delay time of the digital test board and the matching test board signals, and are used to perform delay calibration on the signals output by the matching test board and the digital test board, respectively, to ensure that the matching test board and the digital test board can output signals synchronously.

[0119] S122: After receiving the trigger pulse signal, the digital test board adjusts the delay according to the second delay time, and executes the test operation according to the test vector after the delay adjustment, generates and synchronously outputs the test signal to the chip to be tested, and / or triggers the sampling operation of the output signal of the chip to be tested, thereby realizing synchronous testing of the chip to be tested.

[0120] After receiving the trigger pulse signal, the cooperative test board adjusts the delay according to the first delay time, and performs the test operation according to the test operation data after the delay adjustment, so as to trigger and output the analog signal to the chip under test, and / or trigger the sampling operation of the output signal of the chip under test. After receiving the trigger pulse signal, the digital test board adjusts the delay according to the second delay time, and performs the test operation according to the test vector after the delay adjustment, so as to generate and synchronously output the test signal to the chip under test, and / or trigger the sampling operation of the output signal of the chip under test, so as to realize the synchronous test of the chip under test.

[0121] Among them, the test operation data includes analog signal data and signal trigger data, and the signal trigger data is synchronized with the timing of the test vector. Specifically, after the first delay time is delayed, the cooperation test board determines the trigger time of each analog signal in the analog signal data according to the signal trigger data, and the cooperation test board triggers and outputs the corresponding analog signal to the chip to be tested at the trigger time of each analog signal. This process clarifies that the cooperation test board performs the test operation according to the test operation data, and by splitting the test operation data into analog signal data and signal trigger data, and then triggering and outputting the signal, the cooperation test board can trigger and output the analog signal through the virtual trigger channel, realize the test vector execution function with the digital test board, and ensure the synchronization of the signal output of the cooperation test board and the digital test board. After the digital test board receives the trigger pulse signal, the digital test board parses each test vector row in the test vector to obtain the test execution data of the digital test board. The test execution data includes multiple test operation information (such as microinstructions) arranged in a time sequence. After delaying for a second delay time, the digital test board performs waveform synthesis on each test operation information according to a preset timing signal, generates a test signal and synchronously outputs the test signal, so that the chip under test can convert and output the analog signal output by the test board. The digital test board will also trigger and execute a sampling operation on the output signal of the chip under test according to the test vector, thereby realizing synchronous testing of the chip under test.

[0122] Take ADC test as an example, the test board is a mixed signal board MIX. Fig.11 As shown, after receiving the trigger pulse signal, the FPGA of the mixed signal board MIX first performs a delay adjustment according to the first delay time, and then performs a test operation according to the test operation data after the delay adjustment. Specifically, the FPGA first delays the first delay time, and then the FPGA determines the trigger time of each analog signal in the analog signal data according to the signal trigger data, and then triggers the DAC to generate a corresponding analog signal at the trigger time of each analog signal, and outputs the corresponding analog signal (voltage signal of the voltage reference source) to the chip under test through the peripheral circuit. At the same time, Fig. 9 As shown, after receiving the trigger pulse signal, the digital test board DIG needs to perform delay adjustment after parsing the test vector (symbol file), that is, after delaying for the second delay time, the waveform of the vector in the test vector is synthesized according to the preset timing, and then the synthesized digital waveform is output to the chip under test through PE to trigger the ADC conversion of the chip under test and cooperate with the analog signal conversion and output of the test board; the digital test board will also trigger and execute the sampling operation of the output signal of the chip under test according to the test vector to capture the signal output by the ADC of the chip under test, thereby cooperating with the mixed signal board MIX to realize the ADC test of the chip under test.

[0123] In other embodiments, the test operation data of the test board includes trigger time data for sampling the output signal of the chip to be tested, and the test operation data is synchronized with the timing of the test vector. After delaying the second delay time, the digital test board runs the test vector to generate and output each test signal to the chip to be tested at different trigger times to trigger the chip to be tested to convert and output the test signal. After delaying the first delay time, the test board synchronously executes the test operation data to trigger and perform the sampling operation of the output signal of the chip to be tested at the corresponding time to achieve synchronous testing of the chip to be tested.

[0124] Taking the DAC test of the chip to be tested as an example, the DAC test task of the chip to be tested includes a digital test board DIG and a mixed signal board MIX, that is, the mixed signal board MIX is a matching test board. After the second delay time, the digital test board performs file parsing (symbol parsing) on ​​the test vector, and then synthesizes the corresponding digital waveform according to the predetermined conversion timing and parsing data, and outputs the digital waveform to the chip to be tested through the PE bus, so that the DAC of the chip to be tested converts and outputs the digital waveform; and after the first delay time, the processor FPGA of the mixed signal board MIX will trigger and execute the acquisition operation of the output signal of the chip to be tested at the corresponding time point according to the trigger time of the test operation data, so as to capture the signal output by the DAC of the chip to be tested. Since the trigger time of the mixed signal board MIX is synchronized with the signal trigger time of the test vector of the digital test board, when the two are synchronously triggered to execute the corresponding data, the synchronous test of the chip to be tested can be realized.

[0125] In another embodiment, the test operation data of the test board also includes analog signal data and signal trigger data, as well as trigger time data for sampling the output signal of the chip to be tested; the test operation data is synchronized with the timing of the test vector. After the second delay time is delayed, the digital test board runs the test vector to generate and output each test signal to the chip to be tested at different trigger times; after the first delay time is delayed, the test board determines the trigger time of each analog signal in the analog signal data according to the signal trigger data, and the test board triggers and outputs the corresponding analog signal to the chip to be tested at the trigger time of each analog signal to trigger the chip to be tested to perform signal conversion and output; after that, the test board is triggered and executed at the corresponding time according to the test operation data to perform a sampling operation on the output signal of the chip to be tested, so as to realize synchronous testing of the chip to be tested. Since the trigger time of the mixed signal board MIX is synchronized with the signal trigger time of the test vector of the digital test board, when the two synchronously trigger and execute the corresponding data, synchronous testing of the chip to be tested can be realized.

[0126] In this embodiment, after receiving the trigger pulse signal, the cooperative test board performs delay adjustment according to the first delay time, and performs the test operation according to the test operation data after the delay adjustment, triggers and outputs the analog signal to the chip to be tested, and / or triggers the sampling operation of the output signal of the chip to be tested; after receiving the trigger pulse signal, the digital test board performs delay adjustment according to the second delay time, and performs the test operation according to the test vector after the delay adjustment, generates and synchronously outputs the test signal to the chip to be tested, and / or triggers the sampling operation of the output signal of the chip to be tested, so as to realize the synchronous test of the chip to be tested. The cooperative test board and the digital test board respectively perform the delay calibration of the output signal according to the first delay time and the second delay time, ensuring that the cooperative test board and the digital test board can output the signal synchronously, solving the signal output deviation caused by the different signal link delays, so that the output signals of different types of test boards can be synchronously output to the chip to be tested, further improving the synchronization accuracy of different types of boards during chip testing.

[0127] In one embodiment, the chip testing device further includes a calibration board, and the digital test board and the matching test board are respectively connected to the calibration board. The calibration board is used to calibrate the signal delay output by the digital test board and the matching test board to obtain the first delay time and the second delay time. Specifically, the first delay time and the second delay time are calibrated in the following manner:

[0128] S001: The main control board synchronously triggers the digital test board and the matching test board, so that the digital test board and the matching test board output signals to the calibration board respectively, and controls the calibration board to receive the signal and record the receiving time.

[0129] Wherein, before the chip test is performed, the output end of the digital test board and the output end of the matching test board are respectively connected to the calibration board. After the main control board detects that the digital test board and the matching test board are respectively connected to the calibration board, the main control board synchronously triggers the digital test board and the matching test board through a pulse signal, so that the digital test board and the matching test board output signals to the calibration board respectively. The receiving module of the calibration board receives the signal output by the matching test board and records the receiving time to obtain the first receiving time; the receiving module of the calibration board receives the signal output by the digital test board and records the receiving time to obtain the second receiving time, and feeds back the first delay time and the second delay time to the main control board. That is, the first receiving time is the time when the calibration board receives the output signal of the matching test board, and the second receiving time is the time when the calibration board receives the output signal of the digital test board.

[0130] S002: The main control board receives the first receiving time and the second receiving time fed back by the calibration board, and calibrates the first delay time and the second delay time according to the first receiving time and the second receiving time.

[0131] The main control board receives the first receiving time and the second receiving time fed back by the calibration board, and calibrates the first delay time and the second delay time according to the first receiving time and the second receiving time. For example, the first receiving time is directly used as the delay time of the digital test board to obtain the second delay time, and the first receiving time is directly used as the delay time of the matching test board to obtain the first delay time, so that the subsequent matching test board and the digital test board output signal are both the first receiving time + the second receiving time, ensuring two synchronous outputs, which is simple and convenient. In other embodiments, the time error between the first receiving time and the second receiving time can be determined, and the digital test board and the matching test board are compensated according to the time error to obtain the first delay time and the second delay time.

[0132] In this embodiment, the main control board synchronously triggers the digital test board and the matching test board, so that the digital test board and the matching test board output signals to the calibration board respectively, and controls the calibration board to receive signals and record the receiving time, receives the first receiving time and the second receiving time fed back by the calibration board, and calibrates the first delay time and the second delay time according to the first receiving time and the second receiving time. The signal output time of the digital test board and the matching test board is determined by the same receiving module of the calibration board, so as to calibrate the first delay time and the second delay time, which provides an accurate data basis for delay compensation of different test boards in subsequent tests.

[0133] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0134] The present application also provides an electronic device, which may be a main control board, a digital test board and a matching test board, such as Fig.12 As shown, the electronic device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program, or implements the functions of the modules / units in the above-mentioned device embodiments when executing the computer program.

[0135] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present application. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program in the electronic device.

[0136] Those skilled in the art will understand that Fig.12These are merely examples of the electronic device and do not constitute a limitation of the electronic device. The electronic device may include more or fewer components than those shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0137] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0138] The memory may be an internal storage unit of the electronic device, such as a hard disk or memory of the electronic device. The memory may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Furthermore, the memory may also include both an internal storage unit of the electronic device and an external storage device.

[0139] An embodiment of the present application further provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0140] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0141] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0142] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0143] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0144] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0145] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0146] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A chip testing method, characterized in that: Applied in a chip testing device, the chip testing device comprises a main control board, a digital test board and a matching test board interconnected through a backplane, the digital test board and the matching test board are test boards of different types; the digital test board stores pre-generated test vectors, the matching test board stores pre-generated test operation data, and the test operation data is synchronized with the timing of the test vectors; The method comprises: The main control board synchronously triggers the digital test board and the matching test board through test instructions, so that the matching test board performs test operations according to the test operation data, and the digital test board synchronously performs test operations according to the test vector, so as to perform synchronous testing on the chip to be tested.

2. The chip testing method according to claim 1, characterized in that: The main control board synchronously triggers the digital test board and the matching test board through a test instruction, so that the matching test board performs a test operation according to the test operation data, and the digital test board synchronously performs a test operation according to the test vector, so as to perform a synchronous test on the chip to be tested, including: The main control board sends the test instruction so that the digital test board and the matching test board respond to the test instruction to wait for a trigger pulse signal, wherein the trigger pulse signal is used to synchronously trigger the digital test board and the matching test board to perform a test operation; The main control board synchronously sends the trigger pulse signal so that the cooperative test board performs a test operation according to the test operation data after receiving the trigger pulse signal, and the digital test board performs a test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform synchronous testing on the chip to be tested.

3. The chip testing method according to claim 2, characterized in that: The cooperative test board performs a test operation according to the test operation data after receiving the trigger pulse signal, and enables the digital test board to perform a test operation according to the test vector after synchronously receiving the trigger pulse signal, so as to perform synchronous testing on the chip to be tested, including: After receiving the trigger pulse signal, the matching test board performs delay adjustment according to the first delay time, and performs a test operation according to the test operation data after the delay adjustment, so as to trigger and output an analog signal to the chip under test, and / or trigger a sampling operation of an output signal of the chip under test; After receiving the trigger pulse signal, the digital test board performs delay adjustment according to the second delay time, and performs a test operation according to the test vector after the delay adjustment, so as to generate and synchronously output a test signal to the chip under test, and / or trigger a sampling operation on the output signal of the chip under test, so as to realize synchronous testing of the chip under test; The first delay time and the second delay time are respectively used to perform delay calibration on the signals output by the matching test board and the digital test board, so as to ensure that the matching test board and the digital test board can output signals synchronously.

4. The chip testing method according to claim 3, characterized in that: The test operation data includes analog signal data and signal trigger data, the signal trigger data is synchronized with the timing of the test vector, the delay adjustment is performed according to the first delay time, and the test operation is performed according to the test operation data after the delay adjustment to trigger and output the analog signal to the chip under test, including: The matching test board determines the trigger time of each analog signal in the analog signal data according to the signal trigger data after delaying the first delay time; The matching test board triggers and outputs the corresponding analog signal to the chip under test at the triggering time of each analog signal.

5. The chip testing method according to claim 3, characterized in that: The chip testing device further includes a calibration board, the digital test board and the matching test board are respectively connected to the calibration board, and the first delay time and the second delay time are calibrated in the following manner: The main control board synchronously triggers the digital test board and the matching test board, so that the digital test board and the matching test board respectively output signals to the calibration board, control the calibration board to receive signals and record the receiving time; The main control board receives the first receiving time and the second receiving time fed back by the calibration board, and calibrates the first delay time and the second delay time according to the first receiving time and the second receiving time; The first receiving time is the time when the calibration board receives the output signal of the matching test board, and the second receiving time is the time when the calibration board receives the output signal of the digital test board.

6. The chip testing method according to any one of claims 1 to 5, characterized in that: The chip testing device includes a data generating device, the test operation data includes analog signal data and signal trigger data that triggers analog signal output, and the test operation data of the matching test board is obtained in the following manner: The data generating device determines the analog signal data output by the matching test board to the chip under test according to the test task, and determines the corresponding relationship between the signal triggering time of the digital test board and the matching test board to obtain the triggering time corresponding relationship; The data generating device generates the signal trigger data synchronized with the test vector timing according to the corresponding relationship between the test vector and the trigger time.

7. A chip testing device, characterized in that: It comprises a main control board, a digital test board and a matching test board which are interconnected through a backplane, wherein the digital test board and the matching test board are test boards of different types; the digital test board stores pre-generated test vectors, and the matching test board stores pre-generated test operation data, and the test operation data is synchronized with the timing of the test vectors; The main control board synchronously triggers the digital test board and the matching test board through test instructions, so that the matching test board performs test operations according to the test operation data, and the digital test board synchronously performs test operations according to the test vector, so as to perform synchronous testing on the chip to be tested.

8. A chip testing system, characterized in that: The invention comprises a chip to be tested and a chip testing device, wherein the chip testing device comprises a main control board, a digital test board and a matching test board interconnected through a backplane, wherein the digital test board and the matching test board are test boards of different types; the digital test board stores pre-generated test vectors, and the matching test board stores pre-generated test operation data, wherein the test operation data is synchronized with the timing of the test vectors; The main control board synchronously triggers the digital test board and the matching test board through test instructions, so that the matching test board performs test operations according to the test operation data, and the digital test board synchronously performs test operations according to the test vector, so as to perform synchronous testing on the chip to be tested.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the chip testing method according to any one of claims 1 to 6 are implemented.

10. A readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the chip testing method according to any one of claims 1 to 6 are implemented.

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