Echo segmented pulse compression method under high sampling rate based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an echo segmented pulse compression method under a high sampling rate based on an FPGA (Field Programmable Gate Array). According to the method, down-sampling preprocessing is firstly carried out on the signals sampled by the ADC with the sampling rate of 124 MHz, the sampling rate is reduced to 62 MHz on the premise that spectrum aliasing does not happen to the signals, then segmentation range pulse compression is carried out on the 1PRT echo signals, the total processing amount is reduced by 40%, the data calculation amount can be remarkably reduced, the operation speed and the data processing efficiency can be improved, and the method is suitable for large-scale popularization and application. And FPGA logic resources are saved. And short-time 1s echo pulse compression preprocessing is realized by adopting a method of synthesizing 1000 PRTs, so that the communication data rate is greatly reduced. And in cooperation with operation of other components of the surface scene deformation monitoring system, the system reliability is improved, and the scene deformation monitoring task can be smoothly carried out.

Description

Technical Field

[0001] The invention relates to the technical field of radar and satellite navigation, and in particular to an echo segmented pulse compression method at a high sampling rate based on FPGA. Background Art

[0002] The three-dimensional deformation monitoring technology of surface scenes based on Beidou signals is an important means of monitoring and early warning of geological disasters such as landslides. Equipment is deployed outside the monitoring area to receive reflected signals and monitor surface scene deformation, which can solve the spatial discontinuity problem of differential satellite navigation deformation monitoring. The baseband signal processing of surface scene monitoring is to synchronously sample the intermediate frequency signal and process it in real time online, including capturing, tracking and positioning the direct wave signal, and performing time-frequency synchronization, phase synchronization and pulse compression processing on the echo signal. The time-frequency correspondence of the CA code waveform of the Beidou signal is significantly different from that of the chirp signal. The 20% oversampling of the traditional chirp signal has certain problems. In order to improve the distance resolution of imaging and ensure the loss of signal-to-noise ratio, the Beidou signal within the 40MHz bandwidth must be sampled and processed, so the sampling rate should be greater than 80MHz. In addition, in order to reduce the communication data rate, pulse compression processing of the short-time 1s echo signal is required. In traditional processing methods, the entire signal after ADC sampling is usually directly subjected to FFT and IFFT. This method requires too much calculation and a long processing time, which may take 5 hours in total. It has low processing efficiency and is not feasible in hardware. Summary of the invention

[0003] In view of this, the present invention provides an echo segmented pulse compression method at a high sampling rate based on FPGA, which can perform real-time pulse compression processing on the echo signal, has high processing efficiency, and can reduce the data processing volume and communication data volume. It is achievable in hardware and can be used for engineering applications.

[0004] In order to improve the imaging distance resolution and ensure the loss of signal-to-noise ratio, the signals within the 40MHz bandwidth including the main lobe and the first side lobe of the direct wave and echo Beidou signal must be sampled. In order to prevent signal spectrum aliasing, the signal is sampled using a 124MHz clock, and the sampled signal is a real signal with a data rate of 124MHz. In order to reduce the amount of data processing, the sampled digital real signal is first downsampled and preprocessed. After 2-out-of-1 downsampling, the direct wave and echo digital real signals with a data rate of 124MHz are converted into direct wave and echo digital IQ signals with a data rate of 62MHz. The direct wave IQ signal is captured, tracked, and positioned for standard navigation processing. The accurate Doppler frequency is obtained through the direct wave tracking loop. The direct wave and echo IQ signals are synchronously orthogonally down-converted using the Doppler frequency. The down-converted echo IQ signal and the local CA code signal of the direct wave are subjected to short-time 1ms range pulse compression processing. If the complete echo data of 1ms is directly pulse compressed, the sampling points are 62,000 points. The amount of FFT calculation of 62,000 points in FPGA is very large, which is obviously not feasible. Therefore, an echo segmented pulse compression method is proposed. The simplified method is to reduce the number of pulse compression calculation points and process the 1ms pulse compression segmented. Since 1ms is extracted by 2, the length is 62,000 points. The 1ms echo sampling data is divided into 50 segments, and the length of each 20us data segment is 1240 points. Therefore, a 2048-point FFT calculation is required. The 50 20us pulse compression results are coherently accumulated, and the accumulated result is the pulse compression result of the echo 1ms. In order to ensure the correctness of the imaging result, the atmospheric phase removal at the transmitting end must be achieved. Therefore, phase compensation processing must be performed after each 1ms pulse compression of the echo is completed. Every 1000 1ms echo pulse compression results after phase compensation are coherently accumulated and synthesized. The pulse compression result after 1000 PRT synthesis is the final processed 1s echo pulse pulse compression result. The use of 1s echo pulse compression preprocessing can significantly reduce the amount of end-to-edge data transmission, which is of great significance for the practical application and engineering of equipment. This segmented pulse compression can significantly reduce the amount of data calculation, increase the calculation speed, and save FPGA resources.

[0005] The specific steps of the echo segmented pulse compression method at a high sampling rate based on FPGA of the present invention are as follows:

[0006] S1, the receiver converts the received direct wave and echo RF signals into intermediate frequency analog signals through the RF module circuit, and the analog intermediate frequency is 91.48MHz;

[0007] S2, using a 124MHz clock, the 14-bit quantized ADC is triggered by the same rising edge to perform synchronous intermediate frequency sampling on the Beidou direct wave and echo signal within a 40MHz bandwidth including the main lobe and the first side lobe. The digital intermediate frequency after sampling is 32.52MHz;

[0008] S3, performing downsampling preprocessing on the sampled direct wave and echo digital real signal, the specific steps include:

[0009] S31, synchronously storing the direct wave and echo signal with a data rate of 124 MHz and an intermediate frequency of 32.52 MHz into the multi-channel data FIFO buffer for cross-clock domain processing;

[0010] S32, perform average DC removal processing on the direct wave and echo signal every 2048 points;

[0011] S33, using the same carrier frequency of 32.5MHz to synchronously perform down-conversion on the direct wave and the echo signal, and the direct wave and the echo signal after down-conversion are IQ signals with an intermediate frequency of 20KHz respectively;

[0012] S34, preventing spectrum aliasing from occurring when extracting the signal, and performing low-pass filtering on the direct wave and the echo IQ signal;

[0013] S35, perform 2-out-of-1 processing on the direct wave and echo signal after low-pass filtering, extract the signal data rate after downsampling processing to be 62MHz, send it to the FIFO buffer, and read it out with the divided 62MHz clock;

[0014] S36, the extracted direct wave and echo signal enter the AGC module for automatic gain amplification and truncation processing; the direct wave signal output by the AGC is sent to the capture and tracking module, and the echo signal output by the AGC is sent to the pulse compression module.

[0015] S4, the direct wave signal is quickly captured and tracked, the Doppler frequency of the direct wave signal is obtained by tracking the carrier loop, and the direct wave and the echo signal are synchronously subjected to carrier orthogonal down-conversion processing using the Doppler frequency;

[0016] S5, the echo signal after carrier stripping and the local CA code of the direct wave signal are subjected to short-time 1PRT range-wise segmented pulse compression processing, and the specific steps include:

[0017] S51, after downsampling preprocessing, the sampling rate of the echo signal is 62MHz. In order to meet the requirement that the monitoring distance is greater than 2km in the actual application scenario of the system, the following calculation is performed:

[0018]

[0019] Where c is the speed of light, t is the sampling time, and f s is the sampling rate of the echo signal after downsampling;

[0020] The number of points of 1ms echo data is f s *1e -3 Point, the 1ms echo data is segmented, and the number of points N in each pulse pressure segment is greater than L*f s / c points, so the number of points for FFT calculation is N fft Points, where N fft Take L*f upwards s / cThe value of the nearest integer power of 2;

[0021] S52, the direct wave channel outputs a CA code cycle start pulse every 1ms, and the pulse divides the echo signal periodically. When the pulse arrives, the 1ms echo signal and a period of local CA code signal are synchronously read, and the 1ms echo signal is divided into 50 segments. At the start position of each segment, 2048 points of data are read in sequence, and a period of local CA code signal is divided into 50 segments, each segment of data is 1240 points, and the latter 808 points are padded with zeros. Each segment of echo data and direct wave CA code data read is stored in ping-pong DRAM;

[0022] S53, the 20us echo data and direct wave CA code data read from the Ping-Pong DRAM are pulse compressed in the frequency domain. The 20us pulse compression principle block diagram is as follows: Figure 2 The echo signal is calculated by 2048-point FFT, the direct wave CA code signal is calculated by 2048-point FFT and conjugate, the echo FFT calculation result and the direct wave CA code FFT calculation conjugate result are complex multiplied, and then IFFT operation is performed to output the echo 20us pulse compression result data;

[0023] S54,FFT module clock uses 214MHz. In order to save FPGA logic resources, the FFT module is time-division multiplexed within 20us, and the ping-pong DRAM is also multiplexed;

[0024] S55, coherently accumulate the compression results of 50 adjacent 20us echo pulses to obtain the echo distance pulse compression result of each 1ms;

[0025] S6. In order to remove the influence of the atmospheric phase at the transmitting end, the direct wave compensation phase is obtained in the direct wave channel, and the conjugate multiplication compensation is added to the echo pulse compression result of every 1ms;

[0026] S7. In order to significantly reduce the amount of end-to-edge data transmission, after simulation verification, 1000 PRT synthesis is performed on the 1ms echo pulse compression data, that is, 1000 1ms echo pulse compression results after phase compensation are coherently accumulated, and the first 800 points of data are taken after accumulation to output the echo 1s pulse compression result;

[0027] S8. Quantify and package the echo 1s pulse compression result data and upload it through the Gigabit Ethernet port.

[0028] Beneficial effects:

[0029] The signal sampled by the ADC with a sampling rate of 124MHz is pre-processed by downsampling. The sampling rate is reduced to 62MHz without spectrum aliasing. Then the 1PRT echo signal is segmented and distance-oriented pulse compressed to reduce the total processing volume by 40%, which can significantly reduce the amount of data calculation, improve the operation speed and data processing efficiency, and save FPGA logic resources. In addition, the method of synthesizing 1000 PRTs is used to realize short-time 1s echo pulse compression pre-processing, which greatly reduces the communication data rate. In conjunction with other components of the surface scene deformation monitoring system, the system reliability is improved to ensure that the scene deformation monitoring task can be carried out smoothly. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a flow chart of downsampling preprocessing of direct wave echo signal;

[0031] Figure 2 This is the principle block diagram of echo 20us pulse compression;

[0032] Figure 3 This is the principle block diagram for implementing echo 1s pulse compression;

[0033] Figure 4 Design diagram for low pass filter;

[0034] Figure 5 A schematic diagram of the time relationship of the data stream for pulse compression processing;

[0035] Figure 6 Implement the block diagram for the FFT multiplexing state machine;

[0036] Figure 7 Schematic diagram of echo pulse compression phase compensation process;

[0037] Figure 8 This is the block diagram of the entire echo pulse compression processing FPGA implementation;

[0038] Fig. 9 This is the B3I frequency pulse pressure diagram of PRN21 satellite;

[0039] Fig.10This is the pulse pressure diagram of the B2a frequency point of PRN22 satellite;

[0040] Fig.11 This is the pulse pressure diagram of the B2b frequency point of PRN34 satellite. DETAILED DESCRIPTION

[0041] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0042] The present invention provides an echo segmented pulse compression method at a high sampling rate based on FPGA, comprising the following steps:

[0043] S1, the receiver converts the received direct wave and echo RF signals into intermediate frequency analog signals through the RF module circuit, and the analog intermediate frequency is 91.48MHz;

[0044] S2, the intermediate frequency synchronous ADC performs synchronous intermediate frequency sampling on the Beidou direct wave and echo signal within the 40MHz bandwidth including the main lobe and the first side lobe under the same rising edge trigger;

[0045] The input of the ADC is a multi-channel analog intermediate frequency signal with a sampling rate of 124MHz and a quantization bit number of 14bit. The output is a multi-channel intermediate frequency digital signal with a digital intermediate frequency of 32.52MHz.

[0046] S3, perform downsampling preprocessing on the sampled direct wave and echo digital real signal. The downsampling preprocessing flow chart is as follows: Figure 1 As shown, the specific steps include:

[0047] S31, synchronously storing the direct wave and echo signal with a data rate of 124 MHz and an intermediate frequency of 32.52 MHz into the multi-channel data FIFO buffer for cross-clock domain processing;

[0048] After synchronous acquisition, the echo and direct waves are directly stored in a FIFO with a bit width of 2 times the ADC bit width. The write clock of the FIFO is the ADC sampling clock, and the read clock of the FIFO is the working clock with the same frequency as the write clock.

[0049] S32, perform average DC removal processing on the direct wave and echo signal every 2048 points;

[0050] The direct wave and echo signals read from the FIFO are averaged every 2048 points, and the previous average value is subtracted from the data of each point of the direct wave and echo signals to remove DC.

[0051] S33, using the same carrier frequency of 32.5MHz to synchronously perform down-conversion on the direct wave and the echo signal, and the direct wave and the echo signal after down-conversion are IQ signals with an intermediate frequency of 20KHz respectively;

[0052] The DDC (Digital Down Converson) module directly uses the sin and cos values ​​output by the DDS (Direct Digital Synthetic) in the capture and tracking module, and multiplies them with the direct wave and echo respectively to obtain the direct wave and echo I, Q branch signals.

[0053] S34, preventing spectrum aliasing from occurring when extracting the signal, and performing low-pass filtering on the direct wave and the echo IQ signal;

[0054] The low-pass filter is designed in matlab, using FIR digital filter, the sampling rate is 124MHz, the passband cutoff frequency is 20MHz, the stopband cutoff frequency is 25MHz, the order of the filter is 63, and the low-pass filter design is as follows: Figure 4 As shown in the figure, the coefficients of the designed filter are quantized to 16 bits in Matlab and then the coe coefficient file is output and loaded into the FIR IP core in FPGA for use.

[0055] S35, perform 2-out-of-1 processing on the direct wave and echo signal after low-pass filtering, extract the signal data rate after downsampling processing to be 62MHz, send it to the FIFO buffer, and read it out with the divided 62MHz clock;

[0056] The 124MHz is divided by 2, and the direct wave and echo signal after low-pass filtering are extracted by 2-to-1 extraction using the divided 62MHz clock. The extracted data is sent to the FIFO for cache. The write clock of the FIFO is 124MHz before the division, and the read clock of the FIFO is 62MHz after the division.

[0057] S36, the extracted direct wave and echo signal enter the AGC (Automatic Gain Control) module for automatic gain amplification and truncation processing; the direct wave signal output by the AGC is sent to the capture and tracking module, and the echo signal output by the AGC is sent to the pulse compression module.

[0058] S4, the direct wave signal is quickly captured and tracked, the Doppler frequency of the direct wave signal is obtained by tracking the carrier loop, and the direct wave and the echo signal are synchronously subjected to carrier orthogonal down-conversion processing using the Doppler frequency;

[0059] The DDC module directly uses the sin and cos values ​​output by the DDS in the capture and tracking module, and multiplies them with the direct wave and echo respectively to obtain the direct wave and echo I, Q branch signals. After starting the tracking, the two signals are stored in DRAM. After the above 2x extraction, the sampling rate is 62Msps. The purpose of down-conversion is to convert the direct wave and echo real signals into IQ orthogonal signals, so that the subsequent extraction of the IQ signal will not cause spectrum aliasing.

[0060] S5, the echo signal after carrier stripping and the local CA code of the direct wave signal are subjected to short-time 1PRT range-wise segmented pulse compression processing, and the specific steps include:

[0061] S51, after downsampling preprocessing, the sampling rate of the echo signal is 62MHz. In order to meet the requirement that the monitoring distance is greater than 2km in the actual application scenario of the system, the following calculation is performed:

[0062]

[0063] Where c = 3.0*10 8 , f s =62MHz, so the effective pulse compression points should be greater than 414 points. The points of 1ms echo data are 62000 points. The 1ms echo data is divided into 50 segments, and the points of each 20us data segment are 1240 points. Therefore, the points calculated by FFT are 2048 points.

[0064] S52, the direct wave channel outputs a CA code cycle start pulse every 1ms, and the pulse divides the echo signal periodically. When the pulse arrives, the 1ms echo signal and a period of local CA code signal are synchronously read, and the 1ms echo signal is divided into 50 segments. At the start position of each segment, 2048 points of data are read in sequence, and a period of local CA code signal is divided into 50 segments, each segment of data is 1240 points, and the latter 808 points are padded with zeros. Each segment of echo data and direct wave CA code data read is stored in ping-pong DRAM;

[0065] After stable tracking, the code NCO module outputs a start pulse at the 1ms starting position of each CA code, and the pulse compression module uses this pulse as the DRAM ping-pong storage start signal. Each DRAM storage space is 2048, and it is compressed and calculated at 20us. It switches once every 2048 points of echo data are stored. The code NCO module generates a local CA code. After the pulse compression is started, the CA code is resampled and stored synchronously in the DRAM with a period of 20us. The first 1240 points of DRAM are valid data, and the following 808 points of RAM are filled with 0.

[0066] S53, the 20us echo data and direct wave CA code data read from the Ping-Pong DRAM are pulse compressed in the frequency domain. The 20us pulse compression principle block diagram is as follows: Figure 2 The echo signal is calculated by 2048-point FFT, the direct wave CA code signal is calculated by 2048-point FFT and conjugate, the echo FFT calculation result and the direct wave CA code FFT calculation conjugate result are complex multiplied, and then IFFT operation is performed to output the echo 20us pulse compression result data;

[0067] When a DRAM is full, the FFT module is started. The working clock of DRAM reading and FFT is 124MHz. The FFT module directly uses the Xilinx IP core, and the RAM read address range is 0 to 2047, which is used as the index value of the FFT module input after delay. The FFT results of the direct wave and the echo are respectively multiplied by the conjugate of the FFT of the local CA code. After the complex multiplication results of the two are beat, they are used as the input of the post-stage IFFT data end. The index of the IFFT input data is delayed according to the front-end FFT output index and the delay cycle number of the intermediate complex multiplication operation. The calculation results of IFFT and the accumulation cycle of the back-end DRAM read data are stored in DRAM. After each 1ms cycle, the DRAM is reset to ensure that the first accumulated DRAM output result is 0.

[0068] S54,FFT module clock uses 214MHz. In order to save FPGA logic resources, the FFT module is time-division multiplexed within 20us, and the ping-pong DRAM is also multiplexed;

[0069] The time relationship of the signal pulse compression processing data stream is as follows Figure 5 The two-channel FFT modules are time-division multiplexed within 20us, and the write of RAM1 to RAM4 needs to be multiplexed. In FPGA, the multiplexing of FFT modules is realized through state machine control. The block diagram of FFT multiplexing state machine is shown in Figure 6 shown.

[0070] S55, coherently accumulate the compression results of 50 adjacent 20us echo pulses to obtain the echo distance pulse compression result of each 1ms;

[0071] After the IFFT results are accumulated 50 times, the results are multiplied by the coefficients and then accumulated with the data read from the back-end DRAM and stored in the DRAM in an accumulated loop.

[0072] S6. In order to remove the influence of the atmospheric phase at the transmitting end, the direct wave compensation phase is obtained in the direct wave channel, and conjugate multiplication is used to compensate for the echo pulse compression result every 1ms. The schematic diagram of the echo pulse compression phase compensation process is shown in Figure 7 As shown;

[0073] S7. In order to significantly reduce the amount of data transmission between the end and the edge, after simulation and demonstration, 1000 PRT synthesis is performed on the 1ms echo pulse compression data, that is, 1000 1ms echo pulse compression results after phase compensation are coherently accumulated, and the first 800 points of data are taken after accumulation to output the echo 1s pulse compression result. The principle block diagram of the echo 1s pulse compression implementation is shown in the figure. Figure 3 As shown;

[0074] After each 1000ms cycle, the DRAM is reset to ensure that the first accumulated DRAM output result is 0.

[0075] The entire echo pulse compression processing FPGA implementation block diagram is as follows Figure 8 shown.

[0076] S8. Quantify and package the echo 1s pulse compression result data and upload it through the Gigabit Ethernet port.

[0077] After the 1000ms calculation result is completed, the calculation result is written to the DRAM accessible to the AXI bus, and the corresponding interrupt is sent to the software end to start the data reading. The calculation result and the positioning result are packaged and transmitted through the network port. The data format is 32 bits for each I and Q path, the data size is 800*2*32 bits, and the whole package data coverage length is 1s.

[0078] The effect of the echo segmented pulse compression method at a high sampling rate based on FPGA of the present invention is described below by an example.

[0079] Figures 9 to 11 To test the echo pulse compression results, the eight-star three-frequency direct wave antenna is divided into two paths, one for the direct wave channel and the other for the echo channel test. Fig. 9 This is the B3I frequency pulse pressure diagram of PRN21 satellite. Fig.10 This is the pulse pressure diagram of the B2a frequency point of PRN22 satellite. Fig.11 This is the pulse compression diagram of the B2b frequency point of the PRN34 satellite. From the above three figures, it can be seen that the peak values ​​of the pulse compression results of the eight channels of the eight satellites all appear at the first point, and the peak values ​​of the pulse compression results of the three frequency points also appear at the first point, which is consistent with the theoretical pulse compression results.

[0080] By conducting an eight-star three-frequency direct wave power division test and collecting 600s of data, the peak point phase standard deviation of 600 groups of pulse compression results at eight-star three-frequency points is obtained to verify the phase of the echo pulse compression result, as shown in Tables 1 to 3. It can be seen that the peak point phase standard deviation of 600 groups of pulse compression results at eight-star three-frequency points is less than 1 degree, which meets the design requirements and has high processing efficiency and accuracy.

[0081] Table 1B3 frequency point eight-star 600s pulse compression result peak point phase standard deviation test results

[0082]

[0083]

[0084] Table 2B2a frequency point eight-star 600s pulse compression result peak point phase standard deviation test results

[0085]

[0086] Table 3 Test results of peak point phase standard deviation of eight-star 600s pulse compression results at B2b frequency

[0087]

[0088] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high sampling rate echo segmented pulse compression method based on FPGA, characterized in that: include: Step 1, converting the received direct wave and echo radio frequency signals into intermediate frequency analog signals, the analog intermediate frequency is 91.48MHz; Step 2: Use a 124MHz clock and a 14-bit quantized ADC to perform synchronous intermediate frequency sampling on the Beidou direct wave and echo signal within a 40MHz bandwidth including the main lobe and the first side lobe. The digital intermediate frequency after sampling is 32.52MHz. Step 3, downsampling the sampled direct wave and echo digital real signals by 2 times to convert them into complex signals; Step 4, quickly capture and track the direct wave signal processed in step 3, obtain the Doppler frequency of the direct wave signal by tracking the carrier loop, and use the Doppler frequency to synchronously perform carrier orthogonal down-conversion processing on the direct wave and the echo signal; Step 5, performing short-time 1PRT distance-wise segmented pulse compression processing on the echo signal after carrier stripping and the local CA code of the direct wave signal; Step 6, obtaining the direct wave compensation phase in the direct wave channel, and conjugate multiplying and compensating it into the echo pulse compression result of every 1 ms; Step 7, coherently accumulate the 1000 phase-compensated 1ms echo pulse compression results, and take the first 800 points of data to output the echo 1s pulse compression result; Step 8: quantize and package the echo 1s pulse compression result data and upload it through the Gigabit Ethernet port.

2. The method according to claim 1, characterized in that In step 2, the ADC performs synchronous sampling on the direct wave and the echo signal under the same rising edge trigger.

3. The method according to claim 1, characterized in that In step 3, the downsampling preprocessing is specifically as follows: S31, synchronously storing the direct wave and echo signal acquired in step 2 into a FIFO buffer with a bit width of 2 times the ADC bit width; the write clock of the FIFO is the ADC sampling clock, and the read clock of the FIFO is the working clock with the same frequency as the write clock; S32, the direct wave and echo signal read from the FIFO are averaged every 2048 points, the data of each point of the direct wave and echo signal is subtracted from the previous average value, and the direct wave and echo signal are subjected to DC removal processing; S33, capturing the carrier of the direct wave, and using the carrier to synchronously perform lower sideband processing on the direct wave and the echo signal to obtain the direct wave and the echo IQ signal with an intermediate frequency of 20kHz; S34, performing low-pass filtering on the direct wave and echo IQ signals; S35, divide 124MHz by 2, use the divided 62MHz clock to perform 2-to-1 extraction processing on the direct wave and echo IQ signal after low-pass filtering, and send the extracted data to the FIFO for buffering. The write clock of FIFO is 124MHz before the frequency division, and the read clock of FIFO is 62MHz after the frequency division; S36: The extracted direct wave and echo signal enter the AGC module for automatic gain amplification and truncation processing.

4. The method according to claim 3, characterized in that In the S34, the low-pass filter is designed in matlab, using a FIR digital filter with a sampling rate of 124 MHz, a passband cutoff frequency of 20 MHz, a stopband cutoff frequency of 25 MHz, and a 63-order low-pass filter. The coefficients of the designed filter are quantized to 16 bits in matlab and then a coe coefficient file is output and loaded into the FIR IP core in the FPGA for use.

5. The method according to claim 1, characterized in that In step 3, the DDC module directly uses the sin and cos values ​​output by the DDS in the capture tracking module to multiply them with the direct wave and the echo respectively to obtain the direct wave and echo I, Q branch signals. After starting the tracking, the two signals are stored in the DRAM. After the above-mentioned 2x decimation, the sampling rate is 62Msps.

6. The method according to claim 1, characterized in that The step 5 specifically includes: S51. Calculate the number of effective pulse compression points N according to the requirements of the monitoring distance L in the actual application scenario of the system: Where c is the speed of light, t is the sampling time, and f s is the sampling rate of the echo signal after downsampling in step 3; S52. After stable tracking, the direct wave channel outputs a CA code period start pulse every 1ms. The pulse divides the echo signal periodically. When the pulse arrives, the 1ms echo signal and a period of local CA code signal are synchronously read; the 1ms echo signal is segmented and N segments are read back in sequence at the starting position of each segment. fft Point data, the local CA code signal of each cycle is processed in segments, and each segment of data is L*f s / c point, followed by N fft -L*f s / c point fill zero; where N fft Take L*f upwards s / c is the value of the nearest integer power of 2; each echo data and direct wave CA code data read is stored in the Ping-Pong DRAM; S53, when a DRAM is full, start the FFT module; the DRAM reading and FFT working clock is 124MHz; the FFT module directly uses the Xilinx IP core, and the RAM reading address range is 0~2047, which is used as the index value of the FFT module input after delay; the FFT results of the direct wave and the echo are respectively multiplied by the conjugate of the FFT of the local CA code; the complex multiplication results of the two are used as the input of the post-stage IFFT data terminal after beating, and the index of the IFFT input data is delayed according to the front-end FFT output index and the delay cycle number of the intermediate complex multiplication operation; the calculation result of IFFT and the accumulation cycle of the back-end DRAM reading data are stored in DRAM; after each 1ms cycle, the DRAM is reset to ensure that the first accumulated DRAM output result is 0; among them, the FFT module clock uses 214MHz; the FFT modules of the direct wave channel and the echo signal channel are time-division multiplexed within 20us; S54, coherently accumulate the compression results of 50 adjacent 20us echo pulses to obtain the echo distance pulse compression result of each 1ms.

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