BCI optimization circuit in LIN bus, optimization method and transceiver

Abstract

The invention provides a BCI optimization circuit in an LIN bus, an optimization method and a transceiver, and is applied to the technical field of LIN transceivers, and the BCI optimization circuit comprises a pull-up path and a pull-down path which are respectively connected with the LIN bus; the grid of the field-effect tube of the pull-down path is connected with the grid control module; the grid control module controls energy coupled to the grid of the field effect transistor, so that the optimization circuit has anti-interference capability. When the LIN bus is at a low level or a high level, the grid control module controls the energy coupled to the grid of the field effect transistor, so that the optimization circuit has the anti-interference capability, and the difference between a rising edge and a falling edge is not large compared with that when interference is not added; moreover, when the work of the LIN transceiver is interfered by the BCI, normal communication can still be realized, and communication error codes are not generated, so that the reliability and robustness of LIN communication are improved.

Description

Technical Field

[0001] The present application relates to the technical field of LIN transceivers, and in particular to a BCI optimization circuit, optimization method and transceiver in a LIN bus. Background Art

[0002] LIN (Local Interconnect Network) transceiver is a low-cost serial communication protocol device based on UART / SCI (Universal Asynchronous Receiver-Transmitter / Serial Communication Interface). LIN transceiver usually consists of two parts: transmitter and receiver. The transmitter is responsible for converting data into electrical signals and sending them to the receiver through the LIN bus; while the receiver is responsible for receiving data and converting it into a computer-readable format.

[0003] However, when the LIN transceiver is working, it is susceptible to BCI (Bulk Current Injection) interference, which makes it difficult to communicate normally and easily causes communication errors, resulting in poor reliability of LIN communication.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, the present application provides a BCI optimization circuit, optimization method and transceiver in a LIN bus.

[0006] This application provides the following technical solutions:

[0007] According to a BCI optimization circuit in a LIN bus provided by the present application, the circuit comprises a pull-up path and a pull-down path respectively connected to the LIN bus; the pull-up path is used to pull the LIN bus up to a high level state, and the pull-down path is used to pull the LIN bus down to a low level state;

[0008] The pull-down path includes a field effect transistor, and the gate of the field effect transistor is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field effect transistor so that the optimized circuit has anti-interference capability.

[0009] Preferably, the gate control module includes a current source, a switch and a control resistor;

[0010] One end of the current source is connected to the pull-up path; the other end of the current source is connected to one end of the switch; the other end of the switch is respectively connected to one end of the control resistor and the gate of the field effect tube;

[0011] The other end of the control resistor is connected to the source of the field effect transistor, and the other end of the control resistor is grounded.

[0012] Preferably, the pull-down path further includes a pull-down diode;

[0013] The anode of the pull-down diode is connected to the LIN bus, and the cathode of the pull-down diode is connected to the drain of the field effect transistor.

[0014] Preferably, the pull-up path includes a pull-up diode and a pull-up resistor;

[0015] The anode of the pull-up diode is connected to one end of the current source; the cathode of the pull-up diode is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the LIN bus.

[0016] Preferably, the control resistor is smaller than the parasitic capacitance C between the gate and drain of the field effect tube. GD The equivalent impedance of the control resistor and the parasitic capacitance C GD The equivalent impedance of is different by more than n times, n is greater than 5;

[0017] The current source current multiplied by the control resistance is greater than the threshold turn-on voltage V of the field effect tube TH To enable the normal opening and closing of the LIN bus;

[0018] The current source current multiplied by the control resistance is less than or equal to the maximum gate withstand voltage of the field effect transistor to ensure the gate withstand voltage of the field effect transistor.

[0019] Preferably, when the switch is closed, the gate voltage of the field effect tube is the current source current multiplied by the control resistance, the field effect tube is turned on, the LIN bus is pulled down to a low level state, and at the same time, the energy coupled to the gate of the field effect tube is controlled according to the control resistance to keep the LIN bus in a low level state.

[0020] Preferably, when the switch is disconnected, the gate voltage of the field effect tube is 0, the field effect tube is turned off, the LIN bus is pulled up to a high level state, and the energy coupled to the gate of the field effect tube is controlled according to the control resistor to maintain the high level state of the LIN bus.

[0021] Preferably, the field effect transistor is an N-channel field effect transistor.

[0022] According to an optimization method provided by the present application, a BCI optimization circuit in a LIN bus described above is applied, including: a gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimization circuit has anti-interference capability and maintains the level state of the LIN bus.

[0023] A transceiver provided according to the present application includes a transmitter, a receiver, a LIN bus, and a BCI optimization circuit in any of the above-mentioned LIN buses; the transmitter is connected to the receiver via the LIN bus.

[0024] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the present application include at least:

[0025] In the present application, when the LIN bus is at a low level or a high level, the gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimized circuit has anti-interference ability, and the rising edge and the falling edge are not much different compared to when no interference is added; moreover, when the LIN transceiver is interfered by BCI, it can still communicate normally without causing communication errors, thereby improving the reliability and robustness of LIN communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 Schematic diagram of the LIN bus BCI optimization design circuit for this application. DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0029] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0030] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0032] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0033] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0034] The embodiment of this specification proposes a BCI optimization circuit in a LIN bus, such as Figure 1 As shown, it includes a pull-up path and a pull-down path connected to the LIN bus respectively; the pull-up path is used to pull the LIN bus to a high level state, and the pull-down path is used to pull the LIN bus to a low level state.

[0035] The pull-down path includes a field effect transistor, and the gate of the field effect transistor is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field effect transistor so that the optimized circuit has anti-interference capability.

[0036] In one embodiment, if Figure 1 As shown, the gate control module includes a current source, a switch and a control resistor; one end of the current source is connected to the pull-up path; the other end of the current source is connected to one end of the switch; the other end of the switch is respectively connected to one end of the control resistor and the gate of the field effect tube; the other end of the control resistor is connected to the source of the field effect tube, and the other end of the control resistor is grounded.

[0037] In one embodiment, if Figure 1 As shown, the pull-down path also includes a pull-down diode; the anode of the pull-down diode is connected to the LIN bus, and the cathode of the pull-down diode is connected to the drain of the field effect transistor.

[0038] In one embodiment, if Figure 1 As shown, the pull-up path includes a pull-up diode and a pull-up resistor; the anode of the pull-up diode is connected to one end of the current source; the cathode of the pull-up diode is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the LIN bus.

[0039] In one embodiment, the control resistor is smaller than the parasitic capacitance C between the gate and the drain of the field effect transistor. GD The equivalent impedance of the control resistor and parasitic capacitance C GD The equivalent impedance differs by more than n times, n is greater than 5, and preferably n is equal to 10.

[0040] The current source current multiplied by the control resistance is greater than the threshold turn-on voltage V of the field effect tube TH To ensure the normal opening and closing of the LIN bus; the current source current multiplied by the control resistance is less than or equal to the maximum gate withstand voltage of the field effect tube to ensure the gate withstand voltage of the field effect tube.

[0041] In one embodiment, when the gate control module switches on, the gate voltage of the field effect transistor is the current source current multiplied by the control resistor, the field effect transistor is turned on, the LIN bus is pulled down to a low level state, and at the same time, the energy coupled to the gate of the field effect transistor is controlled according to the control resistor to keep the LIN bus in a low level state.

[0042] In one embodiment, when the switch of the gate control module is disconnected, the gate voltage of the field effect tube is 0, the field effect tube is turned off, the LIN bus is pulled up to a high level state, and the energy coupled to the gate of the field effect tube is controlled according to the control resistor to maintain the high level state of the LIN bus.

[0043] In one embodiment, if Figure 1 As shown, the field effect transistor is an N-channel field effect transistor.

[0044] like Figure 1 As shown, the LIN bus BCI optimization design circuit of the present application, wherein D1 and R1 constitute the internal pull-up path of the LIN bus; D2 and NM1 constitute the pull-down control path of the LIN bus, and the current source I1, switch K2 and resistor R2 constitute the gate control circuit of the NM1 power tube. Figure 1 In the figure, D1 represents a pull-up diode; R1 represents a pull-up resistor; D2 represents a pull-down diode; I1 represents a current source; K2 represents a switch; R2 represents a control resistor; NM1 represents an N-channel field effect transistor; and VBAT represents a power supply voltage.

[0045] When K1 is closed, the gate voltage of NM1 is I1*R2, and the NM1 tube is turned on, thereby pulling down the LIN bus. At this time, if there is BCI interference energy injected on the bus, then due to the large current I1 and the small resistance R2, R2 should be much smaller than the parasitic capacitance C between the gate and the drain of NM1. GD The equivalent impedance of the parasitic capacitance C GD After designing the equivalent impedance of resistor R2, we design the size of current source I1. Considering the normal opening and closing of the LIN bus, I1*R2 must be greater than the threshold opening voltage V of NM1. TH , but at the same time consider the gate voltage of NM1 tube, I1*R2 should be less than or equal to the maximum gate voltage of NM1 tube. R2 is much smaller than the parasitic capacitance C between the gate and the drain of NM1 GD The equivalent impedance can ensure that the energy coupled to the NM1 gate is small, making it difficult to interfere with the current LIN bus low level state.

[0046] When K1 is disconnected, the gate voltage of NM1 is 0, and the NM1 tube is turned off, so that the LIN bus is pulled up to the VBAT power supply. At this time, if there is BCI anti-interference energy injection, due to the small resistance R2, it is difficult for all NM1 gate voltages to couple and turn on NM1 by mistake, so it is difficult to interfere with the current high level state of the LIN bus.

[0047] Therefore, the larger current source I1 and the smaller resistor R2 make it difficult for BCI interference to couple into the internal circuit when the LIN bus is at a high level or a low level, thereby causing malfunction, and ultimately achieving the purpose of enhancing the system BCI anti-interference capability.

[0048] The embodiments of this specification also disclose an optimization method, which applies the BCI optimization circuit in the LIN bus of any of the above embodiments, including: a gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimization circuit has anti-interference ability and maintains the level state of the LIN bus.

[0049] The embodiments of this specification also disclose a transceiver, including a transmitter, a receiver, a LIN bus, and a BCI optimization circuit in the LIN bus according to any one of claims 1 to 8; the transmitter is connected to the receiver via the LIN bus.

[0050] The present application is a LIN bus BCI optimization circuit and method, which can still communicate normally when the LIN transceiver is interfered by BCI, and will not cause communication errors, thereby ensuring the reliability and robustness of LIN communication. The present application has the characteristics of strong anti-BCI interference ability, high integration, simple circuit structure and high reliability. For example, it has strong anti-EMI (Electromagnetic Interference) interference ability. The present application can control the circuit to have a strong anti-interference ability when the LIN bus is at a low level or a high level, so that it will not be turned over by mistake, and the rising edge and the falling edge are not much different compared to when no interference is added.

[0051] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0052] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A BCI optimization circuit in a LIN bus, characterized in that: It includes a pull-up path and a pull-down path respectively connected to the LIN bus; the pull-up path is used to pull the LIN bus up to a high level state, and the pull-down path is used to pull the LIN bus down to a low level state; The pull-down path includes a field effect transistor, and the gate of the field effect transistor is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field effect transistor so that the optimized circuit has anti-interference capability.

2. The BCI optimization circuit in the LIN bus according to claim 1, characterized in that: The gate control module includes a current source, a switch and a control resistor; One end of the current source is connected to the pull-up path; the other end of the current source is connected to one end of the switch; the other end of the switch is respectively connected to one end of the control resistor and the gate of the field effect tube; The other end of the control resistor is connected to the source of the field effect transistor, and the other end of the control resistor is grounded.

3. The BCI optimization circuit in the LIN bus according to claim 2, characterized in that: The pull-down path also includes a pull-down diode; The anode of the pull-down diode is connected to the LIN bus, and the cathode of the pull-down diode is connected to the drain of the field effect transistor.

4. The BCI optimization circuit in the LIN bus according to claim 2, characterized in that: The pull-up path includes a pull-up diode and a pull-up resistor; The anode of the pull-up diode is connected to one end of the current source; the cathode of the pull-up diode is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the LIN bus.

5. The BCI optimization circuit in the LIN bus according to claim 2, characterized in that: The control resistor is smaller than the parasitic capacitance C between the gate and drain of the field effect tube. GD The equivalent impedance of the control resistor and the parasitic capacitance C GD The equivalent impedance of the resistors differs by more than n times, where n is greater than 5; The current source current multiplied by the control resistance is greater than the threshold turn-on voltage V of the field effect tube TH To enable the normal opening and closing of the LIN bus; The current source current multiplied by the control resistance is less than or equal to the maximum gate withstand voltage of the field effect transistor to ensure the gate withstand voltage of the field effect transistor.

6. The BCI optimization circuit in the LIN bus according to claim 5, characterized in that: When the switch is closed, the gate voltage of the field effect tube is the current source current multiplied by the control resistance, the field effect tube is turned on, the LIN bus is pulled down to a low level state, and the energy coupled to the gate of the field effect tube is controlled according to the control resistance to keep the LIN bus in a low level state.

7. The BCI optimization circuit in the LIN bus according to claim 5, characterized in that: When the switch is disconnected, the gate voltage of the field effect tube is 0, the field effect tube is turned off, the LIN bus is pulled up to a high level state, and the energy coupled to the gate of the field effect tube is controlled according to the control resistor to maintain the high level state of the LIN bus.

8. The BCI optimization circuit in the LIN bus according to any one of claims 1 to 7, characterized in that: The field effect transistor is an N-channel field effect transistor.

9. An optimization method, characterized in that: The BCI optimization circuit in the LIN bus according to any one of claims 1 to 8 includes: a gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimization circuit has anti-interference ability and maintains the level state of the LIN bus.

10. A transceiver, characterized in that: The invention comprises a transmitter, a receiver, a LIN bus and a BCI optimization circuit in the LIN bus as described in any one of claims 1 to 8; the transmitter is connected to the receiver via the LIN bus.

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