Semiconductor device and manufacturing method thereof
During the production process of non-planar semiconductor devices, the stacked film layer and sacrificial layer protection technology are used to gradually remove the insulating layer at the bottom of the opening, solving the electrical performance problems caused by structural defects and achieving higher product electrical performance.
Patent Information
- Application Number
- CN202410841382.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-26
- Publication Date
- 2025-02-07
AI Technical Summary
During the production of non-planar semiconductor devices, structural defects are prone to occur, affecting the electrical performance of the product.
By forming a stacked film layer on the substrate and forming a first and second sacrificial layers in the opening, multiple etching and cleaning are performed, and the insulating layer at the bottom of the opening is gradually removed, thereby forming a trench that exposes the conductive layer.
This method reduces damage to the insulating layer through double sacrificial layer protection, reduces the impact of breakdown voltage and wafer acceptability tests, and improves the electrical performance of the product.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] Non-planar semiconductor devices are widely used in mobile devices such as mobile phones and tablet computers due to their advantages of small size, large capacity, high integration and fast transmission speed. However, structural defects are prone to occur during the manufacturing process of non-planar semiconductor devices, which in turn affect the electrical performance of the product.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0004] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, which can reduce structural defects and improve product electrical performance.
[0005] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:
[0006] A stacked film layer is formed on a substrate, wherein the stacked film layer comprises a first conductive layer, a first insulating layer, and a second conductive layer stacked in sequence along a vertical direction; an opening is formed in the stacked film layer, and the opening penetrates the second conductive layer in the vertical direction;
[0007] forming a second insulating layer and a first sacrificial layer, wherein the second insulating layer at least covers the sidewalls of the opening, and the first sacrificial layer is located on the surface of the second insulating layer;
[0008] removing a portion of the first insulating layer located at the bottom of the opening;
[0009] forming a second sacrificial layer in the opening having the first sacrificial layer;
[0010] The first insulating layer remaining at the bottom of the opening is removed to form a groove exposing the first conductive layer.
[0011] In an exemplary embodiment of the present disclosure, removing a portion of the first insulating layer located at the bottom of the opening comprises the following steps:
[0012] Step S1, forming a first protective layer on the sidewall and bottom of the opening having the first sacrificial layer;
[0013] Step S2, etching the first protective layer located at the bottom of the opening and the film layer adjacent to the first protective layer at the bottom of the opening;
[0014] Step S3, cleaning the opening to remove the first protective layer and residues from the etching process;
[0015] Repeat steps S1 to S3 for a preset number of times.
[0016] In an exemplary embodiment of the present disclosure, the preset number of times is 3 to 20 times.
[0017] In an exemplary embodiment of the present disclosure, a material of the first sacrificial layer is polysilicon, silicon oxide or silicon nitride.
[0018] In an exemplary embodiment of the present disclosure, the density of the second sacrificial layer is greater than or equal to 2.09 g / cm 3 .
[0019] In an exemplary embodiment of the present disclosure, a material of the second sacrificial layer is polysilicon, silicon oxide, silicon nitride or carbon.
[0020] In an exemplary embodiment of the present disclosure, removing the first insulating layer remaining at the bottom of the opening to form a groove exposing the first conductive layer comprises the following steps:
[0021] Step S4, forming a second protective layer on the sidewall and bottom of the opening having the second sacrificial layer;
[0022] Step S5, etching the second protection layer located at the bottom of the opening and the first insulating layer located at the bottom of the opening;
[0023] Step S6, cleaning the opening to remove the second protective layer and residues from the etching process;
[0024] Step S4 to step S6 are repeated until the first insulating layer does not exist on the surface of the region of the first conductive layer directly facing the bottom of the opening.
[0025] In an exemplary embodiment of the present disclosure, the material of the first protective layer is carbon.
[0026] In an exemplary embodiment of the present disclosure, the material of the second protective layer is carbon, silicon nitride or silicon oxide.
[0027] In an exemplary embodiment of the present disclosure, forming a first protective layer on the sidewall and the bottom of the opening having the first sacrificial layer includes:
[0028] The first protective layer is formed by a mixed gas of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8) and fluoromethane (CH3F), and the flow ratio of the perfluorobutadiene (C4F6), the perfluorocyclobutane (C4F8) and the fluoromethane (CH3F) is 1:1:1 to 3:3:1.
[0029] In an exemplary embodiment of the present disclosure, after forming the trench, the method for manufacturing the semiconductor device further includes:
[0030] The second sacrificial layer and the first sacrificial layer are removed.
[0031] In an exemplary embodiment of the present disclosure, the stacked film layer further includes a third insulating layer, the third insulating layer is located on a side of the second conductive layer away from the substrate, the opening penetrates the third insulating layer and the second conductive layer at the same time, the second insulating layer is also formed on a surface of a sidewall surrounded by the third insulating layer in the opening, and after removing the second sacrificial layer and the first sacrificial layer, the method for manufacturing the semiconductor device further includes:
[0032] forming a channel layer on a surface of the second insulating layer located on a sidewall of the trench;
[0033] Filling the trench having the channel layer with an insulating material to form an insulating dielectric layer;
[0034] A third conductive layer is formed on a side of the channel layer away from the substrate.
[0035] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device is manufactured using any one of the semiconductor device manufacturing methods described above.
[0036] The semiconductor device and the manufacturing method thereof disclosed in the present invention can protect the second insulating layer on the side wall of the opening through the first sacrificial layer in the process of removing part of the first insulating layer at the bottom of the opening, thereby reducing the probability of damaging the second insulating layer; after removing the part of the first insulating layer located at the bottom of the opening, a second sacrificial layer can be formed in the opening with the first sacrificial layer, and the protection of the second insulating layer on the side wall of the opening is strengthened through the formation of the second sacrificial layer, so as to prevent the first sacrificial layer from being thinned due to wear during the process, thereby weakening the protective effect of the second insulating layer; in the subsequent etching process of the remaining film layer at the bottom of the opening, the second insulating layer can be doubly protected by the first sacrificial layer and the first sacrificial layer at the same time, which helps to reduce the damage to the second insulating layer on the side wall of the opening in the process of removing the remaining first insulating layer at the bottom of the opening, reduce the impact of the damage to the second insulating layer on the breakdown voltage and wafer acceptability test of the finally formed semiconductor device, and improve the electrical performance of the product.
[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0039] Figure 1 It is a schematic diagram of a sacrificial layer in a related technology of the present disclosure.
[0040] Figure 2 It is a schematic diagram of a sacrificial layer in a related technology of the present disclosure.
[0041] Figure 3 It is a schematic diagram of a slot portion in a related technology disclosed in the present invention.
[0042] Figure 4 The flowchart is a method for manufacturing a semiconductor device in an embodiment of the present disclosure.
[0043] Figure 5 Schematic diagram of stacked film layers in an embodiment of the present disclosure.
[0044] Figure 6 Schematic diagram of the second insulating layer in an embodiment of the present disclosure.
[0045] Figure 7 Schematic diagram of the first sacrificial layer in an embodiment of the present disclosure.
[0046] Figure 8 It is a schematic diagram of the structure after completing step S130 in the embodiment of the present disclosure.
[0047] Fig. 9 It is a schematic diagram of the structure after completing step S1 in one embodiment of the present disclosure.
[0048] Fig.10 It is a schematic diagram of the structure after completing step S2 in one embodiment of the present disclosure.
[0049] Fig.11 It is a schematic diagram of the structure after completing step S3 in one embodiment of the present disclosure.
[0050] Fig.12 It is a schematic diagram of the structure after steps S1 to S3 are repeated multiple times in an embodiment of the present disclosure.
[0051] Fig.13 It is a schematic diagram of the structure after completing step S140 in the embodiment of the present disclosure.
[0052] Fig.14 It is a schematic diagram of the structure after completing step S150 in the embodiment of the present disclosure.
[0053] Fig.15 It is a schematic diagram of the structure after the second sacrificial layer is removed in the embodiment of the present disclosure.
[0054] Fig.16 It is a schematic diagram of the structure after completing step S160 in the embodiment of the present disclosure.
[0055] Fig.17 It is a schematic diagram of the structure after completing step S230 in the embodiment of the present disclosure.
[0056] Description of reference numerals:
[0057] 10. Sacrificial layer; 20. Insulating layer; 30. Protective layer; 101. Channel opening; 102. Groove portion; 1. Substrate; 2. Stacked film layers; 21. First conductive layer; 22. First insulating layer; 23. Second conductive layer; 231. Conductive portion; 24. Insulating material layer; 25. Third insulating layer; 26. Fourth insulating layer; 201. Opening; 202. Groove; 3. Second insulating layer; 4. First sacrificial layer; 5. Second sacrificial layer; 6. First protective layer; 7. Channel layer; 8. Insulating dielectric layer; 9. Third conductive layer. DETAILED DESCRIPTION
[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0059] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
[0060] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.
[0061] In the process of manufacturing transistors, during the etching process of the bottom opening of the channel, it is usually necessary to protect the insulating layer 20 in the opening through the protective layer 30 and the sacrificial layer 10 formed on the surface of the protective layer 30, and directly form the channel opening 101 through the etching process after the sacrificial layer 10 is formed. However, in the above process, affected by the preparation process, it is difficult for the sacrificial layer 10 to be deposited to the bottom of the channel opening 101, and the thickness of the sacrificial layer 10 deposited on the sidewall of the channel opening 101 is also relatively small (e.g., Figure 1 As shown in the figure, the sacrificial layer 10 has a weak ability to protect the sidewalls, which makes it easy to damage the protective layer 30 and the insulating layer 20 during the etching process, thereby affecting the wafer acceptability test and electrical properties such as breakdown voltage. When the thickness of the sacrificial layer 10 is thin, pinholes are likely to appear inside the sacrificial layer 10 under the bombardment of high bias during the etching process, and the plasma is likely to enter the protective layer 30 and the insulating layer 20 through the pinholes, thereby damaging the insulating layer 20; and when the thickness of the sacrificial layer 10 is thick (as shown in the figure), the protective layer 30 and the insulating layer 20 are likely to be damaged during the etching process. Figure 2 As shown in FIG. 1 , the sacrificial layer 10 occupies more space at the top of the opening, making it difficult for the plasma to etch laterally, resulting in a smaller area of the area to be etched at the bottom of the channel opening 101, and a larger size at the bottom corner of the groove 102 formed after removing the sacrificial layer 10 (as shown in FIG. 1 ). Figure 3 As shown in the circle, charges are easily concentrated here and leakage occurs.
[0062] Based on this, the present disclosure provides a method for manufacturing a semiconductor device, such as Figure 4 As shown, the method for manufacturing the semiconductor device may include steps S110 to S150, wherein:
[0063] Step S110, forming a stacked film layer on the substrate, the stacked film layer comprising a first conductive layer, a first insulating layer, and a second conductive layer stacked in sequence along a vertical direction; an opening is formed in the stacked film layer, and the opening penetrates the second conductive layer in the vertical direction;
[0064] Step S120, forming a second insulating layer and a first sacrificial layer, wherein the second insulating layer at least covers the sidewalls of the opening, and the first sacrificial layer is located on the surface of the second insulating layer;
[0065] Step S130, removing a portion of the first insulating layer located at the bottom of the opening;
[0066] Step S140, forming a second sacrificial layer in the opening having the first sacrificial layer;
[0067] Step S150 , removing the first insulating layer remaining at the bottom of the opening to form a groove exposing the first conductive layer.
[0068] The manufacturing method of the semiconductor device disclosed in the present invention can protect the second insulating layer on the side wall of the opening through the first sacrificial layer in the process of removing part of the first insulating layer at the bottom of the opening, thereby reducing the probability of damaging the second insulating layer; after removing the part of the first insulating layer located at the bottom of the opening, a second sacrificial layer can be formed in the opening with the first sacrificial layer, and then the protection of the second insulating layer on the side wall of the opening is strengthened through the formation of the second sacrificial layer, so as to prevent the first sacrificial layer from being thinned due to wear during the process, thereby weakening the protective effect of the second insulating layer; in the subsequent etching process of the remaining film layer at the bottom of the opening, the second insulating layer can be doubly protected by the first sacrificial layer and the first sacrificial layer at the same time, which helps to reduce the damage to the second insulating layer on the side wall of the opening during the process of removing the remaining first insulating layer at the bottom of the opening, reduce the impact of the damage to the second insulating layer on the breakdown voltage and wafer acceptability test of the finally formed semiconductor device, and improve the electrical performance of the product.
[0069] The following is a detailed description of the steps and specific details of the method for manufacturing a semiconductor device disclosed in the present invention:
[0070] like Figure 4 As shown, in step S110, a stacked film layer is formed on the substrate, and the stacked film layer includes a first conductive layer, a first insulating layer, and a second conductive layer stacked in sequence along a vertical direction; an opening is formed in the stacked film layer, and in the vertical direction, the opening penetrates the second conductive layer.
[0071] like Figure 5 As shown, the substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, germanium, silicon carbide or silicon germanium, etc., and no special limitation is made to the shape and material of the substrate 1.
[0072] Please continue to see Figure 5 As shown, a stacked film layer 2 can be formed on a substrate 1, and the stacked film layer 2 can include a first conductive layer 21, a first insulating layer 22 and a second conductive layer 23 stacked and distributed in sequence along a vertical direction; wherein the vertical direction can be a direction perpendicular to the extension direction of the substrate 1.
[0073] Please continue to see Figure 5As shown, the first conductive layer 21 can be formed on the surface of the substrate 1. The first conductive layer 21 can be a single film layer or a composite film layer structure composed of multiple film layers, which is not particularly limited here. The material of the first conductive layer 21 can be a material with good conductivity, for example, its material can be polysilicon or tungsten. In some embodiments of the present disclosure, the first conductive layer 21 can be used as a source or drain of a transistor.
[0074] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 5 As shown, the stacked film layer 2 of the present disclosure may further include an insulating material layer 24, which may be formed on the surface of the substrate 1, and the insulating material layer 24 may be adjacent to the first conductive layer 21 and surround the periphery of the first conductive layer 21. The surface of the insulating material layer 24 away from the substrate 1 may be flush with the surface of the first conductive layer 21 away from the substrate 1, so as to provide a flat process reference for subsequent processes, which helps to reduce the difficulty of the process. The material of the insulating material layer 24 may be silicon oxide or silicon nitride, etc.
[0075] Please continue to see Figure 5 As shown, the first insulating layer 22 may cover the surface of the first conductive layer 21 away from the substrate 1. When an insulating material layer 24 is also formed on the substrate 1, the first insulating layer 22 may also cover the insulating material layer 24. The material of the first insulating layer 22 may be silicon oxide.
[0076] Please continue to see Figure 5 As shown, the second conductive layer 23 can be formed on the surface of the first insulating layer 22. At this time, the second conductive layer 23 and the first conductive layer 21 can be insulated and isolated by the first insulating layer 22 to prevent coupling or short circuit between the second conductive layer 23 and the first conductive layer 21. The second conductive layer 23 can be a single-layer film structure or a composite film structure composed of multiple film layers, which is not particularly limited here. The material of the second conductive layer 23 can be a material with good conductive properties, for example, its material can be polysilicon or tungsten.
[0077] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 5 As shown, the stacked film layer 2 may further include a third insulating layer 25. The third insulating layer 25 may be formed on a side of the second conductive layer 23 away from the substrate 1. The second conductive layer 23 may be insulated and protected by the third insulating layer 25 to reduce the risk of coupling or short circuit between the second conductive layer 23 and other conductive structures formed subsequently.
[0078] In an exemplary embodiment of the present disclosure, the stacked film layer 2 may further include a fourth insulating layer 26, which may be located on the surface of the first insulating layer 22 away from the substrate 1, and the fourth insulating layer 26 may be adjacent to the second conductive layer 23 and the third insulating layer 25 located on the top of the second conductive layer 23. The second conductive layer 23 may be insulated and protected in the lateral direction (i.e., in the direction parallel to the substrate 1) by the fourth insulating layer 26 to prevent coupling or short circuit between the second conductive layer 23 and other surrounding conductive structures, thereby helping to improve the reliability of the device. It should be noted that the surface of the fourth insulating layer 26 away from the substrate 1 may be flush with the surface of the third insulating layer 25 away from the substrate 1.
[0079] In some embodiments of the present disclosure, a first conductive layer 21, a first insulating layer 22, a second conductive layer 23 and a third insulating layer 25 may be sequentially formed on the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the first conductive layer 21, the first insulating layer 22, the second conductive layer 23 or the third insulating layer 25 may also be formed by other methods, and the formation method of the first conductive layer 21, the first insulating layer 22, the second conductive layer 23 and the third insulating layer 25 is not specifically limited here. It should be noted that when the stacked film layer 2 also includes an insulating material layer 24, before forming the first insulating layer 22, an insulating material layer 24 may also be formed on the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other methods. When the stacked film layer 2 also includes a fourth insulating layer 26, the fourth insulating layer 26 may be formed after the third insulating layer 25 is formed.
[0080] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 5 As shown, an opening 201 is formed in the stacked film layer 2, and the opening 201 can penetrate the second conductive layer 23 in the vertical direction and expose the first insulating layer 22 below the second conductive layer 23. It should be noted that in order to ensure that the opening 201 completely carves through the second conductive layer 23, the opening 201 can be extended into the first insulating layer 22. The orthographic projection of the bottom surface of the opening 201 on the substrate 1 can be located within the orthographic projection of the first conductive layer 21 on the substrate 1. The opening 201 can divide the second conductive layer 23 into a plurality of conductive portions 231 distributed at intervals. In some embodiments of the present disclosure, the conductive portion 231 can be used as a gate of a transistor. It should be noted that when the stacked film layer 2 also includes a third insulating layer 25, the opening 201 can penetrate the third insulating layer 25 and the second conductive layer 23 at the same time, that is, the top of each conductive portion 231 separated by the opening 201 is also formed with the third insulating layer 25.
[0081] like Figure 4As shown, in step S120 , a second insulating layer 3 and a first sacrificial layer 4 are formed, wherein the second insulating layer 3 at least covers the sidewalls of the opening 201 , and the first sacrificial layer 4 is located on the surface of the second insulating layer 3 .
[0082] like Figure 6 As shown, the material of the second insulating layer 3 may be an insulating material, for example, the material may be silicon oxide. The second insulating layer 3 may be formed in the opening 201 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that, for the convenience of the process, the second insulating layer 3 may conformally cover the sidewalls and bottom surface of the opening 201, and when the stacked film layer 2 includes the third insulating layer 25, the second insulating layer 3 may also cover the surface of the third insulating layer 25, and simultaneously be formed on the surface of the sidewalls surrounded by the third insulating layer 25 in the opening 201.
[0083] like Figure 7 As shown, the first sacrificial layer 4 can conformally cover the surface of the second insulating layer 3, and the first sacrificial layer 4 can protect the surface of the second insulating layer 3 to prevent the plasma from damaging the second insulating layer 3 during the subsequent etching process. In an exemplary embodiment of the present disclosure, the material of the first sacrificial layer 4 can be polysilicon, silicon oxide or silicon nitride, etc., and the first sacrificial layer 4 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc., and the formation method of the first sacrificial layer 4 is not specifically limited here. It should be noted that, for the convenience of the process, the first sacrificial layer 4 can simultaneously cover the top area of the stacked film layer 2, the sidewalls of the opening 201 and the bottom of the opening 201. For example, when the stacked film layer 2 includes the third insulating layer 25, the first sacrificial layer 4 can simultaneously cover the surface of the second insulating layer 3 on the top of the third insulating layer 25, the sidewalls of the opening 201 and the bottom of the opening 201.
[0084] like Figure 4 As shown, in step S130 , a portion of the first insulating layer 22 located at the bottom of the opening 201 is removed.
[0085] After forming the first sacrificial layer 4, a portion of the first insulating layer 22 at the bottom of the opening 201 can be removed by etching. In this process, the first sacrificial layer 4 can be used as a protective layer, thereby reducing the probability of damaging the second insulating layer 3 during the etching process, which helps to reduce structural defects and improve product reliability. In the embodiment of the present disclosure, the structure after completing step S130 is as follows Figure 8 shown.
[0086] In an exemplary embodiment of the present disclosure, removing a portion of the first insulating layer 22 located at the bottom of the opening 201 (ie, step S130) may include steps S1 to S3, wherein:
[0087] S1 , forming a first protection layer 6 on the sidewall and bottom of the opening 201 having the first sacrificial layer 4 .
[0088] In an exemplary embodiment of the present disclosure, the material of the first protective layer 6 may be carbon, and the first protective layer 6 may be formed on the surface of the first sacrificial layer 4 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments of the present disclosure, forming the first protective layer 6 on the sidewall and bottom of the opening 201 having the first sacrificial layer 4 may include using a mixed gas of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8), and fluoromethane (CH3F) to form the first protective layer 6. In this process, the flow ratio of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8), and fluoromethane (CH3F) may be controlled so that the finally formed first protective layer 6 can cover the bottom of the opening 201. For example, the flow ratio of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8), and fluoromethane (CH3F) may be 1:1:1 to 3:3:1. For example, the flow ratio of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8) and fluoromethane (CH3F) can be 1:1:1 or 1:3:3 or 3:3:1. Of course, the flow ratio of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8) and fluoromethane (CH3F) can also be other ratios, which are not listed here. In one embodiment of the present disclosure, the structure after completing step S1 is as follows Fig. 9 shown.
[0089] S2 , etching the first protection layer 6 located at the bottom of the opening 201 and the film layer adjacent to the first protection layer 6 at the bottom of the opening 201 .
[0090] After the first protective layer 6 is deposited, the first protective layer 6 at the bottom of the opening 201 and the film layer adjacent to the first protective layer 6 (for example, the first sacrificial layer 4, the second insulating layer 3 or the first insulating layer 22) can be etched by dry etching. In one embodiment of the present disclosure, the structure after completing step S2 is as follows: Fig.10As shown. In this process, the first protective layer 6 located on the side wall of the opening 201 will also be etched (that is, the first protective layer 6 located on the side wall of the opening 201 can prevent the first sacrificial layer 4 on the side wall of the opening 201 from being consumed during the dry etching process. The first protective layer 6 is used to protect the first sacrificial layer 4 located on the side wall of the opening 201. The second insulating layer 3 on the side wall of the opening 201 can be doubly protected by the first sacrificial layer 4 and the first protective layer 6). However, since dry etching is anisotropic etching, the longitudinal etching speed is faster than the lateral etching speed. The first protective layer 6 at the bottom of the opening 201 will be etched first, and the consumption of the film layer on the side wall is less. In the subsequent etching process, the film layer consumed at the bottom of the opening 201 is the film layer adjacent to the first protective layer 6 (for example, the first sacrificial layer 4, the second insulating layer 3 or the first insulating layer 22). It should be noted that during the etching process, the damage to the first sacrificial layer 4 during the etching process can be controlled by controlling the etching time, thereby controlling the damage to the second insulating layer 3. The time can be obtained based on multiple preliminary tests.
[0091] S3, cleaning the opening 201 to remove the first protective layer 6 and residues in the etching process.
[0092] After the partial area of the first protective layer 6 located on the side wall of the opening 201 is etched, the first protective layer 6 may be damaged by pinholes, etc., so that its protective effect on the first sacrificial layer 4 is weakened. The opening 201 can be cleaned to remove the residues in the etching process and the first protective layer 6 that may be damaged. In the embodiment of the present disclosure, the structure after completing step S3 is as follows: Fig.11 As shown. Repeat step S1, and then re-form the first protective layer 6 on the surface of the first sacrificial layer 4, which is uniform and has no structural damage, and then repeat the above steps S2 and S3; that is, the above steps S1-S3 can be repeated. It should be noted that in the process of repeating steps S1-S3, etching can be gradually carried out through multiple cycles. In this process, due to the multiple protections of the deposited first protective layer 6 on the side wall, the first sacrificial layer 4 can be better prevented from being damaged.
[0093] In some embodiments of the present disclosure, in the process of removing the first protective layer 6 and the residues in the etching process, the cleaning gas can be reasonably selected to ensure that only the first protective layer 6 and the residues in the etching process can be removed during the cleaning process without damaging (or slightly damaging) other film layer structures (for example, the first sacrificial layer 4). The specific cleaning gas can be set according to the materials of the first protective layer 6, the first sacrificial layer 4 and the first insulating layer 22. As long as the first protective layer 6 and the residues in the etching process can be removed without damaging (or slightly damaging) the first sacrificial layer 4, the specific cleaning gas is not particularly limited here.
[0094] In an exemplary embodiment of the present disclosure, the above steps S1-S3 may be repeated for a preset number of times, and the preset number of times may be 3 to 20 times, for example, it may be 3 times, 5 times, 10 times, 15 times or 20 times. Of course, the preset number of times may also be other values, which are not listed here one by one. It should be noted that after repeating the above steps S1-S3 for multiple times, the first sacrificial layer 4 at the bottom of the opening 201 will be completely etched; if a second insulating layer 3 is formed at the bottom of the opening 201, the film layer adjacent to the first protective layer 6 at the bottom of the opening 201 in the subsequent repetition of steps S1-S3 will become the second insulating layer 3. After the second insulating layer 3 at the bottom of the opening 201 is completely etched, the film layer adjacent to the first protective layer 6 at the bottom of the opening 201 in the subsequent repetition of steps S1-S3 will become the first insulating layer 22. If there is no second insulating layer 3 at the bottom of the opening 201, the film layer adjacent to the first protective layer 6 at the bottom of the opening 201 in the subsequent repetition of steps S1-S3 will become the first insulating layer 22. In the embodiment of the present disclosure, the structure after repeating steps S1 to S3 multiple times is as follows Fig.12 shown.
[0095] In the present disclosure, after repeating steps S1 to S3 for a preset number of times, it can be considered that the first sacrificial layer 4 is thinned due to process wear, that is, after repeating steps S1 to S3 for a preset number of times, the protective effect of the first sacrificial layer 4 on the second insulating layer 3 is weakened. At this time, step S140 can be performed.
[0096] like Figure 4 As shown, in step S140 , a second sacrificial layer 5 is formed in the opening 201 having the first sacrificial layer 4 .
[0097] The second sacrificial layer 5 may at least cover the surface of the first sacrificial layer 4, so that the second insulating layer 3 is doubly protected by the second sacrificial layer 5 and the first sacrificial layer 4, thereby enhancing the protection of the second insulating layer 3 located on the side wall of the opening 201 during the subsequent etching process to form the groove 202, thereby reducing the probability of the second insulating layer 3 being damaged, which helps to improve the reliability of the device and the product yield. In the process of forming the second sacrificial layer 5, for the convenience of the process, the second sacrificial layer 5 can cover the bottom of the opening 201 at the same time. For example, the second sacrificial layer 5 can simultaneously cover the surface of the first sacrificial layer 4 on the side wall of the opening 201 and the surface of the first insulating layer 22 remaining at the bottom of the opening 201. In addition, when the first sacrificial layer 4 is also formed on the top of the stacked film layer 2, the second sacrificial layer 5 can also simultaneously cover the first sacrificial layer 4 located at the top of the stacked film layer 2. In the subsequent etching process to form the groove 202, the first sacrificial layer 4 located on the side wall of the opening 201 and the first sacrificial layer 4 located at the top of the stacked film layer 2 can be protected simultaneously by the second sacrificial layer 5. In the embodiment of the present disclosure, the structure after completing step S140 is as follows: Fig.13 shown.
[0098] In an exemplary embodiment of the present disclosure, the second sacrificial layer 5 may be a thin film with a relatively high density, for example, its density may be greater than or equal to 2.09 g / cm 3 . The material of the second sacrificial layer 5 may be polysilicon, silicon oxide, silicon nitride or carbon, etc. Taking the case where the material of the second sacrificial layer 5 is silicon oxide as an example, the second sacrificial layer 5 can be formed by chemical vapor deposition using the same thin film deposition machine as step S1. In this process, there is no need to move the substrate 1 formed with the stacked film layer 2, the first sacrificial layer 4 and the second insulating layer 3, and the second sacrificial layer 5 can be directly formed in the original position, thereby avoiding the time spent on moving the substrate 1 and replacing the machine, which helps to improve the process efficiency. At the same time, the second sacrificial layer 5 is formed by the atomic layer deposition process, which can ensure that the second sacrificial layer 5 can be evenly deposited at the bottom of the opening 201, and can enhance the protection of the bottom side wall of the opening 201.
[0099] like Figure 4 As shown, in step S150 , the first insulating layer 22 remaining at the bottom of the opening 201 is removed to form a groove 202 exposing the first conductive layer 21 .
[0100] In the process of removing the remaining first insulating layer 22 at the bottom of the opening 201, the second sacrificial layer 5 can be provided to strengthen the protection of the second insulating layer 3 on the side wall of the opening 201, so as to prevent the first sacrificial layer 4 from being thinned due to wear during the process, thereby weakening the protection effect of the second insulating layer 3. That is, the second insulating layer 3 on the side wall of the opening 201 can be doubly protected by the first sacrificial layer 4 and the second sacrificial layer 5. The damage to the second insulating layer 3 on the side wall of the opening 201 caused by the process of removing the remaining first insulating layer 22 at the bottom of the opening 201 can be reduced, and the impact of the damage to the second insulating layer 3 on the breakdown voltage and wafer acceptability test of the finally formed semiconductor device can be reduced, thereby improving the electrical performance of the product. In the embodiment of the present disclosure, the structure after completing step S150 is as follows: Fig.14 shown.
[0101] In the present disclosure, since the density of the second sacrificial layer 5 is relatively large, in the process of removing the first insulating layer 22 at the bottom of the opening 201, the second sacrificial layer 5 is not easily penetrated by plasma, and the probability of pinholes appearing inside it is small, which can reduce the probability of plasma passing through the second sacrificial layer 5 and then damaging the first sacrificial layer 4 and the second insulating layer 3 on the side wall of the opening 201, that is, the probability of structural damage to the second insulating layer 3 can be further reduced, which helps to ensure the insulation effect. At the same time, since the density of the second sacrificial layer 5 is relatively large, under the same protection effect, the thickness of the second sacrificial layer 5 can be thinner, that is, the thickness of the second sacrificial layer 5 attached to the side wall of the opening 201 is thinner, and the process opening 201 space during the etching process is relatively large, and the plasma can etch horizontally, and the area of the etched area at the bottom of the opening 201 is increased, so that the size of the bottom corner of the groove 202 formed in the end is reduced, and the charge is not easy to concentrate there, which helps to reduce leakage.
[0102] In an exemplary embodiment of the present disclosure, the first insulating layer 22 remaining at the bottom of the opening 201 is removed to form a groove 202 exposing the first conductive layer 21. (ie, step S150) may include steps S4 to S6, wherein:
[0103] S4 , forming a second protection layer (not shown in the figure) on the sidewall and bottom of the opening 201 having the second sacrificial layer 5 .
[0104] In an exemplary embodiment of the present disclosure, the material of the second protective layer may be carbon, silicon nitride or silicon oxide, and the second protective layer may be formed on the sidewall and bottom of the opening 201 having the second sacrificial layer 5 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In some embodiments of the present disclosure, the material of the second protective layer is carbon, and the specific formation process of the second protective layer is similar to the formation process of the first protective layer 6 in step S1. The specific formation details of the second protective layer may refer to step S1, which will not be repeated here.
[0105] S5 , etching the second protection layer located at the bottom of the opening 201 and the first insulating layer 22 located at the bottom of the opening 201 .
[0106] After the second protective layer is deposited, the second protective layer at the bottom of the opening 201 and the film layer adjacent to the second protective layer (for example, the first insulating layer 22) can be etched by dry etching. In this process, the second protective layer on the side wall of the opening 201 will also be etched (that is, the second protective layer on the side wall of the opening 201 can prevent the second sacrificial layer 5 on the side wall of the opening 201 from being consumed during the dry etching process, and the second protective layer is used to protect the second sacrificial layer 5 on the side wall of the opening 201. The second insulating layer 3 on the side wall of the opening 201 can be triple protected by the second protective layer, the first sacrificial layer 4 and the second sacrificial layer 5), but because the dry etching is anisotropic etching, the second protective layer at the bottom of the opening 201 will be etched first, and in the subsequent etching process, the film layer consumed at the bottom of the opening 201 is the first insulating layer 22 adjacent to the second protective layer.
[0107] S6, cleaning the opening 201 to remove the second protective layer and residues in the etching process.
[0108] Taking the material of the second protective layer as carbon as an example, the specific process of removing the second protective layer and the residues during the etching process is similar to the process of removing the second protective layer and the residues during the etching process in step S3. The details of removing the second protective layer and the residues during the etching process can be referred to step S3 and will not be repeated here.
[0109] It should be noted that after the partial area of the second protective layer located on the side wall of the opening 201 is etched, the protective effect of the second protective layer on the second sacrificial layer 5 is weakened, and the residues in the etching process can be removed, and then step S4 is repeated, and then the second protective layer with a stronger protective effect is re-formed on the surface of the second sacrificial layer 5, and then the above steps S5 and S6 are repeated. That is, the above steps S4-step S6 can be repeated until the first insulating layer 22 does not exist on the surface of the area of the first conductive layer 21 that is directly opposite to the bottom of the opening 201. It should be noted that after repeating the above steps S5-step S6 for multiple times, the second sacrificial layer 5 located at the bottom of the opening 201 will be completely etched, and the film layer etched in the subsequent repetition of steps S5-step S6 is the first insulating layer 22 located at the bottom of the opening 201.
[0110] In some embodiments of the present disclosure, in order to ensure that the finally formed groove 202 can completely expose the first conductive layer 21, and thus ensure the electrical contact performance between the first conductive layer 21 and the channel layer 7 subsequently formed in the groove 202, the finally formed groove 202 can be extended to the inside of the first conductive layer 21 during the process of repeating the above steps S4 to S6, that is, the first conductive layer 21 can be slightly overetched. In the process of etching the first conductive layer 21, the film layer adjacent to the protective layer is the first conductive layer 21.
[0111] In an exemplary embodiment of the present disclosure, after forming the trench 202, the method for manufacturing a semiconductor device of the present disclosure may further include:
[0112] Step S160 , removing the second sacrificial layer 5 and the first sacrificial layer 4 .
[0113] The second sacrificial layer 5 can be removed by a wet etching process. Taking the second sacrificial layer 5 as an example of a material of silicon oxide, an acidic solution can be used to remove the second sacrificial layer 5. For example, the acidic solution can be hydrofluoric acid, for example, it can be buffered hydrofluoric acid (BHF), hydrofluoric acid with a concentration of 49%, or dilute hydrofluoric acid (DHF). It should be noted that since the density of the second sacrificial layer 5 is relatively large and the film itself is relatively thin, it can be well removed with less residue. In the embodiment of the present disclosure, the structure after removing the second sacrificial layer 5 is as follows: Fig.15 shown.
[0114] After removing the second sacrificial layer 5, the etching solution can be switched, and the first sacrificial layer 4 can be removed by wet etching. Taking the material of the first sacrificial layer 4 as polysilicon as an example, the etching solution can be a tetramethylhydroxylamine solution. Of course, the first sacrificial layer 4 can also be removed by other solutions, as long as the first sacrificial layer 4 can be removed without damaging (or slightly damaging) the second insulating layer 3 and the first conductive layer 21 leaking out from the bottom of the groove 202. In the embodiment of the present disclosure, the structure after completing step S160 is as follows: Fig.16 shown.
[0115] In an exemplary embodiment of the present disclosure, after removing the second sacrificial layer 5 and the first sacrificial layer 4, the method for manufacturing a semiconductor device of the present disclosure may further include steps S210 to S230, wherein:
[0116] Step S210 , forming a channel layer 7 on the surface of the second insulating layer 3 located on the sidewall of the trench 202 .
[0117] The material of the channel layer 7 may be polysilicon, and the polysilicon layer may be formed in the groove 202 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. For the convenience of the process, the polysilicon layer may simultaneously cover the surface of the second insulating layer 3 on the sidewall of the groove 202, and may also simultaneously cover the bottom of the groove 202, that is, the polysilicon layer may be in contact with and connected to the first conductive layer 21, and the polysilicon layer may be doped by an ion implantation process to form the channel layer 7. It should be noted that the polysilicon layer may be n-type doped or p-type doped according to actual needs, and the doping type of the channel layer 7 formed after doping is not specifically limited here.
[0118] Step S220 , filling the trench 202 having the channel layer 7 with an insulating material to form an insulating dielectric layer 8 .
[0119] For example, the insulating material may be silicon oxide, and the insulating material may be filled in the trench 202 where the channel layer 7 is formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, thereby forming an insulating dielectric layer 8. The insulating dielectric layer 8 may fill the trench 202, and its surface away from the substrate 1 may be flush with the surface of the channel layer 7 away from the substrate 1. The channel layer 7 on two oppositely distributed sidewalls in the trench 202 may be insulated and isolated by the insulating dielectric layer 8.
[0120] Step S230 , forming a third conductive layer 9 on a side of the channel layer 7 away from the substrate 1 .
[0121] The material of the third conductive layer 9 may be a material with strong conductivity, for example, the material may be polysilicon or tungsten. The third conductive layer 9 may be formed on the surface of the channel layer 7 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The third conductive layer 9 may constitute a junction field effect transistor together with the first conductive layer 21, the second conductive layer 23, the second insulating layer 3 and the channel layer 7, wherein the first conductive layer 21 may serve as the source (or drain) of the junction field effect transistor, the second conductive layer 23 may serve as the gate of the junction field effect transistor, the second insulating layer 3 may serve as the gate oxide layer of the junction field effect transistor, the third conductive layer 9 may serve as the drain (or source) of the junction field effect transistor, and the channel layer 7 may serve as the channel region of the junction field effect transistor. In the embodiment of the present disclosure, the structure after completing step S230 is as follows. Fig.17 shown.
[0122] In some embodiments of the present disclosure, in the process of forming the third conductive layer 9, for the convenience of the process, the third conductive layer 9 can simultaneously cover the ends of the two channel layers 7 away from the substrate 1 and the surface of the insulating dielectric layer 8 away from the substrate 1, that is, the third conductive layer 9 can be connected between the channel layers 7 of the two transistors, that is, the two adjacently distributed transistors can share the same drain (or source). At the same time, in the embodiment of the present disclosure, the first conductive layer 21 is also connected between the channel layers 7 of the two transistors, that is, the two adjacently distributed transistors can also share the same source (or drain), which can improve the integration of the device and is conducive to the miniaturization design of the device. In addition, when the polysilicon layer simultaneously covers the surface of the second insulating layer 3 on the side wall of the groove 202 and the bottom of the groove 202, the channel layer 7 formed after doping the polysilicon layer also simultaneously covers the surface of the second insulating layer 3 on the side wall of the groove 202 and the bottom of the groove 202, that is, the channel layers 7 of two adjacent transistors are interconnected, which can further improve the product integration; at the same time, since the channel layers 7 of two adjacent transistors are interconnected, the current can flow more directly between the two transistors, reducing resistance and obstacles to current transmission, which can enhance the current conduction capability, improve the circuit working efficiency, and reduce the circuit energy consumption.
[0123] It should be noted that, although the steps of the method for manufacturing a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.
[0124] The embodiments of the present disclosure also provide a semiconductor device, which can be manufactured using the manufacturing method of the semiconductor device in any of the above embodiments. The specific details, formation process and beneficial effects have been described in detail in the embodiments of the corresponding semiconductor device manufacturing method, and will not be repeated here.
[0125] For example, the semiconductor device may be a junction field effect transistor, a dynamic random access memory or a static random access memory, etc. Of course, it may also be other storage devices, which are not listed here one by one.
[0126] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: A stacked film layer is formed on a substrate, wherein the stacked film layer comprises a first conductive layer, a first insulating layer, and a second conductive layer stacked in sequence along a vertical direction; an opening is formed in the stacked film layer, and the opening penetrates the second conductive layer in the vertical direction; forming a second insulating layer and a first sacrificial layer, wherein the second insulating layer at least covers the sidewalls of the opening, and the first sacrificial layer is located on the surface of the second insulating layer; removing a portion of the first insulating layer located at the bottom of the opening; forming a second sacrificial layer in the opening having the first sacrificial layer; The first insulating layer remaining at the bottom of the opening is removed to form a groove exposing the first conductive layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: Removing a portion of the first insulating layer located at the bottom of the opening comprises the following steps: Step S1, forming a first protective layer on the sidewall and bottom of the opening having the first sacrificial layer; Step S2, etching the first protective layer located at the bottom of the opening and the film layer adjacent to the first protective layer at the bottom of the opening; Step S3, cleaning the opening to remove the first protective layer and residues from the etching process; Repeat steps S1 to S3 for a preset number of times.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: The preset number of times is 3 to 20 times.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first sacrificial layer is polysilicon, silicon oxide or silicon nitride.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The density of the second sacrificial layer is greater than or equal to 2.09 g / cm 3 .
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the second sacrificial layer is polysilicon, silicon oxide, silicon nitride or carbon.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: Removing the first insulating layer remaining at the bottom of the opening to form a groove exposing the first conductive layer comprises the following steps: Step S4, forming a second protective layer on the sidewall and bottom of the opening having the second sacrificial layer; Step S5, etching the second protection layer located at the bottom of the opening and the first insulating layer located at the bottom of the opening; Step S6, cleaning the opening to remove the second protective layer and residues from the etching process; Step S4 to step S6 are repeated until the first insulating layer does not exist on the surface of the region of the first conductive layer directly facing the bottom of the opening.
8. The method for manufacturing a semiconductor device according to claim 2, wherein: The material of the first protective layer is carbon.
9. The method for manufacturing a semiconductor device according to claim 7, wherein: The material of the second protection layer is carbon, silicon nitride or silicon oxide.
10. The method for manufacturing a semiconductor device according to claim 2, wherein: Forming a first protective layer on the sidewall and bottom of the opening having the first sacrificial layer comprises: The first protective layer is formed by a mixed gas of perfluorobutadiene (C4F6), perfluorocyclobutane (C4F8) and fluoromethane (CH3F), and the flow ratio of the perfluorobutadiene (C4F6), the perfluorocyclobutane (C4F8) and the fluoromethane (CH3F) is 1:1:1 to 3:3:
1.
11. The method for manufacturing a semiconductor device according to any one of claims 1 to 10, characterized in that: After forming the trench, the method for manufacturing the semiconductor device further includes: The second sacrificial layer and the first sacrificial layer are removed.
12. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The stacked film layer further includes a third insulating layer, the third insulating layer is located on a side of the second conductive layer away from the substrate, the opening penetrates the third insulating layer and the second conductive layer at the same time, the second insulating layer is also formed on a surface of a side wall of the opening surrounded by the third insulating layer, and after removing the second sacrificial layer and the first sacrificial layer, the method for manufacturing the semiconductor device further includes: forming a channel layer on a surface of the second insulating layer located on a sidewall of the trench; Filling the trench having the channel layer with an insulating material to form an insulating dielectric layer; A third conductive layer is formed on a side of the channel layer away from the substrate.
13. A semiconductor device, characterized in that: The semiconductor device is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1 to 12.