Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a semiconductor structure, a bottom dielectric layer and a field plate structure, the semiconductor structure comprises a semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, the semiconductor layer comprises a cellular region and a terminal region adjacent to the cellular region, and the gate structure is located on the upper surface of the terminal region. A source region and a drain region of the device are positioned on the upper surface layers of the semiconductor layers on two opposite sides of the gate structure; the bottom dielectric layer covers the upper surface of the semiconductor structure; the field plate structure is located on the upper surface of the bottom dielectric layer on the side, close to the drain region, of the gate structure, the field plate structure at least comprises an optimized field plate, and in the direction from the source region to the drain region, the size of the optimized field plate above the cellular region is larger than that of the optimized field plate above the terminal region. According to the invention, the optimized field plate is arranged in the field plate structure, so that the breakdown voltage of the device is improved, and the robustness of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor device and a preparation method thereof. Background Art

[0002] The cell region and terminal region of the RF-LDMOS device usually provide the main areas for the device to withstand breakdown performance, such as Figure 1 and Figure 2 As shown, they are schematic diagrams of the cross-sectional structure of the RF-LDMOS device and schematic diagrams of the arrangement of the top surface parts of the RF-LDMOS device, including substrate 01, cell region 011, terminal region 012, well region 013, drift region 014, source region 015, drain region 016, source contact region 017, gate structure 02, gate oxide layer 021, gate polysilicon layer 022, first metal silicide layer 023, second metal silicide layer 024, third metal silicide layer 025, first dielectric layer 03, second dielectric layer 031, interlayer dielectric layer 032, first field plate 04 and second field plate 041. The cell region is formed by reasonably designing the field plate parameters. , the doping concentration and length of the drift region, the doping concentration and thickness of the epitaxial layer on the surface of the substrate and other parameters can ensure that the device breakdown voltage meets the requirements, and at the same time can ensure that the breakdown position occurs in the body, thereby improving the robustness of the device; the terminal region is provided with the required breakdown voltage of the device by the epitaxial layer on the surface of the substrate and the drift region, while in the intersection area of ​​the cell region and the terminal region, due to the influence of the cell region, the electric field lines are concentrated in the corners of the drain region close to the gate structure and the terminal region, resulting in the breakdown voltage of the terminal region being lower than the breakdown voltage of the cell region, thereby making the breakdown voltage of the device relatively low, and the breakdown of the device is easy to occur in the terminal region and on the surface of the device, which greatly reduces the robustness of the device.

[0003] Therefore, there is an urgent need to find a semiconductor device that can increase the breakdown voltage of the device and improve the robustness of the device. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to solve the problems in the prior art that the terminal region of the semiconductor device has a low breakdown voltage and is prone to breakdown, and the device has poor robustness.

[0005] To achieve the above object and other related objects, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor structure, comprising a semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, wherein the semiconductor layer comprises a cell region and a terminal region adjacent to the cell region, and a source region and a drain region of the device are located on the upper surface of the semiconductor layer on opposite sides of the gate structure;

[0007] a bottom dielectric layer covering the upper surface of the semiconductor structure;

[0008] A field plate structure is located on the upper surface of the bottom dielectric layer on the side of the gate structure close to the drain region, and the field plate structure includes at least one optimized field plate. In the direction from the source region to the drain region, the size of the optimized field plate above the cell region is larger than the size of the optimized field plate above the terminal region.

[0009] Optionally, the semiconductor layer also includes a first conductive type drift region and a second conductive type well region, the doping type of the source region and the drain region is the same as the doping type of the drift region, the source region is located on the upper surface of the well region, the drain region is located on the upper surface of the drift region in the cell region, and the gate structure is located on the upper surface of the semiconductor layer between the source region and the drift region.

[0010] Optionally, a second conductive type source contact region is further provided in the semiconductor layer and is located on an upper surface of the well region, and a side of the source contact region close to the source region is adjacent to the source region.

[0011] Optionally, the semiconductor layer also includes a second conductive type substrate and a second conductive type epitaxial layer stacked in sequence, the drift region and the well region are located on the upper surface layer of the epitaxial layer, and a second conductive type substrate contact region is also provided in the semiconductor layer, and the substrate contact region extends from the surface of the epitaxial layer at least to the top surface of the substrate.

[0012] Optionally, the gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, and a size of the gate dielectric layer is not smaller than a size of the gate conductive layer.

[0013] Optionally, a first contact layer and a second contact layer are further provided in the semiconductor structure, the first contact layer covers the upper surface of the source region, and the second contact layer covers the upper surface of the drain region.

[0014] Optionally, the field plate structure also includes at least one first stacked structure located between the underlying dielectric layer and the optimized field plate, the first stacked structure including a lower field plate and a first isolation layer stacked in sequence, the optimized field plate being located on an upper surface of the first isolation layer adjacent to the optimized field plate, an end of the optimized field plate close to the gate structure being located directly above a portion of the lower field plate adjacent to the optimized field plate, an end of the lower field plate close to the gate structure adjacent to the underlying dielectric layer being located directly above a portion of the gate structure, and the lower field plate being located only above the cell region.

[0015] Optionally, the field plate structure includes multiple layers of the first stacked structures, and in two adjacent layers of the first stacked structures, one end of the lower field plate of the upper layer of the first stacked structure close to the gate structure is located directly above a portion of the lower field plate of the lower layer of the first stacked structure.

[0016] Optionally, different lower field plates have different sizes in the arrangement direction of the drift region and the well region; different lower field plates have different thicknesses; and different first isolation layers have different thicknesses.

[0017] Optionally, the thickness of the first isolation layer is different from the thickness of the bottom dielectric layer; the thickness of the lower field plate is different from the thickness of the optimized field plate.

[0018] Optionally, the field plate structure also includes at least one second stacked structure located above the optimized field plate, the second stacked structure includes a second isolation layer and an upper field plate stacked in sequence, the second isolation layer covers the upper surface of the optimized field plate, and an end of the upper field plate adjacent to the optimized field plate close to the gate structure is located directly above a portion of the optimized field plate.

[0019] Optionally, the field plate structure includes a second stacked structure, and in the direction from the source region to the drain region, the size of the upper field plate above the cell region is not less than the size of the upper field plate above the terminal region.

[0020] Optionally, the field plate structure includes multiple layers of the second stacked structures, and in two adjacent layers of the second stacked structures, one end of the upper field plate of the upper layer of the second stacked structure close to the gate structure is located directly above a portion of the lower field plate of the lower layer of the second stacked structure.

[0021] Optionally, in the direction from the source region to the drain region, a size of a portion above the cell region in the upper field plate of at least one layer of the second stacked structure is not less than a size of a portion above the terminal region.

[0022] Optionally, the thicknesses of different second isolation layers are not completely the same; the thicknesses of different upper field plates are not completely the same; and the sizes of different upper field plates in the arrangement direction of the drift region and the well region are different.

[0023] Optionally, in the direction from the source region to the drain region, a size of the field plate adjacent to the gate structure in the field plate structure is not less than 0.35 μm.

[0024] The present invention also provides a method for preparing a semiconductor device, comprising the following steps:

[0025] A semiconductor structure is provided, comprising a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, wherein the semiconductor layer comprises a cell region and a terminal region adjacent to the cell region, and a source region and a drain region of the device are located on an upper surface layer of the semiconductor layer at opposite sides of the gate structure;

[0026] A bottom dielectric layer is formed covering the upper surface of the semiconductor structure, and a field plate structure is formed on the upper surface of the bottom dielectric layer and is located on the side of the gate structure close to the drain region, wherein the field plate structure includes at least one optimized field plate, and in the direction from the source region to the drain region, the size of the portion above the cell region in the optimized field plate is larger than the size of the portion above the terminal region.

[0027] As described above, the semiconductor device and preparation method of the present invention provide an optimized field plate in the field plate structure, and in the direction from the source region to the drain region, by making the size of the portion above the cell region in the optimized field plate larger than the size of the portion above the terminal region, the electric field lines in the terminal region of the device are then more directed toward the gate of the device and the optimized field plate, thereby improving the electric field distribution in the terminal region, avoiding the aggregation of electric field lines in the boundary area between the cell region and the terminal region to reduce the breakdown voltage of the terminal region, increasing the breakdown voltage at the terminal region of the device and making it greater than the breakdown voltage of the cell region, and not affecting the breakdown voltage of the cell region of the device, ensuring that the breakdown of the device occurs in the body of the cell region, avoiding the voltage breakdown position of the device occurring on the surface of the device, improving the robustness of the device, and improving the breakdown voltage and reliability of the device, while not changing the device manufacturing steps, and having a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic cross-sectional structure diagram of an RF-LDMOS device.

[0029] Figure 2 Shown is a schematic diagram of the arrangement of various parts on the top surface of the RF-LDMOS device.

[0030] Figure 3 The process flow chart of the method for manufacturing a semiconductor device of the present invention is shown.

[0031] Figure 4 It is a schematic diagram showing the cross-sectional structure after forming an epitaxial layer in the method for preparing a semiconductor device of the present invention.

[0032] Figure 5 It is a schematic diagram of the top surface structure after forming the epitaxial layer in the method for preparing the semiconductor device of the present invention.

[0033] Figure 6 It is a schematic diagram showing the cross-sectional structure after forming the substrate contact region in the method for preparing the semiconductor device of the present invention.

[0034] Figure 7 It is a schematic diagram showing the cross-sectional structure of the method for preparing a semiconductor device of the present invention after forming an isolation structure.

[0035] Figure 8 It is a schematic diagram of the cross-sectional structure after forming the gate dielectric layer in the method for preparing the semiconductor device of the present invention.

[0036] Fig. 9 It is a schematic diagram showing the cross-sectional structure after forming the third contact layer in the method for preparing a semiconductor device of the present invention.

[0037] Fig.10 It is a schematic diagram showing the cross-sectional structure after forming the drift region in the method for preparing the semiconductor device of the present invention.

[0038] Fig.11 It is a schematic diagram showing the cross-sectional structure after forming the well region in the method for manufacturing the semiconductor device of the present invention.

[0039] Fig.12 It is a schematic diagram showing the cross-sectional structure after forming the source contact region in the method for manufacturing the semiconductor device of the present invention.

[0040] Fig.13 It is a schematic diagram showing the cross-sectional structure after forming the first contact layer and the second contact layer in the method for preparing the semiconductor device of the present invention.

[0041] Fig.14 It is a schematic diagram of the cross-sectional structure after forming an optimized field plate in the method for preparing a semiconductor device of the present invention.

[0042] Fig.15 It is a schematic diagram showing the cross-sectional structure after forming the upper field plate in the method for preparing the semiconductor device of the present invention.

[0043] Fig.16 It is a schematic diagram showing the cross-sectional structure of a cell region after forming an interlayer dielectric layer in the method for preparing a semiconductor device of the present invention.

[0044] Fig.17 It is a schematic cross-sectional structure diagram of a terminal region after forming an interlayer dielectric layer in the method for preparing a semiconductor device of the present invention.

[0045] Fig.18 The schematic diagram shows the cross-sectional structure of the cell region after the first plug and the second plug are formed in the method for manufacturing the semiconductor device of the present invention.

[0046] Fig.19 The cross-sectional structure schematic diagram shows the terminal region portion after the first plug and the second plug are formed in the method for manufacturing a semiconductor device of the present invention.

[0047] Fig. 20It is a schematic diagram showing the cross-sectional structure of a cell region after forming a source electrode and a drain electrode in the method for manufacturing a semiconductor device of the present invention.

[0048] Fig.21 It is a schematic cross-sectional structure diagram of the terminal region after the source and drain are formed in the method for manufacturing the semiconductor device of the present invention.

[0049] Fig. 22 It is a schematic diagram showing the cross-sectional structure of a cell region after forming an insulating layer in the method for preparing a semiconductor device of the present invention.

[0050] Fig.23 It is a schematic diagram showing the cross-sectional structure of the terminal region after the insulating layer is formed in the method for preparing a semiconductor device of the present invention.

[0051] Fig.24 It is a schematic cross-sectional structure diagram of a cell region after forming a fourth plug and a fifth plug in the method for manufacturing a semiconductor device of the present invention.

[0052] Fig.25 The schematic diagram shows the cross-sectional structure of the terminal region after the fourth plug and the fifth plug are formed in the method for manufacturing the semiconductor device of the present invention.

[0053] Fig.26 It is a schematic diagram showing the cross-sectional structure of a cell region after forming a source pad and a drain pad in the method for manufacturing a semiconductor device of the present invention.

[0054] Fig. 27 The cross-sectional structure schematic diagram of the terminal region after the source pad and the drain pad are formed in the method for manufacturing the semiconductor device of the present invention is shown.

[0055] Fig.28 It is a schematic diagram showing the cross-sectional structure of a cell region after forming a passivation layer in the method for preparing a semiconductor device of the present invention.

[0056] Fig.29 It is a schematic diagram showing the cross-sectional structure of the terminal region after forming the passivation layer in the method for preparing the semiconductor device of the present invention.

[0057] Fig.30 It is a schematic diagram showing the cross-sectional structure of a cell region after forming a back electrode layer in the method for preparing a semiconductor device of the present invention.

[0058] Fig.31 It is a schematic cross-sectional structure diagram of the terminal region after forming the back electrode layer in the method for preparing the semiconductor device of the present invention.

[0059] Fig.32It is a schematic diagram showing the arrangement of the top surface parts after the back electrode layer is formed in the method for preparing the semiconductor device of the present invention.

[0060] Fig.33 Display as Fig.30 Devices and Figure 1 Statistical table of breakdown voltage and breakdown position of devices in the figure.

[0061] Description of Figure Numbers

[0062] 01 Substrate

[0063] 011 Cell Area

[0064] 012 Terminal Area

[0065] 013 Well region

[0066] 014 Drift Zone

[0067] 015 Source Area

[0068] 016 Leakage Area

[0069] 017 Source contact area

[0070] 02 Gate structure

[0071] 021 Gate Oxide Layer

[0072] 022 Gate polysilicon layer

[0073] 023 First metal silicide layer

[0074] 024 Second metal silicide layer

[0075] 025 Third metal silicide layer

[0076] 03 First dielectric layer

[0077] 031 Second dielectric layer

[0078] 032 Interlayer dielectric layer

[0079] 04 First board

[0080] 041 The Second Board

[0081] 1 Semiconductor layer

[0082] 10 Substrate

[0083] 11 Cell area

[0084] 12 Terminal Area

[0085] 13 Epitaxial layer

[0086] 14 Drift Zone

[0087] 15 Well region

[0088] 16 Source area

[0089] 17 Drain area

[0090] 18 Source contact area

[0091] 19 Substrate contact area

[0092] 191 Isolation Structure

[0093] 2 Gate structure

[0094] 20 Semiconductor Structure

[0095] 21. Gate dielectric layer

[0096] 22. Gate conductive layer

[0097] 23 First contact layer

[0098] 24 Second contact layer

[0099] 25 Third contact layer

[0100] 3 Bottom dielectric layer

[0101] 4 Field plate structure

[0102] 41 Optimized field plate

[0103] 42 first stacking structure

[0104] 421 Second Isolation Layer

[0105] 422 Board

[0106] 43 Interlayer dielectric layer

[0107] 5 Source

[0108] 51 First Plug

[0109] 52 Source interconnect layer

[0110] 53 Fourth Plug

[0111] 54 Source pad

[0112] 6 Drain

[0113] 61 Second plug

[0114] 62 Drain interconnect layer

[0115] 63 Fifth Plug

[0116] 64 Drain pad

[0117] 7 Insulation layer

[0118] 8 Passivation layer

[0119] 9 Back electrode layer DETAILED DESCRIPTION

[0120] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0121] See also Figures 3 to 33 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0122] Embodiment 1

[0123] This embodiment provides a method for preparing a semiconductor device, such as Figure 3 FIG. 1 is a process flow chart of the method for preparing the semiconductor device, comprising the following steps:

[0124] S1: providing a semiconductor structure including a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, wherein the semiconductor layer includes a cell region and a terminal region adjacent to the cell region, and a source region and a drain region of the device are located on an upper surface layer of the semiconductor layer on opposite sides of the gate structure;

[0125] S2: forming an underlying dielectric layer covering the upper surface of the semiconductor structure, and forming a field plate structure on the upper surface of the underlying dielectric layer and located on the side of the gate structure close to the drain region, wherein the field plate structure includes at least one optimized field plate, and in the direction from the source region to the drain region, the size of the optimized field plate above the cell region is larger than the size of the optimized field plate above the terminal region.

[0126] See also Figures 4 to 13 , perform step S1: provide a semiconductor structure 20 including a semiconductor layer 1 and a gate structure 2 located on the upper surface of the semiconductor layer 1, the semiconductor layer 1 includes a cell region 11 and a terminal region 12 adjacent to the cell region 11, and the source region 16 and the drain region 17 of the device are located on the upper surface of the semiconductor layer 1 on opposite sides of the gate structure 2.

[0127] As an example, the semiconductor layer 1 also includes a first conductive type drift region 14, a second conductive type well region 15, and a second conductive type substrate 10 and a second conductive type epitaxial layer 13 stacked in sequence. The doping type of the source region 16 and the drain region 17 is the same as the doping type of the drift region 14. The drift region 14 and the well region 15 are located on the upper surface layer of the epitaxial layer 13, the source region 16 is located on the upper surface layer of the well region 15, the drain region 17 is located on the upper surface layer of the drift region 14 in the cell region 11, and the gate structure 2 is located on the upper surface of the semiconductor layer 1 between the source region 16 and the drift region 14 (that is, the gate structure 2 is located on the upper surface of the epitaxial layer 13 between the source region 16 and the drift region 14).

[0128] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0129] Specifically, Figure 4 and Figure 5 As shown, they are respectively a schematic diagram of the cross-sectional structure after the epitaxial layer 13 is formed and a schematic diagram of the top surface structure after the epitaxial layer 13 is formed. The method of forming the epitaxial layer 13 on the upper surface of the substrate 10 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0130] Specifically, the substrate 10 is usually a process platform for manufacturing devices. Under the condition of ensuring device performance, the thickness, size and shape of the substrate 10 can be selected according to actual conditions; the thickness of the epitaxial layer 13 can be selected according to actual conditions. In this embodiment, the thickness of the epitaxial layer 13 is 5 μm, and the thickness of the substrate 10 is 1 mm.

[0131] Specifically, the epitaxial layer 13 has a high resistance characteristic, and the substrate 10 below the epitaxial layer 13 has a low resistance characteristic, that is, the doping concentration of the epitaxial layer 13 is lower than the doping concentration of the substrate 10 .

[0132] Specifically, the cell region 11 is used to form the cell structure of the device, and the terminal region 12 is used to make the terminal structure of the device. While ensuring the performance of the device, the size and shape of the cell region 11 in the semiconductor layer 1 can be selected according to actual conditions; the size and shape of the terminal region 12 can be selected according to actual conditions.

[0133] As an example, Figure 6 , which is a schematic diagram of the cross-sectional structure after the substrate contact region 19 is formed, a second conductive type substrate contact region 19 is also formed in the semiconductor layer 1 , and the substrate contact region 19 extends from the upper surface of the epitaxial layer 13 at least to the top surface of the substrate 10 .

[0134] Specifically, the substrate contact region 19 is used to lead the source of the device to the back side of the device to reduce the source parasitic inductance of the device. At the same time, the substrate contact region 19 is a heavily doped region to achieve good interconnection with the low-resistance substrate 10 while activating the substrate contact region 19 through subsequent annealing.

[0135] Specifically, the method for forming the substrate contact region 19 includes ion implantation or other suitable methods. In this embodiment, high-energy boron ions are implanted into the region corresponding to the substrate contact region 19 in the epitaxial layer 13, and then a high-temperature well-driving process is performed to activate the doped region after the boron ions are doped and form the substrate contact region 19 penetrating the epitaxial layer 13.

[0136] Specifically, Figure 7 , which is a schematic diagram of the cross-sectional structure after the isolation structure 191 is formed, an isolation structure 191 for defining the active area of ​​the device is also formed in the epitaxial layer 13, and the substrate contact region 19 is located in the active area of ​​the device.

[0137] Specifically, the isolation structure 191 may be a local oxidation isolation structure or a shallow trench isolation structure. Preferably, a thick local oxidation isolation layer is formed in the epitaxial layer 13 by a wet oxidation process as the isolation structure 191 .

[0138] As an example, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 which are stacked in sequence, and a size of the gate dielectric layer 21 is not smaller than a size of the gate conductive layer 22 .

[0139] Specifically, Figure 8 , which is a schematic diagram of a cross-sectional structure after forming a gate dielectric layer 21, the gate dielectric layer 21 covers the upper surface of the epitaxial layer 13 in the active area, and the method of forming the gate dielectric layer 21 includes chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods. In this embodiment, a dry oxygen oxidation process is used to form the gate dielectric layer 21 on the upper surface of the epitaxial layer 13 in the active area.

[0140] Specifically, forming the gate conductive layer 22 includes the following steps: forming a gate conductive material layer on the upper surface of the gate dielectric layer 21 ; and etching the gate conductive material layer to obtain the gate conductive layer 22 .

[0141] Specifically, the method of forming the gate conductive material layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0142] Specifically, the method of etching the gate conductive material layer includes dry etching, wet etching or other suitable methods.

[0143] Specifically, Fig. 9As shown, it is a schematic diagram of the cross-sectional structure after the third contact layer 25 is formed. A third contact layer 25 is also formed on the upper surface of the gate conductive layer 22. The third contact layer 25 is used to reduce the contact resistance between the gate conductive layer 22 and the subsequently formed gate, thereby improving the RF performance of the device. The method for forming the third contact layer 25 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0144] Specifically, Fig.10 As shown, it is a schematic diagram of the cross-sectional structure after the drift region 14 is formed. The drift region 14 is used to ensure the breakdown voltage of the device so that the device can meet the requirements of the corresponding application scenario. The method of forming the drift region 14 includes ion implantation or other suitable methods. In this embodiment, the gate self-alignment process is adopted and the upper surface layer of the epitaxial layer 13 on the side of the gate structure 2 away from the substrate contact region 19 is doped with phosphorus ions through a light drain doping ion implantation (LDD) process, and the doped structure is activated at high temperature and pushed to obtain the drift region 14.

[0145] Specifically, Fig.11 As shown, it is a schematic diagram of the cross-sectional structure after the well region 15 is formed. The well region 15 is used to provide the device with a threshold voltage that meets the requirements. The threshold voltage of the device is regulated by adjusting the doping concentration of the well region 15. At the same time, the well region 15 and the drift region 14 work together to limit the electric field strength of the gate structure 2 away from the substrate contact region 19 (i.e., the region between the gate structure 2 and the drain region formed subsequently), thereby controlling the hot carrier effect in the device and improving the reliability of the device.

[0146] Specifically, the method for forming the well region 15 includes ion implantation or other suitable methods. In this embodiment, a gate self-alignment process is adopted and the upper surface layer of the epitaxial layer 13 on the side of the gate structure 2 close to the substrate contact region 19 is doped with boron ions by ion implantation, and the doped structure is activated at high temperature and pushed to obtain the well region 15, and the well region 15 extends at least to the bottom of the gate conductive layer 22.

[0147] Specifically, the source region 16 is spaced apart from the sidewall of the well region 15 close to the drift region 14 by a preset distance, and the method for forming the source region 16 includes ion implantation or other suitable methods; the method for forming the drain region 17 includes ion implantation or other suitable methods. In this embodiment, an ion implantation process is adopted to implant As ions into the region in the epitaxial layer 13 corresponding to the source region 16 and the drain region 17, and high temperature annealing is performed after the ion implantation is completed, so as to simultaneously form a heavily doped N-type source region 16 and a heavily doped N-type drain region 17.

[0148] Specifically, the gate conductive layer 22 is located above the region between the source region 16 and the drift region 14 , and in the direction from the source region 16 to the drain region 17 , both ends of the gate conductive layer 22 extend above the source region 16 and the drift region 14 , respectively.

[0149] Specifically, the substrate contact region 19 is located at one end of the well region 15 away from the drift region 14 , and may be adjacent to the well region 15 or spaced apart from the well region 15 .

[0150] As an example, Fig.12 , which is a schematic diagram of the cross-sectional structure after the source contact region 18 is formed, a second conductive type source contact region 18 is also formed in the semiconductor layer 1 and is located on the upper surface of the well region 15 , and the source contact region 18 is adjacent to the source region 16 on one side thereof.

[0151] Specifically, when the substrate contact region 19 is adjacent to the well region 15 (the end away from the drift region 14), the substrate contact region 19 may be adjacent to the source contact region 18 (the side away from the source region 16), or may be spaced apart from the source contact region 18. In the present embodiment, the substrate contact region 19 is adjacent to the well region 15 (the end away from the drift region 14) and adjacent to the source contact region 18 (the side away from the source region 16).

[0152] As an example, Fig.13 , which is a schematic diagram of the cross-sectional structure after forming the first contact layer 23 and the second contact layer 24 , the first contact layer 23 and the second contact layer 24 are also formed in the semiconductor structure 20 , the first contact layer 23 covers the upper surface of the source region 16 , and the second contact layer 24 covers the upper surface of the drain region 17 .

[0153] Specifically, the first contact layer 23 also covers the upper surfaces of the substrate contact region 19 and the source contact region 18. The formation of the first contact layer 23 and the second contact layer 24 includes the following steps: etching the gate dielectric layer 21 on the upper surface of the epitaxial layer 13 after the source region 16 and the drain region 17 are formed to expose the substrate contact region 19, the source contact region 18, the source region 16 and the drain region 17; forming a metal layer covering the exposed surfaces of the substrate contact region 19, the source contact region 18, the source region 16 and the drain region 17, and annealing to form an alloy between the metal layer and silicon at a high temperature, thereby obtaining a metal silicide layer as the first contact layer 23 and the second contact layer 24.

[0154] Specifically, by forming the first contact layer 23 and the second contact layer 24 on the exposed surfaces of the source region 16 and the drain region 17 , the contact resistance between the subsequently formed source and drain and the corresponding source region 16 and drain region 17 can be reduced.

[0155] Specifically, the material of the metal layer includes Ti, Co, Ni or other suitable metal materials, and its formation process is a commonly used metal deposition process, which will not be described in detail here. In this embodiment, the metal deposited on the exposed surface of the source region 16 and the drain region 17 is Ti. After high-temperature annealing, Ti reacts with silicon on the surface of the source region 16 and the drain region 17 to form a TiSi alloy.

[0156] Specifically, after forming the metal layer covering the exposed surfaces of the substrate contact region 19, the source contact region 18, the source region 16 and the drain region 17, the annealing temperature and annealing time are related to the material of the corresponding metal layer and are not limited here.

[0157] Specifically, after forming the first contact layer 23 and the second contact layer 24 and before forming the bottom dielectric layer 3, a step of removing the unreacted metal layer is also included.

[0158] Specifically, the method of removing the unreacted metal layer includes dry etching, wet etching or other suitable methods.

[0159] See also Figures 14 to 32 , perform step S2: form an underlying dielectric layer 3 covering the upper surface of the semiconductor structure 20, and form a field plate structure 4 on the upper surface of the underlying dielectric layer 3 and located on the side of the gate structure 2 close to the drain region 17, the field plate structure 4 includes at least one optimized field plate 41, and in the direction from the source region 16 to the drain region 17, the size of the optimized field plate 41 above the cell region 11 is larger than the size of the optimized field plate 41 above the terminal region 12.

[0160] Specifically, the method of forming the bottom dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0161] Specifically, the material of the bottom dielectric layer 3 includes a silicon oxide layer, a silicon nitride layer, an aluminum nitride layer or other suitable dielectric material layers. In this embodiment, a silicon oxide layer is used as the bottom dielectric layer 3 .

[0162] Specifically, Fig.14 , which is a schematic diagram of the cross-sectional structure after the optimized field plate 41 is formed. The formation of the optimized field plate 41 includes the following steps: forming an optimized field plate material layer above the bottom dielectric layer 3; and etching the optimized field plate material layer to obtain the optimized field plate 41.

[0163] Specifically, the method of forming the optimized field plate material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0164] Specifically, the method of etching the optimized field plate material layer includes dry etching, wet etching or other suitable methods.

[0165] Specifically, only one optimized field plate 41 is provided in the field plate structure 4 as the field plate of the device, and one end of the optimized field plate 41 close to the gate structure 2 is located directly above the gate structure 2 .

[0166] As an example, in the direction from the source region 16 to the drain region 17 , the difference between the size of the portion above the cell region 11 and the size of the portion above the terminal region 12 in the optimized field plate 41 is not less than 0.1 μm.

[0167] Specifically, while ensuring device performance, along the direction from the source region 16 to the drain region 17 , the difference between the size of the portion above the cell region 11 and the size of the portion above the terminal region 12 in the optimized field plate 41 may also be other suitable differences.

[0168] As an example, the field plate structure 4 also includes at least one first stacking structure (not shown in the figure) located between the underlying dielectric layer 3 and the optimized field plate 41, the first stacking structure includes a lower field plate and a first isolation layer stacked in sequence, the optimized field plate 41 is located on the upper surface of the first isolation layer, the end of the optimized field plate 41 close to the gate structure 2 is located directly above the lower field plate, the end of the lower field plate adjacent to the underlying dielectric layer 3 close to the gate structure 2 is located directly above the gate structure 2, and the lower field plate is only located above the cell region 11.

[0169] As an example, the thickness of the first isolation layer is different from the thickness of the bottom dielectric layer 3. Under the condition of ensuring the performance of the device, the thickness of the first isolation layer can also be the same as the thickness of the bottom dielectric layer 3; the material of the first isolation layer can be the same as that of the bottom dielectric layer 3, or different.

[0170] As an example, the thickness of the lower field plate is different from that of the optimized field plate 41. Under the condition of ensuring device performance, the thickness of the lower field plate can also be the same as that of the optimized field plate 41; the material of the optimized field plate 41 can be the same as or different from that of the lower field plate.

[0171] Specifically, forming a first stacking structure on the upper surface of the bottom dielectric layer 3 includes the following steps: forming a lower field plate material layer on the upper surface of the bottom dielectric layer 3, and etching the lower field plate material layer to obtain a lower field plate; forming a first isolation layer covering the exposed surface of the lower field plate and the exposed upper surface of the bottom dielectric layer 3.

[0172] Specifically, the method of forming the lower field plate material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of etching the lower field plate material layer includes dry etching, wet etching or other suitable methods; the method of forming the first isolation layer includes physical vapor deposition, chemical vapor deposition or other suitable methods.

[0173] As an example, the field plate structure 4 includes multiple layers of first stacked structures. In two adjacent first stacked structures, one end of the lower field plate of the upper first stacked structure close to the gate structure 2 is located directly above a portion of the lower field plate of the lower first stacked structure.

[0174] Specifically, when the field plate structure 4 includes a multi-layer first stacking structure, the steps of forming a lower field plate material layer, etching the lower field plate material layer and forming a first isolation layer 4 are repeated in sequence until the number of layers of the first stacking structure between the underlying dielectric layer 3 and the optimized field plate 41 reaches a preset number of layers, and after the lower field plate located on the upper surface of the underlying dielectric layer 3 is formed, the lower field plate material layers repeatedly formed thereafter are all formed on the upper surface of the corresponding first isolation layer.

[0175] As an example, different lower field plates have different sizes in the arrangement direction of the drift region 14 and the well region 15 , that is, when the field plate structure 4 includes a multi-layer first stacking structure, different lower field plates have different sizes in the arrangement direction of the drift region 14 and the well region 15 .

[0176] Specifically, while ensuring device performance, the sizes of different lower field plates in the arrangement direction of the drift region 14 and the well region 15 may be the same, or partially the same. Preferably, the sizes of the lower field plates in the field plate structure 4 in the arrangement direction of the drift region 14 and the well region 15 are the same.

[0177] As an example, different lower field plates have different thicknesses, that is, when the field plate structure 4 includes multiple layers of the first stacked structure, the thicknesses of different lower field plates are different.

[0178] Specifically, under the condition of ensuring the device performance, the thicknesses of different lower field plates may be the same, or partially the same. Preferably, the thicknesses of the lower field plates in the field plate structure 4 are the same.

[0179] As an example, different first isolation layers have different thicknesses, that is, when the field plate structure 4 includes a multi-layer first stacked structure, different first isolation layers have different thicknesses.

[0180] Specifically, under the condition of ensuring the device performance, the thicknesses of different first isolation layers may be the same, or partially the same. Preferably, the thicknesses of the first isolation layers in the field plate structure 4 are the same.

[0181] As an example, Fig.15 As shown, it is a schematic diagram of the cross-sectional structure after the second stacking structure 42 is formed above the optimized field plate 41. The field plate structure 4 also includes at least one second stacking structure 42 located above the optimized field plate 41. The second stacking structure 42 includes a second isolation layer 421 and an upper field plate 422 stacked in sequence. The second isolation layer 421 covers the upper surface of the optimized field plate 41, and the end of the upper field plate 422 adjacent to the optimized field plate 41, which is close to the gate structure 2, is located directly above part of the optimized field plate 41.

[0182] Specifically, while ensuring the performance of the device, the distance between the end of the upper field plate 422 close to the drain region 17 and the drain region can be selected according to actual conditions.

[0183] It should be noted that the thickness of the second isolation layer 421 can be the same as or different from the thickness of the underlying dielectric layer 3; the material of the second isolation layer 421 can be the same as or different from the material of the underlying dielectric layer 3; the thickness of the optimized field plate 41 can be the same as or different from the thickness of the upper field plate 422; the material of the optimized field plate 41 can be the same as or different from the material of the upper field plate 422.

[0184] As an example, the field plate structure 4 includes a second stacked structure 42 , and in the direction from the source region 16 to the drain region 17 , the size of the portion above the cell region 11 in the upper field plate 422 is not less than the size of the portion above the terminal region 12 .

[0185] Specifically, the field plate structure 4 includes a second stacked structure 42 , and in the direction from the source region 16 to the drain region 17 , the difference between the size of the portion above the cell region 11 and the size of the portion above the terminal region 12 in the upper field plate 422 is not less than 0.1 μm.

[0186] Specifically, while ensuring device performance, along the direction from the source region 16 to the drain region 17 , the difference between the size of the portion above the cell region 11 and the size of the portion above the terminal region 12 in the upper field plate 422 may also be other suitable differences.

[0187] Specifically, forming a second stacked structure 42 above the optimized field plate 41 includes the following steps: forming a second isolation layer 421 on the upper surface of the semiconductor structure 20 after the optimized field plate 41 is formed, and forming an upper field plate material layer on the upper surface of the second isolation layer 421; etching the upper field plate material layer to obtain an upper field plate 422.

[0188] Specifically, the method of forming the second isolation layer 421 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0189] Specifically, the material of the second isolation layer 421 includes a silicon oxide layer, a silicon nitride layer, an aluminum nitride layer or other suitable dielectric material layers. In this embodiment, a silicon oxide layer is used as the second isolation layer 421 .

[0190] Specifically, the method of forming the upper field plate material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0191] Specifically, the method of etching the upper field plate material layer includes dry etching, wet etching or other suitable methods.

[0192] Specifically, when the field plate structure 4 includes a second stacking structure 42 and the first stacking structure is not arranged between the optimized field plate 41 and the underlying dielectric layer 3, while ensuring the device performance, in the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 in the upper field plate 422 may also be smaller than the size of the portion above the terminal region 12.

[0193] As an example, the field plate structure 4 includes multiple layers of second stacked structures 42 . In two adjacent layers of second stacked structures 42 , one end of the upper field plate 422 of the upper second stacked structure 42 close to the gate structure 2 is located directly above the upper field plate 422 of the lower second stacked structure 42 .

[0194] Specifically, when the field plate structure 4 includes multiple layers of second stacking structures 42 , in two adjacent second stacking structures, the second isolation layer 421 of the upper second stacking structure 42 covers the exposed surface of the upper field plate 422 and the exposed upper surface of the second isolation layer 421 of the lower second stacking structure 42 .

[0195] Specifically, when the field plate structure 4 includes a multi-layer second stacking structure 42, the steps of forming a second isolation layer 421, forming an upper field plate material layer and etching the upper field plate material layer are repeated in sequence until the number of layers of the second stacking structure 42 above the optimized field plate 41 reaches a preset number of layers to obtain the field plate structure 4.

[0196] As an example, in the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 in the upper field plate 422 of at least one layer of the second stacked structure 42 is not less than the size of the portion above the terminal region 12, that is, when the field plate structure 4 includes multiple layers of the second stacked structure 42, the size of the portion above the cell region 11 in at least one upper field plate 422 is less than the size of the portion above the terminal region 12. In this embodiment, a second stacked structure 42 is provided above the optimized field plate 41, and the size of the portion above the cell region 11 in the upper field plate 422 of the second stacked structure 42 is greater than the size of the portion above the terminal region 12.

[0197] As an example, the thicknesses of different second isolation layers 421 are not completely the same, that is, when the field plate structure 4 includes multiple layers of second stacked structures 42, the thicknesses of the second isolation layers 421 in each second stacked structure 42 are partially different or completely different. When the field plate structure 4 includes multiple layers of second stacked structures 42, the thicknesses of the second isolation layers 421 in each second stacked structure 42 may also be completely the same while ensuring device performance.

[0198] As an example, the thicknesses of different upper field plates 422 are not completely the same, that is, when the field plate structure 4 includes multiple layers of second stacked structures 42, the thicknesses of the upper field plates 422 in each second stacked structure 42 are partially different or completely different. When the field plate structure 4 includes multiple layers of second stacked structures 42, the thicknesses of the upper field plates 422 in each second stacked structure 42 may also be completely the same while ensuring device performance.

[0199] As an example, different upper field plates 422 have different sizes in the arrangement direction of the drift region 14 and the well region 15. When the field plate structure 4 includes multiple layers of second stacked structures 42, in the arrangement direction of the drift region 14 and the well region 15, the sizes of the upper field plates 422 in each second stacked structure 42 may be partially different or completely the same while ensuring device performance.

[0200] Specifically, when the field plate structure 4 includes a multilayer second stacking structure 42 and the first stacking structure is not provided between the optimized field plate 41 and the bottom dielectric layer 3, under the condition of ensuring the device performance, in the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 and the size of the portion above the terminal region 12 in each upper field plate 422 can be selected according to the actual situation, for example, the size of the portion above the cell region 11 can be the same as the size of the portion above the terminal region 12, or the size of the portion above the cell region 11 can be larger than the size of the portion above the terminal region 12, or the size of the portion above the cell region 11 can be smaller than the size of the portion above the terminal region 12. Preferably, the size of the portion above the cell region 11 in all upper field plates 422 is larger than the size of the portion above the terminal region 12.

[0201] As an example, in the direction from the source region 16 to the drain region 17, the size of the field plate adjacent to the gate structure 2 in the field plate structure 4 is not less than 0.35 μm. That is, when the field plate structure 4 is provided with a first stacking structure, the size of the lower field plate adjacent to the gate structure 2 in the direction from the source region 16 to the drain region 17 is not less than 0.35 μm, and when the field plate structure 4 does not include the first stacking structure, the size of the optimized field plate 41 adjacent to the gate structure 2 in the direction from the source region 16 to the drain region 17 is not less than 0.35 μm.

[0202] Specifically, the performance and reliability of the device are guaranteed by ensuring that the dimension of the field plate close to the gate structure 2 in the direction from the source region 16 to the drain region 17 is not less than 0.35 μm.

[0203] As an example, after forming the field plate structure 4 , the steps further include forming a source electrode 6 electrically connected to the source region 16 and the field plate structure 4 , a drain electrode 7 electrically connected to the drain region 17 , and a gate electrically connected to the gate structure 2 .

[0204] As an example, Fig.16 and Fig.17As shown, they are respectively a schematic diagram of the cross-sectional structure of the cell region 11 after the interlayer dielectric layer 43 is formed and a schematic diagram of the cross-sectional structure of the terminal region 12 after the interlayer dielectric layer 43 is formed (the size of the upper portion of the cell region 11 in the optimized field plate 41 and the upper field plate 422 in the figure is larger than the size of the upper portion of the terminal region 12, because the subsequent process flow charts are all in Fig.16 and Fig.17 The subsequent processes are sequentially performed on the basis of the structure in the figure, so the field plate structure 2 in the figure is no longer described in detail in the subsequent process flow chart), after the field plate structure 4 is formed, before the source 5, the drain 6 and the gate are formed, it also includes the step of forming an interlayer dielectric layer 43 covering the field plate structure 4 on the bottom dielectric layer 3, the source penetrates the interlayer dielectric layer 43 and the bottom dielectric layer 3 and is electrically connected to the source region 16, the drain 6 penetrates the interlayer dielectric layer 43 and the bottom dielectric layer 3 and is electrically connected to the drain region 17, and the gate penetrates the interlayer dielectric layer 43 and is electrically connected to the gate conductive layer 22.

[0205] Specifically, the method of forming the interlayer dielectric layer 43 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0206] Specifically, after forming the interlayer dielectric layer 43 and before forming the source electrode 5 , the drain electrode 6 and the gate electrode, a step of thinning the interlayer dielectric layer 43 is further included to make the thickness of the interlayer dielectric layer 43 reach a preset thickness.

[0207] Specifically, the method of thinning the interlayer dielectric layer 43 includes chemical mechanical polishing, dry etching, wet etching or other suitable methods. In this embodiment, the interlayer dielectric layer 43 is thinned by using a chemical mechanical polishing process.

[0208] Specifically, under the condition of ensuring the performance of the device, the thickness of the interlayer dielectric layer 43 can be selected according to the actual situation, and is not limited here. In this embodiment, the thickness of the interlayer dielectric layer 43 obtained after thinning is 3 μm.

[0209] Specifically, the source electrode 5 is electrically connected to the source region 16 through the first contact layer 23, the drain electrode 6 is electrically connected to the drain region 17 through the second contact layer 24, and the gate electrode is electrically connected to the gate conductive layer 22 through the third contact layer 25. When a substrate contact region 19 and a source contact region 18 are formed in the device, the source electrode 5 is also electrically connected to the substrate contact region 19 and the source contact region 18 respectively through the first contact layer 23.

[0210] Specifically, Fig.18 and Fig.19As shown, they are schematic cross-sectional structures of the cell region 11 after the first plug 51 and the second plug 61 are formed, and schematic cross-sectional structures of the terminal region 12 after the first plug 51 and the second plug 61 are formed. Forming the source 5, the drain 6 and the gate comprises the following steps: forming a source contact hole, a drain contact hole and a gate contact hole in the interlayer dielectric layer 43, wherein the bottom surfaces of the source contact hole respectively expose the first contact layer 23 and each field plate in the field plate structure 4, the bottom surface of the drain contact hole exposes the second contact layer 24, and the bottom surface of the gate contact hole exposes the third contact layer 25; forming a source contact hole, a drain contact hole and a gate contact hole and covering the interlayer dielectric layer 43; The first filling layer on the upper surface is removed, and the first filling layer covering the upper surface of the interlayer dielectric layer 43 is removed to obtain a first plug 51 filling the source contact hole, a second plug 61 filling the drain contact hole, and a third plug filling the gate contact hole; an interconnection material layer covering the upper surface of the interlayer dielectric layer 43 is formed, and the interconnection material layer is etched to simultaneously obtain a source interconnection layer 52, a drain interconnection layer 62, and a gate interconnection layer, the source interconnection layer 52 interconnects the first plug 51 and together with the first plug 51 constitutes a source 5, the drain interconnection layer 62 interconnects the second plug 61 and together with the second plug 61 constitutes a drain 6, and the gate interconnection layer interconnects the third plug and together with the third plug constitutes a gate. In this embodiment, two source contact holes are formed above the first contact layer 23 at intervals to reduce the contact resistance between the source 5 and the substrate contact area 19 and the source contact area 18. Under the condition of ensuring the device performance, one source contact hole can be formed on the side of the gate structure 2 close to the substrate contact area 19, or three or more source contact holes can be formed.

[0211] Specifically, the method of etching the interlayer dielectric layer 43 includes dry etching, wet etching or other suitable methods.

[0212] Specifically, while ensuring device performance, the number, size and shape of the source contact holes can be selected according to actual conditions and are no longer restricted here; the size and shape of the gate contact holes can be selected according to actual conditions and are no longer restricted here; the size and shape of the drain contact holes can be selected according to actual conditions and are no longer restricted here.

[0213] Specifically, the method of forming the first filling layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of forming the interconnection material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0214] Specifically, the method of removing the first filling layer covering the upper surface of the interlayer dielectric layer 43 includes dry etching, wet etching, chemical mechanical polishing or other suitable methods; the method of etching the interconnect material layer includes dry etching, wet etching or other suitable methods.

[0215] Specifically, Fig. 20 and Fig.21 As shown, there are respectively a schematic diagram of the cross-sectional structure of the cell region 11 after the source 5 and the drain 6 are formed, and a schematic diagram of the cross-sectional structure of the terminal region 12 after the source 5 and the drain 6 are formed. The source 5 is electrically connected to the source region 16, the source contact region 18, the substrate contact region 19 and each field plate in the field plate structure 4 through a source contact hole penetrating the interlayer dielectric layer 43, the drain 6 is electrically connected to the drain region 17 through the drain contact hole, and the gate is electrically connected to the gate conductive layer 22 through the gate contact hole.

[0216] Specifically, Figure 24 to Figure 27 As shown, they are respectively a schematic diagram of the cross-sectional structure of the cell region 11 after the fourth plug 53 and the fifth plug 63 are formed, a schematic diagram of the cross-sectional structure of the terminal region 12 after the fourth plug 53 and the fifth plug 63 are formed, a schematic diagram of the cross-sectional structure of the cell region 11 after the source pad 54 and the drain pad 64 are formed, and a schematic diagram of the cross-sectional structure of the terminal region 12 after the source pad 54 and the drain pad 64 are formed. After the source 5, the drain 6 and the gate are formed, the following steps are also included: forming an insulating layer 7 covering the upper surface of the interlayer dielectric layer 43 and the exposed surfaces of each electrode (source 5, drain 6 and gate); simultaneously forming a source lead-out hole, a drain lead-out hole and a gate lead-out hole penetrating the insulating layer 7, the bottom surface of the source lead-out hole exposes the source 5, the bottom surface of the gate lead-out hole exposes the gate, and the bottom surface of the drain lead-out hole exposes the drain 6; forming a source lead-out hole, a drain lead-out hole and a gate lead-out hole filled with the source lead-out hole, the drain lead-out hole and the gate The method comprises the following steps: forming a lead-out hole and covering a second filling layer on the upper surface of the insulating layer 8, and removing the second filling layer covering the upper surface of the insulating layer 7 to obtain a fourth plug 53 filling the source lead-out hole, a fifth plug 63 filling the drain lead-out hole, and a sixth plug filling the gate lead-out hole; forming a pad layer covering the upper surfaces of the insulating layer 7, the fourth plug 53, the fifth plug 63, and the sixth plug, and etching the pad layer to obtain a source pad 54 electrically connected to the fourth plug 53, a drain pad 64 electrically connected to the fifth plug 63, and a gate pad electrically connected to the sixth plug; forming a passivation layer 8 covering the exposed surface of the source pad 54, the drain pad 64, and the gate pad and the upper surface of the insulating layer 7, and etching the passivation layer 8 to expose the source pad 54, the drain pad 64, and the gate pad; thinning the substrate 1 from the back side of the substrate 1 to a preset thickness, and forming a back electrode layer 9 on the back side of the thinned substrate 1.

[0217] Specifically, Fig. 22 and Fig.23As shown, they are respectively a schematic diagram of the cross-sectional structure of the cell area 11 after the insulating layer 7 is formed and a schematic diagram of the cross-sectional structure of the terminal area 12 after the insulating layer 7 is formed. The method of forming the insulating layer 7 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0218] Specifically, after forming the insulating layer 7 and before forming the second filling layer, the method further includes a step of thinning the insulating layer 8 to a preset thickness.

[0219] Specifically, the method of thinning the insulating layer 7 includes dry etching, wet etching, chemical mechanical polishing or other suitable methods.

[0220] Specifically, the method of simultaneously forming the source lead-out hole, the drain lead-out hole and the gate lead-out hole penetrating the insulating layer 7 includes dry etching, wet etching or other suitable methods.

[0221] Specifically, the method of forming the second filling layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of removing the second filling layer covering the upper surface of the insulating layer 8 includes dry etching, wet etching, chemical mechanical grinding or other suitable methods; the method of forming the pad layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method of etching the pad layer includes dry etching, wet etching or other suitable methods.

[0222] Specifically, Fig.28 and Fig.29 As shown, they are respectively a schematic diagram of the cross-sectional structure of the cell area 11 after the passivation layer 8 is formed and a schematic diagram of the cross-sectional structure of the terminal area 12 after the passivation layer 8 is formed. The method of forming the passivation layer 8 includes physical vapor deposition, chemical vapor deposition or other suitable methods.

[0223] Specifically, Fig.30 , Fig.31 and Fig.32 As shown, there are respectively a schematic diagram of the cross-sectional structure of the cell area 11 after the back electrode layer 9 is formed, a schematic diagram of the cross-sectional structure of the terminal area 12 after the back electrode layer 9 is formed, and a schematic diagram of the arrangement of the top surface parts after the back electrode layer 9 is formed. The method for etching the passivation layer 8 includes dry etching, wet etching or other suitable methods; the method for thinning the substrate 1 from the back side of the substrate 1 includes chemical mechanical grinding, dry etching, wet etching or other suitable methods; the method for forming the back electrode layer 9 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0224] Specifically, an optimized field plate 41 is formed in the field plate structure 4 of the device, and in the arrangement direction of the drift region 14 and the well region 15, the size of the portion above the cell region 11 in the optimized field plate 41 is larger than the size of the portion above the terminal region 12, so that the electric field lines in the terminal region 12 of the device are more directed to the gate of the device and the optimized field plate 41, thereby improving the electric field distribution in the terminal region 12, avoiding the aggregation of electric field lines in the boundary area between the cell region 11 and the terminal region 12 to reduce the breakdown voltage at the terminal region 12, and improving the breakdown voltage at the terminal region 12 of the device to make it greater than the breakdown voltage of the cell region 11, without changing the device manufacturing steps.

[0225] Specifically, since the breakdown voltage of the cell region 11 of the device is lower than that of the terminal region 12, the breakdown position of the device is located in the cell region 11, thereby avoiding the voltage breakdown position of the device occurring on the surface of the device, improving the robustness of the device, and increasing the breakdown voltage and reliability of the device.

[0226] The preparation method of the semiconductor device of this embodiment forms an optimized field plate 41 in the field plate structure 4. In the direction from the source region 16 to the drain region 17, the size of the part above the cell region 11 in the optimized field plate 41 is larger than the size of the part above the terminal region 12, so as to guide the electric field lines in the terminal region 12 of the device more toward the gate of the device and the optimized field plate 41, thereby improving the electric field distribution in the terminal region 12, avoiding the aggregation of electric field lines in the boundary area between the cell region 11 and the terminal region 12 to reduce the breakdown voltage in the terminal region 12, increasing the breakdown voltage in the terminal region 12 of the device and making it greater than the breakdown voltage of the cell region 11, so that the position where the device breaks down is within the cell region 11, avoiding the voltage breakdown position of the device occurring on the surface of the device, improving the robustness of the device, and improving the breakdown voltage and reliability of the device without increasing the manufacturing steps.

[0227] Embodiment 2

[0228] This embodiment provides a semiconductor device, such as Fig.30 , Fig.31 and Fig.32As shown, it is a schematic diagram of the cross-sectional structure of the cell region of the semiconductor device, a schematic diagram of the cross-sectional structure of the terminal region of the semiconductor device, and a schematic diagram of the arrangement of the top surface parts of the semiconductor device, including a semiconductor structure 20, an underlying dielectric layer 3 and a field plate structure 4, wherein the semiconductor structure 20 includes a semiconductor layer 1 and a gate structure 2 located on the upper surface of the semiconductor layer 1, the semiconductor layer 1 includes a cell region 11 and a terminal region 12 located outside the cell region 11, and the source region 16 and the drain region 17 of the device are located on the upper surface of the semiconductor layer 1 on opposite sides of the gate structure 2; the underlying dielectric layer 3 covers the upper surface of the semiconductor structure 20; the field plate structure 4 is located on the upper surface of the underlying dielectric layer 3 on the side of the gate structure 2 close to the drain region 17, and the field plate structure 4 includes at least one optimized field plate 41, and in the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 in the optimized field plate 41 is larger than the size of the portion above the terminal region 12.

[0229] As an example, the semiconductor layer 1 also includes a first conductive type drift region 14 and a second conductive type well region 15. The doping types of the source region 16 and the drain region 17 are the same as the doping type of the drift region 14. The source region 16 is located on the upper surface of the well region 15, the drain region 17 is located on the upper surface of the drift region 14 in the cell region 11, and the gate structure 2 is located on the upper surface of the semiconductor layer 1 between the source region 16 and the drift region 14.

[0230] As an example, the semiconductor layer 1 also includes a second conductive type substrate 10 and a second conductive type epitaxial layer 13 stacked in sequence, the drift region 14 and the well region 15 are located on the upper surface layer of the epitaxial layer 13, and a second conductive type substrate contact region 19 is also provided in the semiconductor layer 1. The substrate contact region 19 extends from the surface of the epitaxial layer 13 at least to the top surface of the substrate 10. The substrate contact region 19 is typically a heavily doped region to facilitate ohmic contact with the source 5.

[0231] Specifically, the doping concentration of the epitaxial layer 13 is less than the doping concentration of the substrate 10, and the material of the substrate 10 includes silicon, silicon germanium, silicon carbide, gallium nitride or other suitable semiconductor materials; the material of the epitaxial layer 13 includes silicon, silicon germanium, silicon carbide, gallium nitride or other suitable semiconductor materials.

[0232] Specifically, the epitaxial layer is also provided with an isolation structure 191 defining the active region of the device. Under the condition of ensuring the performance of the device, the structure, size and shape of the isolation structure 191 can be selected according to the actual situation, and no limitation is imposed here. In this embodiment, a silicon oxide layer with a thickness of 450 nm formed by a local oxidation process is used as the isolation structure 191.

[0233] Specifically, the substrate contact region 19 may be adjacent to the sidewall of the well region 15 away from the drift region 14, or may be spaced apart from the well region 15 by a preset distance; while ensuring device performance, the size, doping concentration and thickness of the substrate contact region 16 may be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the upper surface and the bottom surface of the substrate contact region 16.

[0234] Specifically, the drift region 14 is used to ensure the withstand voltage of the device, and the well region 15 is used to adjust the threshold voltage of the device. The drift region 14 can be spaced apart from the well region 15, or can be adjacent to the well region 15. Under the condition of ensuring the performance of the device, the size, shape, doping concentration and thickness of the drift region 14 can be selected according to actual conditions; the size, shape, doping concentration and thickness of the well region 15 can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the drift region 14 and the well region 15 and the upper surface thereof.

[0235] Specifically, the contact type between the source region 16 and the source electrode 5 and the contact type between the drain region 17 and the drain electrode 6 are both ohmic contacts. The source region 16 and the side wall of the well region 15 close to the drift region 14 are separated by a preset distance. Under the condition of ensuring the performance of the device, the doping concentration, size, thickness of the source region 16 and the distance between the side wall of the well region 15 close to the drift region 14 can be selected according to actual conditions; the doping concentration, size, thickness of the drain region 17 and the distance between the side wall of the drift region 14 close to the well region 15 can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the source region 16 and the drain region 17 and the upper surface thereof.

[0236] As an example, the semiconductor layer 1 is further provided with a second conductive type source contact region 18 located on the upper surface of the well region 15 , and the source contact region 18 is adjacent to the source region 16 on one side thereof.

[0237] Specifically, the contact type between the source contact region 18 and the source 5 is an ohmic contact, and the substrate contact region 19 can be adjacent to the side wall of the source contact region 18 away from the source region 16, or can be spaced apart from the source contact region 18 by a preset distance. Under the condition of ensuring the performance of the device, the size, shape, thickness and doping concentration of the source contact region 18 can be selected according to actual conditions. The thickness here refers to the distance between the bottom surface of the source contact region 18 and its upper surface.

[0238] As an example, the gate structure 2 includes a gate dielectric layer 21 and a gate conductive layer 22 stacked in sequence, the size of the gate dielectric layer 21 is not smaller than the size of the gate conductive layer 22, the gate conductive layer 22 is located directly above the area between the source region 16 and the drift region 14, and the gate conductive layer 22 extends to directly above the source region 16 and the drift region 14 at both ends of the arrangement direction of the drift region 14 and the well region 15.

[0239] Specifically, the material of the gate dielectric layer 21 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials; the material of the gate conductive layer 22 includes polysilicon or other suitable conductive materials; the thickness of the gate dielectric layer 21 can be selected according to actual conditions while ensuring the performance of the device; the thickness of the gate conductive layer 22 can be selected according to actual conditions. In this embodiment, a silicon oxide layer with a thickness of 30nm is used as the gate dielectric layer 21, and a high-concentration N-type doped polysilicon layer with a thickness of 300nm is used as the gate conductive layer 22.

[0240] As an example, a first contact layer 23 and a second contact layer 24 are further provided in the semiconductor structure 1 . The first contact layer 23 covers the upper surface of the source region 16 , and the second contact layer 24 covers the upper surface of the drain region 17 .

[0241] Specifically, a third contact layer 25 is also provided on the upper surface of the gate conductive layer 22, and the first contact layer 23 also covers the upper surfaces of the source contact area 18 and the substrate contact area 19. The first contact layer 23 is used to reduce the contact resistance between the source 5 and the source area 16, the source contact area 18 and the substrate contact area 19 respectively, the second contact layer 24 is used to reduce the contact resistance between the drain 6 and the drain area 17, and the third contact layer 25 is used to reduce the contact resistance between the gate conductive layer 22 and the gate.

[0242] Specifically, the material of the first contact layer 23 includes TiSi alloy, CoSi alloy, MoSi alloy, NiSi alloy, NiPtSi alloy, WSi alloy or other suitable metal silicide materials; the material of the second contact layer 24 includes TiSi alloy, CoSi alloy, MoSi alloy, NiSi alloy, NiPtSi alloy, WSi alloy or other suitable metal silicide materials; the material of the third contact layer 25 includes TiSi alloy, CoSi alloy, MoSi alloy, NiSi alloy, NiPtSi alloy, WSi alloy or other suitable metal silicide materials.

[0243] Specifically, under the condition of ensuring the performance of the device, the thickness and shape of the first contact layer 23 can be selected according to the actual situation; the thickness and shape of the second contact layer 24 can be selected according to the actual situation; the thickness and shape of the third contact layer 25 can be selected according to the actual situation. In this embodiment, a TiSi alloy layer is used as the first contact layer 23 and the second contact layer 24, and a WSi alloy layer with a thickness of 100 nm is used as the third contact layer 25.

[0244] Specifically, under the condition of ensuring the performance of the device, the thickness of the bottom dielectric layer 3 can be selected according to the actual situation. In this embodiment, the thickness of the bottom dielectric layer 3 is 70 nm.

[0245] Specifically, the material of the optimized field plate 41 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0246] Specifically, while ensuring device performance, the thickness of the optimized field plate 41 can be selected according to actual conditions; in the direction from the source region 16 to the drain region 17, the size of the optimized field plate 41 above the cell region 11 can be selected according to actual conditions; in the direction from the source region 16 to the drain region 17, the size of the optimized field plate 41 above the terminal region 12 can be selected according to actual conditions.

[0247] Specifically, only one optimized field plate 41 is provided in the field plate structure 4 as the field plate of the device, and one end of the optimized field plate 41 close to the gate structure 2 is located directly above the gate structure 2 .

[0248] As an example, the field plate structure 4 also includes at least one first stacking structure (not shown in the figure) located between the underlying dielectric layer 3 and the optimized field plate 41, the first stacking structure includes a lower field plate and a first isolation layer stacked in sequence, the optimized field plate 41 is located on the upper surface of the first isolation layer adjacent to the optimized field plate 41, one end of the optimized field plate 41 close to the gate structure 2 is located directly above the lower field plate adjacent to the optimized field plate 41, and one end of the lower field plate adjacent to the underlying dielectric layer 3 close to the gate structure 2 is located directly above the gate structure 2, and the lower field plate is only located above the cell region 11.

[0249] Specifically, the material of the lower field plate includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0250] Specifically, while ensuring device performance, the thickness of the lower field plate can be selected according to actual conditions; in the direction from the source region 16 to the drain region 17 , the size of the lower field plate above the cell region 11 can be selected according to actual conditions.

[0251] Specifically, the material of the first isolation layer includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. The thickness of the first isolation layer can be selected according to actual conditions while ensuring device performance. In this embodiment, a silicon oxide layer with a thickness of 130 nm is used as the first isolation layer.

[0252] As an example, the thickness of the first isolation layer is different from the thickness of the bottom dielectric layer 3 ; the thickness of the lower field plate is different from the thickness of the optimized field plate 41 .

[0253] Specifically, under the condition of ensuring the performance of the device, the thickness and material of each first isolation layer and the bottom dielectric layer 3 can be the same or different.

[0254] Specifically, the field plate structure 4 includes multiple layers of first stacked structures. In two adjacent layers of first stacked structures, one end of the lower field plate of the upper first stacked structure close to the gate structure 2 is located directly above the lower field plate of the lower first stacked structure.

[0255] As an example, different lower field plates have different sizes in the direction of arrangement of the drift region 14 and the well region 15; different lower field plates have different thicknesses; and different first isolation layers have different thicknesses. Under the condition of ensuring device performance, the thickness of the lower field plates in each first stacking structure can also be completely the same or partially the same; in the direction from the source region 16 to the drain region 17, the size of the lower field plates above the cell region 11 in each first stacking structure can also be completely the same or partially the same; in the direction from the source region 16 to the drain region 17, the thickness of the first isolation layer in each first stacking structure can be completely the same or partially the same.

[0256] Specifically, under the condition of ensuring the device performance, the number of the first stacked structures in the field plate structure 4 can be selected according to actual conditions.

[0257] As an example, the field plate structure 4 also includes at least one second stacking structure 42 located above the optimized field plate 41, and the second stacking structure 42 includes a second isolation layer 421 and an upper field plate 422 stacked in sequence, the second isolation layer 421 covers the upper surface of the optimized field plate 41, and the end of the upper field plate 422 adjacent to the optimized field plate 41, close to the gate structure 2, is located directly above the optimized field plate 41.

[0258] As an example, the field plate structure 4 includes a second stacked structure 42, and in the direction from the source region 16 to the drain region 17, the size of the portion of the upper field plate 422 above the cell region 11 is not less than the size of the portion above the terminal region 12. In this embodiment, an optimized field plate 41 and an upper field plate 422 are provided in the device, and a tungsten layer with a thickness of 150 nm is used as the optimized field plate 41 and the upper field plate 422 respectively, the distance between the end of the optimized field plate 41 above the cell region 11 close to the drain region 17 and the gate structure 2 is 0.7 μm, the distance between the end of the optimized field plate 41 above the terminal region 12 close to the drain region 17 and the gate structure 2 is 0.5 μm, the distance between the end of the upper field plate 422 above the cell region 11 close to the drain region 17 and the adjacent optimized field plate 41 is 0.8 μm, and the distance between the end of the upper field plate 422 above the terminal region 12 close to the drain region 17 and the adjacent optimized field plate 41 is 0.5 μm.

[0259] As an example, the field plate structure 4 includes multiple layers of second stacked structures 42 , and in two adjacent layers of second stacked structures 42 , one end of the upper field plate 422 of the upper second stacked structure 42 close to the gate structure 2 is located directly above a portion of the lower field plate 422 of the lower second stacked structure 42 .

[0260] As an example, in the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 in the upper field plate 422 of at least one layer of the second stacked structure 42 is not less than the size of the portion above the terminal region 12. While ensuring device performance, in the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 in the upper field plate 422 is less than the size of the portion above the terminal region 12.

[0261] Specifically, under the condition of ensuring the device performance, the number of the second stacked structures 42 in the field plate structure 4 can be selected according to actual conditions.

[0262] Specifically, the material of the second isolation layer 421 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials.

[0263] Specifically, the material of the upper field plate 422 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0264] As an example, in the direction from the source region 16 to the drain region 17, the size of the field plate adjacent to the gate structure 2 in the field plate structure 4 is not less than 0.35 μm, that is, when the first stacking structure is provided in the field plate structure 4, the size of the lower field plate adjacent to the gate structure 2 in the direction from the source region 16 to the drain region 17 is not less than 0.35 μm, and when the field plate structure 4 does not include the first stacking structure, the size of the optimized field plate 41 adjacent to the gate structure 2 in the direction from the source region 16 to the drain region 17 is not less than 0.35 μm.

[0265] Specifically, the device is further provided with an interlayer dielectric layer 43 covering the exposed surface of the field plate structure 4. The material of the interlayer dielectric layer 43 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In this embodiment, a silicon oxide layer is used as the interlayer dielectric layer 43.

[0266] Specifically, under the condition of ensuring the performance of the device, the thickness of the interlayer dielectric layer 43 can be selected according to the actual situation. In this embodiment, the thickness of the interlayer dielectric layer 43 is 3 μm.

[0267] Specifically, the interlayer dielectric layer 43 is also provided with a source contact hole, a drain contact hole and a gate contact hole penetrating the interlayer dielectric layer 43, the bottom surface of the source contact hole respectively exposes the first contact layer 23 and each field plate in the field plate structure 4, the bottom surface of the drain contact hole exposes the second contact layer 24, and the bottom surface of the gate contact hole exposes the third contact layer 25.

[0268] Specifically, the device is further provided with a source electrode 6 electrically connected to the source region 16 and the field plate structure 4 , a drain electrode 7 electrically connected to the drain region 17 , and a gate electrode electrically connected to the gate structure 2 .

[0269] Specifically, the source 6 includes a first plug 51 filling the source contact hole and a source interconnection layer 52 electrically connecting the first plugs 51, the drain 7 includes a second plug 61 filling the drain contact hole and a drain interconnection layer 62 interconnecting the second plugs 61, and the gate includes a third plug filling the gate contact hole and a gate interconnection layer interconnecting the third plug.

[0270] Specifically, the material of the first plug 51 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the second plug 61 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the third plug includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the source interconnection layer 52 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, copper-aluminum alloy or other suitable conductive materials; the material of the drain interconnection layer 62 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, copper-aluminum alloy or other suitable conductive materials; the material of the gate interconnection layer includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, copper-aluminum alloy or other suitable conductive materials. In this embodiment, tungsten plugs are used as the first plug 51 , the second plug 61 and the third plug, and a copper-aluminum alloy layer with a thickness of 3 μm is used as the source interconnection layer 52 , the drain interconnection layer 62 and the gate interconnection layer.

[0271] Specifically, the upper surface of the interlayer dielectric layer 43 is also provided with an insulating layer 7 and a source lead-out hole, a drain lead-out hole and a gate lead-out hole penetrating the insulating layer 7. The insulating layer 7 covers the exposed surfaces of the source 5, the drain 6 and the gate and the upper surface of the interlayer dielectric layer 43. The bottom surface of the source lead-out hole exposes the source interconnection layer 52, the bottom surface of the drain lead-out hole exposes the drain interconnection layer 62, and the bottom surface of the gate lead-out hole exposes the gate interconnection layer.

[0272] Specifically, the material of the insulating layer 7 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In this embodiment, a silicon oxide layer is used as the insulating layer 7 .

[0273] Specifically, under the condition of ensuring the performance of the device, the thickness of the insulating layer 7 can be selected according to the actual situation; the opening size and shape of the source lead-out hole can be selected according to the actual situation; the opening size and shape of the drain lead-out hole can be selected according to the actual situation; the opening size and shape of the gate lead-out hole can be selected according to the actual situation. In this embodiment, the thickness of the insulating layer 7 is 3 μm, where the thickness refers to the distance between the upper surface of each interconnection layer and the upper surface of the insulating layer 7.

[0274] Specifically, the device is further provided with a fourth plug 53 filling the source contact hole, a sixth plug filling the gate lead-out hole, a fifth plug 63 filling the drain lead-out hole, a source pad 54 located on the upper surface of the insulating layer 7 and electrically connected to the fourth plug 53, a gate pad located on the upper surface of the insulating layer 8 and electrically connected to the sixth plug, and a drain pad 64 located on the upper surface of the insulating layer 7 and electrically connected to the fifth plug 63, wherein the material of each pad is the same as the material of each interconnection layer, and the material of the fourth to sixth plugs is the same as the material of the first to third plugs, which will not be repeated here.

[0275] Specifically, the device is further provided with a back metal layer covering the bottom surface of the substrate 10 and a passivation layer 8 covering each pad and the upper surface of the insulating layer 7. The material of the passivation layer 8 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable materials; the material of the back electrode layer 9 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials. In this embodiment, a composite film layer structure consisting of a 300nm silicon oxide layer and an 800nm ​​silicon nitride layer is used as the passivation layer 8, and a Ti / Ni / Ag layer is used as the back electrode layer 9.

[0276] Specifically, take the RF-LDMOS with two field plates as an example. Fig.33 As shown, Figure 1 Devices and Fig.32 The breakdown simulation test statistics of the device in the figure are as follows: Fig.32 The optimized field plate 41 above the middle terminal region 12 is relative to Figure 1 The first field plate in the gate structure 2 decreases by 300 nm from the side close to the drain region 17 toward the gate structure 2, and the upper field plate above the terminal region 12 decreases by 300 nm relative to the Figure 1 The second field plate in the embodiment decreases by 200 nm from the direction close to the drain region 17 toward the gate structure 2. Figure 1 Devices and Fig.32 The parameters of the rest of the device are the same. Fig.33 It can be seen from the statistical results that Figure 1 The breakdown of the terminal region of the device occurs on the device surface with a breakdown voltage of 64V, while the breakdown of the cell region occurs inside the device with a breakdown voltage of 70V. Fig.32 The breakdown of the device in the terminal region 12 and the cell region 11 occurs in the device body, and the breakdown voltage of the cell region 11 (70V) is less than the breakdown voltage of the terminal region 12 (75V), that is, the semiconductor device of the present application is relatively Figure 1 The device improves the breakdown voltage at the terminal region 12 and makes the breakdown at the terminal region 12 occur within the device body, thereby improving the robustness of the device.

[0277] Specifically, by improving the structure of the field plate structure 4, an optimized field plate 41 is set in the field plate structure 4, and in the direction from the source region 16 to the drain region 17, the size of the part above the cell region 11 in the optimized field plate 41 is larger than the size of the part above the terminal region 12, thereby improving the breakdown voltage of the terminal region 12 of the device, and making the breakdown voltage of the terminal region 12 greater than the breakdown voltage of the cell region 11, ensuring that the breakdown of the device occurs in the cell region 11 of the device, thereby improving the breakdown voltage of the device and improving the robustness of the device.

[0278] The semiconductor device of this embodiment improves the structure of the field plate structure 4, and an optimized field plate 41 is provided in the field plate structure 4. In the direction from the source region 16 to the drain region 17, the size of the portion above the cell region 11 in the optimized field plate 41 is larger than the size of the portion above the terminal region 12, so that the breakdown voltage of the terminal region 12 is greater than the breakdown voltage of the cell region 11 and does not affect the breakdown voltage of the cell region 11, thereby ensuring that the breakdown of the device occurs in the cell region 11, thereby improving the overall breakdown voltage of the device, and at the same time causing the breakdown of the device to occur within the device body, thereby improving the robustness of the device.

[0279] In summary, the semiconductor device and preparation method of the present invention are provided with an optimized field plate in the field plate structure, and in the direction from the source region to the drain region, the size of the portion above the cell region in the optimized field plate is larger than the size of the portion above the terminal region, so that the electric field lines in the terminal region of the device are more directed to the gate and the optimized field plate of the device, the electric field distribution in the terminal region is improved, the electric field lines in the boundary region between the cell region and the terminal region are avoided to gather and reduce the breakdown voltage at the terminal region, the breakdown voltage at the terminal region of the device is increased and made greater than the breakdown voltage of the cell region, and the breakdown voltage of the cell region of the device is not affected, the position where the device breakdown occurs is ensured to be in the body of the cell region, the voltage breakdown position of the device is avoided to occur on the surface of the device, the robustness of the device is improved, the breakdown voltage and reliability of the device are increased, and the device manufacturing steps are not changed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0280] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor structure, comprising a semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, wherein the semiconductor layer comprises a cell region and a terminal region adjacent to the cell region, and a source region and a drain region of the device are located on the upper surface of the semiconductor layer on opposite sides of the gate structure; a bottom dielectric layer covering the upper surface of the semiconductor structure; A field plate structure is located on the upper surface of the bottom dielectric layer on the side of the gate structure close to the drain region, and the field plate structure includes at least one optimized field plate, and the size of the optimized field plate above the cell region in the direction from the source region to the drain region is larger than the size of the optimized field plate above the terminal region.

2. The semiconductor device according to claim 1, wherein: The semiconductor layer also includes a first conductive type drift region and a second conductive type well region. The doping types of the source region and the drain region are the same as the doping type of the drift region. The source region is located on the upper surface of the well region, the drain region is located on the upper surface of the drift region in the cell region, and the gate structure is located on the upper surface of the semiconductor layer between the source region and the drift region.

3. The semiconductor device according to claim 2, wherein: The semiconductor layer is also provided with a second conductive type source contact region located on the upper surface of the well region, and the source contact region is adjacent to the source region on one side thereof close to the source region.

4. The semiconductor device according to claim 2, wherein: The semiconductor layer also includes a second conductive type substrate and a second conductive type epitaxial layer stacked in sequence, the drift region and the well region are located on the upper surface layer of the epitaxial layer, and a second conductive type substrate contact region is also provided in the semiconductor layer, and the substrate contact region extends from the surface of the epitaxial layer at least to the top surface of the substrate.

5. The semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence, and the size of the gate dielectric layer is not smaller than the size of the gate conductive layer.

6. The semiconductor device according to claim 1, wherein: The semiconductor structure is further provided with a first contact layer and a second contact layer. The first contact layer at least covers the upper surface of the source region, and the second contact layer covers the upper surface of the drain region.

7. The semiconductor device according to claim 1, wherein: The field plate structure also includes at least one first stacked structure located between the bottom dielectric layer and the optimized field plate, the first stacked structure includes a lower field plate and a first isolation layer stacked in sequence, the optimized field plate is located on the upper surface of the first isolation layer adjacent to the optimized field plate, one end of the optimized field plate close to the gate structure is located directly above part of the lower field plate, one end of the lower field plate close to the gate structure is located directly above part of the gate structure, and the lower field plate is only located above the cell region.

8. The semiconductor device according to claim 7, wherein: The field plate structure includes multiple layers of the first stacked structures. In two adjacent layers of the first stacked structures, one end of the lower field plate of the upper layer of the first stacked structure close to the gate structure is located directly above part of the lower field plate of the lower layer of the first stacked structure.

9. The semiconductor device according to claim 8, characterized in that: Different lower field plates have different sizes in the arrangement direction of the drift region and the well region; different lower field plates have different thicknesses; and different first isolation layers have different thicknesses.

10. The semiconductor device according to claim 7, wherein: The thickness of the first isolation layer is different from the thickness of the bottom dielectric layer; the thickness of the lower field plate is different from the thickness of the optimized field plate.

11. The semiconductor device according to claim 1, wherein: The field plate structure also includes at least one second stacked structure located above the optimized field plate, the second stacked structure includes a second isolation layer and an upper field plate stacked in sequence, the second isolation layer covers the upper surface of the optimized field plate, and an end of the upper field plate adjacent to the optimized field plate and close to the gate structure is located directly above a portion of the optimized field plate.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The field plate structure includes a second stacked structure. In the direction from the source region to the drain region, the size of the portion above the cell region in the upper field plate is not less than the size of the portion above the terminal region.

13. The semiconductor device according to claim 11, wherein: The field plate structure includes multiple layers of the second stacked structures. In two adjacent layers of the second stacked structures, one end of the upper field plate of the upper layer of the second stacked structure close to the gate structure is located directly above a portion of the upper field plate of the lower layer of the second stacked structure.

14. The semiconductor device according to claim 13, wherein: In the direction from the source region to the drain region, the size of the portion above the cell region in the upper field plate of at least one layer of the second stacked structure is not less than the size of the portion above the terminal region.

15. The semiconductor device according to claim 13, wherein: The thicknesses of different second isolation layers are not completely the same; the thicknesses of different upper field plates are not completely the same; and the sizes of different upper field plates in the arrangement direction of the drift region and the well region are different.

16. The semiconductor device according to claim 1, wherein: In the direction from the source region to the drain region, a size of the field plate adjacent to the gate structure in the field plate structure is not less than 0.35 μm.

17. A method for preparing a semiconductor device, characterized in that: The following steps are involved: A semiconductor structure is provided, comprising a semiconductor layer and a gate structure located on an upper surface of the semiconductor layer, wherein the semiconductor layer comprises a cell region and a terminal region adjacent to the cell region, and a source region and a drain region of the device are located on an upper surface layer of the semiconductor layer at opposite sides of the gate structure; A bottom dielectric layer is formed covering the upper surface of the semiconductor structure, and a field plate structure is formed on the upper surface of the bottom dielectric layer and is located on the side of the gate structure close to the drain region, wherein the field plate structure includes at least one optimized field plate, and in the direction from the source region to the drain region, the size of the portion above the cell region in the optimized field plate is larger than the size of the portion above the terminal region.

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