Wafer testing method, system and testing machine

Abstract

The invention provides a wafer testing method and system and a testing machine, belongs to the technical field of semiconductors, and can improve the accuracy and efficiency of wafer testing. The method comprises the steps that a test machine receives a calibration starting signal from a test board, the calibration starting signal is used for indicating that a wafer is placed at a designated position, and the designated position is a position where the wafer does not make contact with the test board and the distance between the wafer and the test board is smaller than or equal to a distance threshold value; the test machine sends an open circuit calibration instruction to the test board, wherein the open circuit calibration instruction is used for eliminating adverse effects of stray capacitance between the wafer and the test board on wafer test; the test machine receives the capacity value of the stray capacitor from the test board; and the test machine sends an open circuit calibration success signal to the test board, and the open circuit calibration success signal is determined according to the capacity value of the stray capacitance and is used for indicating that the open circuit calibration of the wafer is successful and indicating a probe of the test board to contact the wafer so as to test the wafer.

Description

Technical Field

[0001] The embodiments of the present application belong to the field of semiconductor technology, and in particular, relate to a wafer testing method, system and testing machine. Background Art

[0002] Transient Voltage Suppressor (TVS) is an overvoltage protection device with bidirectional voltage stabilization characteristics and bidirectional negative resistance characteristics. It is used in various AC and DC power supply circuits to suppress instantaneous overvoltage. When a surge pulse voltage appears in the protected circuit, the bidirectional breakdown diode can quickly break down from a high resistance state to a low resistance state, shunting and clamping the surge voltage, thereby protecting the components in the circuit from being damaged by the instantaneous surge pulse voltage.

[0003] The capacitance is determined by the cross section of the TVS avalanche junction and is measured at a specific operating frequency (such as 1MHz). The size of the capacitance is proportional to the current carrying capacity of the TVS. Too much capacitance will cause signal attenuation. Therefore, capacitance is an important parameter for selecting TVS in data interface circuits. For capacitors, the higher the data / signal frequency of the circuit, the greater the interference of the diode capacitor to the circuit, and the greater the noise or attenuation signal intensity. Therefore, it is necessary to determine the capacitance range of the selected component based on the characteristics of the circuit. For high-frequency circuits, the capacitance should generally be as small as possible, such as LCTVS and low-capacitor TVS, the capacitance should not exceed 3pF, while the capacitance of the circuit that does not require high capacitance can be higher than 40pF.

[0004] At present, when measuring capacitance in mass production, due to the differences in test benches (such as test lines, test sockets, and test positions), the test results are affected by distributed parameters, resulting in a certain deviation from the actual value. When testing low-impedance devices, this error has a greater impact on the measurement results. The stray capacitance change caused by the movement of the test bench can reach around 0.1pF, which is unacceptable for ultra-low capacitance. Summary of the invention

[0005] The embodiments of the present application provide a wafer testing method, system and testing machine, which can solve the problem of inaccurate stray capacitance test results in the existing wafer testing process, so as to improve the accuracy and efficiency of wafer testing.

[0006] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0007] In a first aspect, a wafer testing method is provided. The method comprises:

[0008] The tester receives a calibration start signal from the test bench, where the calibration start signal is used to indicate that the wafer has been placed at a specified position, where the specified position is a position where the wafer is not in contact with the test bench and the distance between the wafer and the test bench is less than or equal to a distance threshold;

[0009] The test machine sends an open circuit calibration instruction to the test bench, and the open circuit calibration instruction is used to eliminate the adverse effect of stray capacitance between the wafer and the test bench on the wafer test;

[0010] The test machine receives the capacity value of the stray capacitance from the test bench;

[0011] The test machine sends an open circuit calibration success signal to the test bench. The open circuit calibration success signal is determined according to the capacity value of the stray capacitance, and is used to indicate that the open circuit calibration of the wafer is successful, and to instruct the probe of the test bench to contact the wafer so as to test the wafer.

[0012] In one possible implementation, the open circuit calibration instruction includes one or more single-frequency zeroing instructions, and the one or more single-frequency zeroing instructions are used to control the capacitance value of the stray capacitance between the wafer and the test bench to be less than or equal to a capacitance threshold.

[0013] Optionally, the open circuit calibration success signal is determined according to the capacitance value of the stray capacitance, including:

[0014] If the capacitance value of the stray capacitance is less than or equal to the capacitance threshold, an open circuit calibration success signal is generated.

[0015] Optionally, the one or more single frequency clear instructions include an operating frequency of the wafer.

[0016] Furthermore, the method further comprises:

[0017] The tester receives a test start signal from the test bench, where the test start signal is used to indicate that a probe of the test bench has contacted the wafer;

[0018] The test machine sends a test instruction to the test bench, and the test instruction is determined according to the test start signal and is used to test the wafer;

[0019] The tester receives the test data of the wafer from the test bench;

[0020] The test machine sends a test end signal and test results to the test bench. The test end signal is used to indicate that the test work of the wafer has been completed. The test result is determined based on the test data and is used by the test bench to classify the wafers.

[0021] Optionally, the test results include a wafer passing test and a wafer failing test;

[0022] If the wafer passes the test, the wafer is classified as qualified; or,

[0023] If the wafer fails the test, the classification result of the wafer is rejected.

[0024] In a second aspect, a wafer testing system is provided. The system includes a testing machine and a testing table; wherein the testing machine is used to perform the following steps:

[0025] Receiving a calibration start signal from the test bench, the calibration start signal is used to indicate that the wafer has been placed at a specified position, where the specified position is a position where the wafer is not in contact with the test bench and the distance between the wafer and the test bench is less than or equal to a distance threshold;

[0026] Sending an open circuit calibration instruction to the test bench, the open circuit calibration instruction is used to eliminate the adverse effect of stray capacitance between the wafer and the test bench on the wafer test;

[0027] Receiving the capacity value of stray capacitance from the test bench;

[0028] An open circuit calibration success signal is sent to the test bench. The open circuit calibration success signal is determined according to the capacity value of the stray capacitance, and is used to indicate that the open circuit calibration of the wafer is successful, and to instruct the probe of the test bench to contact the wafer so as to test the wafer.

[0029] In some implementations, the open circuit calibration instruction includes one or more single frequency zeroing instructions, and the one or more single frequency zeroing instructions are used to control the capacitance value of the stray capacitance between the wafer and the test bench to be less than or equal to a capacitance threshold.

[0030] Optionally, the open circuit calibration success signal is determined according to the capacitance value of the stray capacitance, including:

[0031] If the capacitance value of the stray capacitance is less than or equal to the capacitance threshold, an open circuit calibration success signal is generated.

[0032] Optionally, the one or more single frequency clear instructions include an operating frequency of the wafer.

[0033] Furthermore, the testing machine is also used to perform the following steps:

[0034] receiving a test start signal from a test station, the test start signal being used to indicate that a probe of the test station has contacted the wafer;

[0035] Sending a test instruction to the test station, the test instruction is determined according to the test start signal and is used to test the wafer;

[0036] receiving test data of wafers from a test station;

[0037] The test end signal and test result are sent to the test bench. The test end signal is used to indicate that the test work of the wafer has been completed. The test result is determined based on the test data and is used by the test bench to classify the wafer.

[0038] Optionally, the test results include a wafer passing test and a wafer failing test;

[0039] If the wafer passes the test, the wafer is classified as qualified; or,

[0040] If the wafer fails the test, the classification result of the wafer is rejected.

[0041] In a third aspect, a testing machine is provided, comprising a processor and a memory, wherein the memory stores programs or instructions, and when the programs or instructions are executed by the processor, the testing machine executes the wafer testing method as described in any implementation of the first aspect.

[0042] In a fourth aspect, a computer-readable storage medium is provided, storing a program or instruction. When a computer reads and executes the program or instruction, the computer executes the wafer testing method as described in any implementation of the first aspect.

[0043] In the existing wafer testing process, an open circuit calibration is usually performed on an empty test bench (i.e., no wafer is placed on the test bench) first. After the open circuit calibration is passed, multiple wafers of the same batch are placed on the test bench in sequence for testing. That is, all wafer tests are completed based on the open circuit calibration results when the test bench is empty. Since the stray capacitance between the wafer and the test bench depends on many factors such as whether the wafer contacts the test bench (whether the test bench is empty) and the distance between the wafer and the test bench, these factors will cause the stray capacitance in the empty test bench scenario to differ greatly from the stray capacitance actually generated when the wafer contacts the test bench, resulting in a large difference in the wafer test results based on the open circuit calibration results of the empty test bench with large errors, resulting in large errors in the wafer test results. In addition, it is not considered that when different wafers are tested, there will be deviations in the distances between different wafers and the test bench, resulting in deviations in the stray capacitance between different wafers and the test bench, which will lead to deviations in the test results of different wafers using the same open circuit calibration results, that is, the test results are also inaccurate between different wafers.

[0044] Based on the wafer testing method, system and testing machine provided in the embodiments of the present application, before testing each wafer, the wafer can be placed in a designated position that is not in contact with the test bench and is close enough to the test bench (less than or equal to a distance threshold, such as 30 to 50 microns) to complete an open circuit calibration. After the open circuit calibration is successful, the wafer can be tested using the open circuit calibration result for the wafer. Compared with the open circuit calibration in the scenario where the test bench is idle used in the existing wafer testing process, the deviation between the stray capacitance when the wafer is placed in the designated position and the actual stray capacitance generated when the wafer is in contact with the test bench is smaller, that is, the wafer is placed The open circuit calibration result placed at the above-specified position is more accurate and more targeted. Therefore, using the open circuit calibration result for the wafer to test the wafer can obtain more accurate wafer test results, and can avoid the measurement error caused by the difference in distance between different wafers and the test bench, but using the same open circuit calibration result to complete the wafer test. This can more effectively improve the accuracy and reliability of wafer testing, thereby reducing the probability of problematic wafers flowing into subsequent processes, such as packaging, mounting, sales and maintenance, etc., which can greatly reduce the workload of subsequent processes and reduce customer complaints, thereby improving efficiency and customer satisfaction. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0046] Figure 1 A schematic diagram of a process of a wafer testing method;

[0047] Figure 2 A schematic diagram of the architecture of a wafer testing system is provided for an embodiment of the present application;

[0048] Figure 3 A schematic diagram of a wafer testing method according to an embodiment of the present application;

[0049] Figure 4 A schematic diagram of a scenario for performing open circuit calibration on a wafer provided in an embodiment of the present application;

[0050] Figure 5 A waveform diagram of a test signal provided in an embodiment of the present application;

[0051] Figure 6 A structural schematic diagram of a testing machine is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0053] First, in conjunction with the accompanying drawings, the prior art related to the technical solution provided in the embodiments of the present application is introduced.

[0054] For example, Figure 1 FIG. 1 is a flow chart of a wafer testing method. Figure 1 As shown, the method comprises the following steps:

[0055] S101, when no wafer is placed on the prober, open circuit calibration is performed on the tester. For example, if the ideal empty measurement value of the stray capacitance is near 0pF, such as between -0.01pF and 0.01pF, the open circuit calibration is considered successful.

[0056] S102, a wafer is placed on a test bench, and a test machine calls a test program for the wafer model, wherein the test program is set according to the characteristics of the wafer.

[0057] S103, moving the test bench to contact the wafer to start testing, triggering the test bench to generate a Start Of Test (SOT) signal.

[0058] S104, the test bench sends a test start signal to the test machine, and the test machine receives the test start signal.

[0059] S105, after receiving the test start signal, the test machine tests the wafer according to the program requirements, such as sending one or more single-frequency test instructions to the test bench.

[0060] S106, the test machine receives test data from the test bench, such as a response signal made by the wafer after receiving a test instruction.

[0061] S107, the test machine generates a test result and an End Of Test (EOT) signal according to the test data, and sends the result to the test station. The test result may be a test pass or a test fail, and may be a logic signal.

[0062] S108, after receiving the test end signal, the test bench will classify the product according to the test result. For example, if the test passes, the wafer can be classified as a good product, and if the test fails, the wafer can be classified as a defective product.

[0063] Then, the next wafer is placed on the test bench, and the above steps S102 to S108 are continued until the test of the wafers in the same batch is completed.

[0064] It can be seen from the above process that, under the premise that the hardware and capacitance range do not change, open circuit calibration is only performed before testing all wafers and when the test bench is empty (no wafers are placed). Not only are all wafers tested using the same open circuit calibration result, but the open circuit calibration is completed when the test bench is empty, without considering the different effects of whether the wafer is placed on the test bench on the open circuit calibration result, nor is it considered the effect of the distance between the wafer and the test bench when different wafers are placed on the test bench on the open circuit calibration result. As a result, the accuracy and reliability of wafer testing are poor, which in turn leads to problems such as a decrease in the yield rate in subsequent processes such as packaging, patch mounting, finished product manufacturing, high repair and maintenance costs, customer complaints, etc., resulting in reduced production efficiency, increased costs, and possible reduced customer satisfaction.

[0065] For example, Figure 2 A schematic diagram of the architecture of a wafer testing system is provided for an embodiment of the present application. Figure 2 As shown, the system includes a testing machine and a testing bench; wherein, the testing machine is used to execute the wafer testing method provided in the embodiment of the present application, such as executing a program or instruction that can implement the wafer testing method provided in the embodiment of the present application, and the testing bench is used to install the wafer to be tested and cooperate with the testing machine to complete the wafer testing. The specific implementation can refer to the following method embodiment, which will not be repeated here.

[0066] For example, Figure 3 The following is a flow chart of a wafer testing method provided in an embodiment of the present application. Figure 3 As shown, the method comprises the following steps:

[0067] S300, after placing the wafer at the designated position, open circuit calibration is performed on the wafer, such as executing the following S301 to S304:

[0068] S301, the test bench sends a calibration start signal to the test machine, and the test machine receives the calibration start signal from the test bench. The calibration start signal is used to indicate that the wafer has been placed at a specified position, where the wafer is not in contact with the test bench and the distance between the wafer and the test bench is less than or equal to a distance threshold.

[0069] The distance threshold is a very small value, such as 20 microns to 50 microns. In this way, it can be ensured that the capacity of the open-circuit stray capacitance between the wafer and the test bench when the wafer is open-circuited and calibrated is as close as possible to the actual stray capacitance between the wafer and the test bench when the wafer is contacted with the test bench for testing, so that the adverse effects of the stray capacitance between the wafer and the test bench can be eliminated as much as possible when the wafer is tested using the open-circuit calibration result, thereby improving the accuracy and reliability of wafer testing.

[0070] S302, the test machine sends an open circuit calibration instruction to the test bench, and the test bench receives the open circuit calibration instruction from the test bench, wherein the open circuit calibration instruction is used to eliminate the adverse effect of stray capacitance between the wafer and the test bench on the wafer test.

[0071] In one possible implementation, the open circuit calibration instruction includes one or more single-frequency zeroing instructions, and the one or more single-frequency zeroing instructions are used to control the capacitance value of the stray capacitance between the wafer and the test bench to be less than or equal to the capacitance threshold. The capacitance threshold can be determined according to the actual needs of the wafer test, so as to eliminate the adverse effects of the stray capacitance on the accuracy of the wafer test as much as possible, and is usually a very small value, such as ±0.01pF.

[0072] Optionally, one or more single-frequency clear instructions include the operating frequency of the wafer. Among them, the frequency of any single-frequency clear instruction can be determined according to the operating frequency of the wafer (such as the clock frequency of the wafer), such as a single-frequency clear instruction of 1MHz or 5MHz. It is easy to understand that if the wafer has multiple working clocks (such as multiple clock domains), there can be multiple single-frequency clear instructions.

[0073] S303, the test bench sends the capacity value of the stray capacitance to the test machine, and the test machine receives the capacity value of the stray capacitance from the test bench. Wherein, stray capacitance refers to the stray capacitance between the wafer and the test bench after open circuit calibration (compensation). Ideally, the stray capacitance after open circuit calibration (compensation) is 0. In actual testing work, the stray capacitance after open circuit calibration can be kept within a very small range without affecting the accuracy of wafer testing, such as being less than or equal to the above-mentioned capacitance threshold.

[0074] It should be noted that the above open circuit calibration operations, such as S302 and S303, may be performed once or multiple times until the capacitance value of the stray capacitance is less than or equal to the capacitance threshold.

[0075] S304, the tester sends an open circuit calibration success signal to the test bench, and the test bench receives the open circuit calibration success signal from the tester. The open circuit calibration success signal is determined according to the capacitance value of the stray capacitance, and is used to indicate that the open circuit calibration of the wafer is successful, and to instruct the probe of the test bench to contact the wafer so as to test the wafer.

[0076] Optionally, the open circuit calibration success signal is determined according to the capacitance value of the stray capacitance, including:

[0077] If the capacitance value of the stray capacitance is less than or equal to the capacitance threshold, an open circuit calibration success signal is generated.

[0078] For example, Figure 4 A schematic diagram of a scenario for performing open circuit calibration on a wafer provided in an embodiment of the present application. Figure 4 As shown, the design under test (DUT) is the wafer, G is the stray conductance, which can be regarded as the resistive stray parameter of the wafer in parallel, and B is the stray susceptance, which can be regarded as the inductive or capacitive stray parameter of the wafer in parallel. The purpose of the open circuit calibration is to place the wafer in a designated position that does not contact the test bench and is close enough to the test bench before testing the wafer to complete the open circuit calibration, so that when the test bench contacts the wafer for testing the wafer, the open circuit calibration result for the wafer is used to compensate or even eliminate the measurement error caused by the stray parameters between the wafer and the test bench, thereby improving the accuracy and reliability of wafer testing.

[0079] Furthermore, after the open circuit calibration is completed, the test work on the wafer can be started, that is, the following S305 to S308 are continued to be executed:

[0080] S305, the test bench sends a Start Of Test (SOT) signal to the test machine, and the test machine receives the Start Of Test signal from the test bench. The Start Of Test signal is used to indicate that the probe of the test bench has contacted the wafer, that is, the test bench has made preparations for testing the wafer, and the test machine can start the test program of the wafer accordingly.

[0081] S306, the test machine sends a test instruction to the test bench, and the test bench receives the test instruction from the test machine, wherein the test instruction is determined according to the test start signal and is used to test the wafer.

[0082] S307, the test bench sends the test data of the wafer to the test machine, and the test machine receives the test data of the wafer from the test bench. The test data may include data obtained by testing the response signal of the wafer to the test instruction, including but not limited to: measurement data of various physical quantities such as voltage, current, power, resistance, inductance, capacitance, etc.

[0083] S308, the tester sends an End Of Test (EOT) signal and test results to the test bench, and the test bench receives the End Of Test signal and test results from the tester. The End Of Test signal is used to indicate that the test work of the wafer has been completed, and the test result is determined according to the test data and the design target of the wafer, and is used by the test bench to classify the wafer.

[0084] If the test data shows that the wafer's various indicators meet the design goals, the wafer is classified as passed, qualified, or good. If the test data shows that the wafer has indicators that do not meet the design goals, the wafer is classified as failed, unqualified, or defective. Specifically, the test results include wafers that pass the test and wafers that fail the test;

[0085] If the wafer passes the test, the wafer is classified as qualified or good; or,

[0086] If the wafer fails the test, the wafer is classified as unqualified or defective.

[0087] For example, Figure 5 The waveform diagram of the test signal provided in the embodiment of the present application. Figure 5 As shown, SOT is the test start signal, EOT is the test end signal, and BIN is the signal corresponding to the test instruction, which can be a binary signal. It can be seen that when the test bench is ready to test the wafer (the mobile test bench contacts the wafer), the test bench sends a SOT signal (valid at low level) to the test machine. After the test machine receives the SOT signal, it knows that the test bench is ready for the test, then starts the test program and sends a test instruction (BIN signal, valid at low level) to the test bench. During the validity period of the BIN signal, the test bench is instructed to perform various tests on the wafer and feedback the test data to the test machine. The test machine determines whether the wafer passes the test based on the test data and the design target of the wafer, and sends an EOT signal to the test machine when the test is completed, and sends the test result together with the EOT signal. Among them, the test result can be that the wafer passes the test or the wafer fails the test. After the tester receives the EOT signal, it classifies the wafer according to the test results. If the wafer passes the test, the classification result of the wafer can be a test success, a qualified wafer, or a good wafer. On the contrary, if the wafer fails the test, the classification result of the wafer can be a test failure, a unqualified wafer, or a defective wafer. After that, the next wafer can be tested until the test of the same batch and the same model of wafers is completed.

[0088] In addition, if Figure 5As shown, to avoid EOT signal transmission errors, the EOT signal is valid only during the valid period of the BIN signal, the width of the BIN signal is larger than the width of the EOT signal, and the EOT signal is valid after the BIN signal is valid, and the EOT signal is invalid before the BIN signal is invalid, that is, there is a front porch before the EOT signal is valid, and there is a back porch after the EOT signal is invalid, so as to play a protective role.

[0089] It is easy to understand that wafers that pass the test can enter the subsequent processes, such as packaging, mounting, sales and maintenance, etc. Wafers that fail the test can be directly eliminated to avoid entering the subsequent processes and increasing the workload, thereby improving the efficiency of the subsequent processes, reducing customer complaints and improving satisfaction.

[0090] For example, Figure 6 A structural diagram of a testing machine is provided for an embodiment of the present application. Figure 4 As shown, the test machine 600 includes a processor 601, a memory 602 and a communication interface 603. The memory 602 stores a program or instruction. When the program or instruction is executed by the processor 601, the test machine 600 executes the wafer testing method described in any implementation of the above method embodiment. Among them, the communication interface 603 is used for the test machine 600 to communicate with the test bench or other equipment using various forms of signals such as electrical signals, optical signals, and radio frequency signals.

[0091] An embodiment of the present application provides a computer-readable storage medium storing a program or instruction. When a computer reads and executes the program or instruction, the computer executes the wafer testing method as described in any implementation manner in the above method embodiments.

[0092] In the existing wafer testing process, an open circuit calibration is usually performed on an empty test bench (i.e., no wafer is placed on the test bench) first. After the open circuit calibration is passed, multiple wafers of the same batch are placed on the test bench in sequence for testing. That is, all wafer tests are completed based on the open circuit calibration results when the test bench is empty. Since the stray capacitance between the wafer and the test bench depends on many factors such as whether the wafer contacts the test bench (whether the test bench is empty) and the distance between the wafer and the test bench, these factors will cause the stray capacitance in the empty test bench scenario to differ greatly from the stray capacitance actually generated when the wafer contacts the test bench, resulting in a large difference in the wafer test results based on the open circuit calibration results of the empty test bench with large errors, resulting in large errors in the wafer test results. In addition, it is not considered that when different wafers are tested, there will be deviations in the distances between different wafers and the test bench, resulting in deviations in the stray capacitance between different wafers and the test bench, which will lead to deviations in the test results of different wafers using the same open circuit calibration results, that is, the test results are also inaccurate between different wafers.

[0093] Based on the wafer testing method, system and testing machine provided in the embodiments of the present application, before testing each wafer, the wafer can be placed in a designated position that is not in contact with the test bench and is close enough to the test bench (less than or equal to a distance threshold, such as 30 to 50 microns) to complete an open circuit calibration. After the open circuit calibration is successful, the wafer can be tested using the open circuit calibration result for the wafer. Compared with the open circuit calibration in the scenario where the test bench is idle used in the existing wafer testing process, the deviation between the stray capacitance when the wafer is placed in the designated position and the actual stray capacitance generated when the wafer is in contact with the test bench is smaller, that is, the wafer is placed The open circuit calibration result placed at the above-specified position is more accurate and more targeted. Therefore, using the open circuit calibration result for the wafer to test the wafer can obtain more accurate wafer test results, and can avoid the measurement error caused by the difference in distance between different wafers and the test bench, but using the same open circuit calibration result to complete the wafer test. This can more effectively improve the accuracy and reliability of wafer testing, thereby reducing the probability of problematic wafers flowing into subsequent processes, such as packaging, mounting, sales and maintenance, etc., which can greatly reduce the workload of subsequent processes and reduce customer complaints, thereby improving efficiency and customer satisfaction.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A wafer testing method, characterized in that: include: The tester receives a calibration start signal from the test bench, wherein the calibration start signal is used to indicate that the wafer has been placed at a specified position, wherein the specified position is a position where the wafer is not in contact with the test bench and the distance between the wafer and the test bench is less than or equal to a distance threshold; The test machine sends an open circuit calibration instruction to the test bench, wherein the open circuit calibration instruction is used to eliminate the adverse effect of stray capacitance between the wafer and the test bench on wafer testing; The testing machine receives the capacity value of the stray capacitance from the testing station; The test machine sends an open circuit calibration success signal to the test bench, where the open circuit calibration success signal is determined based on the capacity value of the stray capacitance, and is used to indicate that the open circuit calibration of the wafer is successful, and to instruct the probe of the test bench to contact the wafer so as to test the wafer.

2. The method according to claim 1, characterized in that The open circuit calibration instruction includes one or more single-frequency zeroing instructions, and the one or more single-frequency zeroing instructions are used to control the capacitance value of the stray capacitance between the wafer and the test bench within a range less than or equal to a capacitance threshold.

3. The method according to claim 2, characterized in that The open circuit calibration success signal is determined according to the capacitance value of the stray capacitance, including: If the capacitance value of the stray capacitance is less than or equal to the capacitance threshold, the open circuit calibration success signal is generated.

4. The method according to claim 2, characterized in that: One or more of the single frequency clear instructions include an operating frequency of the wafer.

5. The method according to any one of claims 1 to 4, characterized in that: Also includes: The tester receives a test start signal from the test station, wherein the test start signal is used to indicate that a probe of the test station has contacted the wafer; The test machine sends a test instruction to the test bench, wherein the test instruction is determined according to the test start signal and is used to test the wafer; The testing machine receives the test data of the wafer from the testing station; The testing machine sends a test end signal and a test result to the testing station, wherein the test end signal is used to indicate that the test work of the wafer has been completed, and the test result is determined based on the test data and is used by the testing station to classify the wafer.

6. The method according to claim 5, characterized in that The test results include whether the wafer passed the test or failed the test; If the wafer passes the test, the classification result of the wafer is qualified; or, If the wafer fails the test, the classification result of the wafer is unqualified.

7. A wafer testing system, characterized in that: The invention comprises a testing machine and a testing bench; wherein the testing machine is used to perform the following steps: Receiving a calibration start signal from the test bench, the calibration start signal being used to indicate that the wafer has been placed at a specified position, the specified position being a position where the wafer is not in contact with the test bench and the distance between the wafer and the test bench is less than or equal to a distance threshold; Sending an open circuit calibration instruction to the test bench, wherein the open circuit calibration instruction is used to eliminate the adverse effect of stray capacitance between the wafer and the test bench on wafer testing; receiving a capacity value of the stray capacitance from the test bench; An open circuit calibration success signal is sent to the test bench, where the open circuit calibration success signal is determined according to the capacity value of the stray capacitance, and is used to indicate that the open circuit calibration of the wafer is successful, and to instruct a probe of the test bench to contact the wafer so as to test the wafer.

8. The system according to claim 7, characterized in that The open circuit calibration instruction includes one or more single-frequency zeroing instructions, and the one or more single-frequency zeroing instructions are used to control the capacitance value of the stray capacitance between the wafer and the test bench within a range less than or equal to a capacitance threshold.

9. The system according to claim 8, characterized in that The open circuit calibration success signal is determined according to the capacitance value of the stray capacitance, including: If the capacitance value of the stray capacitance is less than or equal to the capacitance threshold, the open circuit calibration success signal is generated.

10. The system according to any one of claims 7 to 9, characterized in that: The testing machine is also used to perform the following steps: receiving a test start signal from the test station, wherein the test start signal is used to indicate that a probe of the test station has contacted the wafer; Sending a test instruction to the test station, wherein the test instruction is determined according to the test start signal and is used to test the wafer; receiving test data of the wafer from the test station; A test end signal and a test result are sent to the test bench, wherein the test end signal is used to indicate that the test work of the wafer has been completed, and the test result is determined according to the test data and is used by the test bench to classify the wafer.

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