Dynamic unit matching enhanced current steering type digital-to-analog converter based on pseudorandom sequence generation

Abstract

The invention discloses a dynamic unit matching enhanced current steering type digital-to-analog converter structure generated based on a pseudorandom sequence. The circuit is composed of a high-speed parallel-to-serial interface, a decoder, a shifter, a sampling drive circuit, a clock frequency divider, a band-gap reference circuit and a switch current unit. The digital-to-analog converter controls the shifter to perform random shifting through a random number generated by the pseudo-random sequence generator, and the randomness of input data is increased by alternately selecting traditional sequential shifting and cross shifting. According to the invention, by selecting the MOS tube type with small mismatch degree and the four-quadrant random walk layout mode, performing six-stage binary tree buffering on the clock of the sampling drive circuit, and alternately selecting the traditional sequence shift and cross shift, the mismatch degree and the time sequence deviation on the clock link caused by process manufacturing and real working environment are reduced, and the time sequence deviation on the clock link is reduced. And meanwhile, the randomization degree of data is improved, the dynamic unit matching degree is enhanced, and the method is suitable for various communication and measurement devices.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and in particular to a dynamic unit matching enhanced current steering type digital-to-analog converter based on pseudo-random sequence generation. Background Art

[0002] A digital-to-analog converter is a medium that converts digital signals into analog signals. Since digital signals are stable and easy to process, they are the main signals processed by modern computers. However, the interaction between humans and between humans and instruments is often more convenient and intuitive with analog signals, so a digital-to-analog converter is needed to convert the signal processed in the digital domain into an analog signal. The indicators for measuring digital-to-analog converters include accuracy, speed, and power consumption. High-speed and high-precision digital-to-analog converters are widely used in the field of communications. They can directly synthesize the required signals without adding an up-conversion process, greatly improving the reliability of the system.

[0003] The current steering type digital-to-analog converter has the characteristics of high speed and strong driving capability. It is the main implementation method of high-speed and high-precision digital-to-analog converter. It mainly consists of decoding circuit, driving circuit and switching current unit array. The binary digital code generates thermometer code through the decoding circuit to reduce the burrs generated by the high bit. The driving circuit uses the decoding result to generate a high-quality differential switch signal, controls the corresponding switching current unit to direct to the positive output terminal or the negative output terminal, and obtains the output signal by the voltage difference on the output terminal resistor.

[0004] However, there are usually the following problems in the traditional current-steering DAC structure:

[0005] 1. Process manufacturing and actual working environment will cause different degrees of mismatch between internal devices of the chip;

[0006] 2. Timing deviation with gradient characteristics will appear on the internal clock link of the chip;

[0007] 3. The degree of randomization that can be achieved by traditional dynamic unit matching based on sequential shifting is limited.

[0008] Therefore, the current-steering DAC needs to be improved accordingly to solve the above problems. Summary of the invention

[0009] The present invention aims to solve the problems of device mismatch, timing error and limited random degree of dynamic unit matching in traditional current-steering digital-to-analog converters, and propose a current-steering digital-to-analog converter with enhanced dynamic element matching.

[0010] The invention comprises a high-speed parallel-to-serial interface, a decoder, a shifter and a delayer, a sampling drive circuit, a clock frequency divider, a bandgap reference circuit and a switch current unit.

[0011] The high-speed parallel-to-serial interface is used to convert multiple low-speed data into single-channel high-speed data, and provide the single-channel high-speed data to the decoder;

[0012] The decoder is used to translate the high bits of the single-channel high-speed data into thermometer codes and the low bits into binary codes, and output the codes to the shifter and the delayer;

[0013] The shifter and delayer are used to randomly shift the thermometer code, delay match the binary code, and output it to the sampling drive circuit;

[0014] The sampling driver is used to resample, adjust the cross point, isolate the power domain and enhance the driving force of the digital signals sent by the shifter and the delayer, and then output them to the switch current unit;

[0015] The switch current unit is used to control the signal output by the sampling drive circuit to flow to the positive phase end or the negative phase end, and convert it into a voltage signal output through a load resistor;

[0016] The clock divider is used to provide different rate clocks required by the high-speed parallel-to-serial interface, decoder, shifter and sampling drive circuit;

[0017] The bandgap reference circuit is used to provide the required voltage bias for the current source MOS tube, Cascode tube and Switch tube of the switch current unit.

[0018] The beneficial effects of the present invention are as follows:

[0019] The present invention reduces the mismatch degree caused by process manufacturing and actual working environment by selecting MOS tube types with small mismatch degree and four-quadrant random walk layout mode; reduces the timing deviation on the clock link by performing binary tree buffering on the clock of the sampling drive circuit; and improves the randomization degree of data by alternately selecting traditional sequential shifting and cross shifting, thereby enhancing the dynamic unit matching degree. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 The present invention is a block diagram of a dynamic unit matching enhanced current steering type digital-to-analog converter structure based on pseudo-random sequence generation.

[0022] Figure 2 It is a segmented decoding flow chart and its corresponding timing diagram.

[0023] Figure 3 It is a schematic diagram of a pseudo-random sequence generating circuit.

[0024] Figure 4 It is a schematic diagram of a traditional sequential shifter circuit.

[0025] Figure 5 It is a schematic diagram of a cross shifter circuit.

[0026] Figure 6 It is a schematic diagram of a sampling drive circuit. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and preferred examples, and the purpose and effects of the present invention will become more clear. It should be understood that the specific examples described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0029] In the description of the present invention, if the terms "upper", "lower", "side", etc. indicate an orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "highest", "first", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0030] The current steering type digital-to-analog converter proposed by the present invention is composed of a high-speed parallel-to-serial interface, a decoder, a shifter, a sampling drive circuit, a clock frequency divider, a bandgap reference circuit and a switch current unit.

[0031] The shifter randomly shifts the thermometer code to achieve the purpose of dynamic unit matching. The shifter is mainly composed of a traditional sequential shifter, a cross shifter and a shift mode selector. The traditional sequential shifter shifts the data to the left as a whole, the cross shifter shuffles the data and shifts it crosswise, and the shift mode selector is used to alternately select between the two shift modes to further enhance the randomness of the shift;

[0032] The sampling drive circuit is composed of a sampling stage, a latch stage and a drive stage, which resamples the input data, improves the drive capability, and adjusts the cross point.

[0033] The switch current unit is composed of a current source and a differential switch, and is provided with a tiny current source to reduce switching parasitic capacitance.

[0034] Furthermore, the dynamic unit matching enhancement technology involved in the present invention is mainly implemented by a thermometer decoder, a binary decoder, a pseudo-random sequence generator, a cross shifter and a shift mode selector. When the enable signal of the dynamic unit matching technology is low, only the traditional sequential shifter is connected to the output, and only the sequential shifting effect can be achieved. When the enable signal of the dynamic unit matching technology is high, the results of the traditional sequential shifter and the cross shifter are connected to the output through the selector, and the clock on the selector alternately controls the output of the results of the traditional sequential shifter and the cross shifter, thereby achieving the purpose of dynamic unit matching enhancement.

[0035] Furthermore, the present invention adopts a 6-6-4 segmented current steering structure, the upper 6 bits and the middle 6 bits adopt a thermometer decoding method, and the lower 4 bits adopt a binary decoding method. In the field of high-speed and high-precision digital-to-analog converters, the pure use of binary decoding methods will cause very serious current mismatch and conversion burr problems, and the pure use of thermometer decoding methods will increase the layout area by geometric multiples for each additional bit, which brings great obstacles to the wiring of power supply, clock and signal, and the chip production cost will also increase accordingly. Generally speaking, the pure thermometer decoding method will not be used on digital-to-analog converters with a conversion accuracy of more than 10 bits.

[0036] The segmented current steering structure uses a thermometer decoding method for high bits and a binary decoding method for low bits. Compared with the pure binary decoding method, the current mismatch degree is greatly reduced; compared with the pure thermometer decoding method, the layout area and routing difficulty are greatly reduced. Therefore, the segmented current steering structure has the advantages of high matching degree and moderate complexity. The present invention uses a three-segmented current steering structure, which further reduces the binary decoding bit number at the cost of a smaller circuit design complexity, so that the matching degree is increased while the complexity is reduced as much as possible.

[0037] Furthermore, in order to achieve the purpose of reducing the timing deviation, the present invention adopts a binary tree wiring for the clock when designing the actual layout of the sampling drive circuit. Generally speaking, in the clock wiring method of the sampling drive circuit, most of them adopt daisy chain wiring starting from the edge end or daisy chain wiring starting from the center. Although these two wiring methods are very simple and convenient, they inevitably introduce a timing deviation with a gradient characteristic, which will cause great damage to the dynamic performance of the current steering type digital-to-analog converter.

[0038] Furthermore, the binary tree wiring method adopted by the present invention not only routes the clock according to the binary tree, but also uses inverters at each level of bifurcation to improve the driving capability, avoiding the problem of insufficient driving force caused by excessive fan-out. Therefore, the length and load of all clock paths remain consistent, which can minimize the clock delay difference between channels and reduce the timing deviation on the clock link.

[0039] Further, in the switch current unit designed by the present invention, the type and area of ​​the MOS tube corresponding to the current source array are carefully selected, and a four-quadrant random walk layout method is adopted. Under the 28nm process, the mismatch degree between the 1.8V withstand voltage MOS tube and the 0.9V withstand voltage MOS tube is very different. Even between the 0.9V withstand voltage MOS tube, there is a difference in the mismatch degree between the low threshold voltage and the high threshold voltage MOS tube. In order to reduce the mismatch caused by process manufacturing, the present invention selects a MOS tube (nch_mac) with a low mismatch feature. However, the area size of the MOS tube also has a great influence on the mismatch degree. Generally speaking, the larger the area, the smaller the mismatch degree caused by process manufacturing, but this will increase the system mismatch caused by ambient temperature. Therefore, the present invention adopts a four-quadrant random walk layout method to compensate for the mismatch caused by process manufacturing and ambient temperature to the maximum extent.

[0040] Furthermore, in the switch current unit designed by the present invention, the input drive signal of the switch tube is cross-wired. The traditional vertical wiring method makes the coupling capacitance between the input drive signal and the output current signal larger. Even if the ground plane is used to isolate these two key signals, because they inevitably have capacitance coupled to the ground plane, the equivalent capacitance of these two capacitors in series is still enough to affect the performance. The cross-wiring method adopted by the present invention can make the coupling capacitance generated by the differential input drive signal to the output signal the same, and because the input drive signal is exactly inverted, the impact on the output signal can just offset each other. The linearity of the output signal of the digital-to-analog converter is improved.

[0041] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0042] Figure 1 is a structural block diagram of a current-steering digital-to-analog converter with dynamic cell matching enhancement according to an embodiment of the present application. Figure 1 As shown, this embodiment mainly consists of a high-speed parallel-to-serial interface 100, a decoder 200, a shifter and a delayer 300, a sampling drive circuit 400, a bandgap reference circuit 500, a clock divider 600, and a switch current unit 700.

[0043] After frequency division, the sampling clock becomes 4 low-speed clocks CLK_1 / 2 / 3 / 4, which are used as the clock input of the high-speed parallel-to-serial interface to control the acceleration of multiple low-speed data into one high-speed data. Then the high-speed data enters the decoder, and the high bit is translated into thermometer code and the low bit is translated into binary code. Then it passes through the shifter with dynamic unit matching enhancement to improve the randomness of the digital. Then it enters the sampling drive circuit to increase the drive capability while adjusting the intersection of SW_P and SW_N. Finally, it enters the switch current unit to control the current source to flow to the positive output end or the negative output end.

[0044] Figure 2 It is a key link of the dynamic unit matching enhancement technology of the current steering digital-to-analog converter - the segmented decoding flow chart and the corresponding timing relationship diagram. This part mainly includes the thermometer decoding circuit, the binary decoding circuit and the synchronization circuit. The thermometer decoding circuit translates the binary code Binary<15:4> into the thermometer code Thermometer_MSB<63:0> and Thermometer_ULSB<63:0>. Figure 2 The correspondence between the data before and after decoding is marked. The binary decoding circuit consists of a buffer, whose purpose is to match the delay of the thermometer decoding circuit. The decoded data is aligned by the synchronization circuit and output as MSB<63:0>, ULSB<63:0>, LSB<3:0>.

[0045] Figure 3 The schematic diagram of the pseudo-random sequence generation circuit is a key link in the dynamic unit matching enhancement technology of the current steering type digital-to-analog converter. The circuit is composed of registers connected end to end to form a shift register. When the rising edge of the clock signal CLK comes, the data is transmitted backward in sequence. In order to avoid the situation where the data stream outputs the level "0" state at the same time and cannot escape, a state avoidance circuit is designed to jump out of this state in time when the output state appears to be all "0". Finally, select Q <1> , Q <3> , Q <9> , Q <19> , Q <25> , Q <31> Acts as a random number controlled shifter to accomplish dynamic cell matching.

[0046] Figure 4 and Figure 5 The key link of the dynamic unit matching enhancement technology for current-steering digital-to-analog converters is the schematic diagram of the traditional sequential shifter and cross-shifter circuit. Figure 4The conventional sequential shifter consists of multiple stages of selectors, each stage has 63 selectors. Obviously, each stage of selectors can achieve left shift or no shift. Whether to shift the 6-bit data Q generated by the pseudo-random sequence circuit <1> , Q <3> , Q <9> , Q <19> , Q <25> , Q <31> Control, so that the input data MSB<63:0> can be randomly shifted to the left in the range of 0 to 63. Although this sequential shifting method achieves the purpose of dynamic unit matching to a certain extent, it is limited by the degree of randomization of the shift and can only shift in the range of 0 to 63. The dynamic unit enhancement technology proposed in the embodiment of the present application adds an additional cross shifter. Figure 5 It can be seen that the shifting method is no longer the traditional sequential shifting, but is replaced by different degrees of cross shifting. With this shifting method, the data MSB<63:0> is no longer moved sequentially as a whole, but instead the MSB<63:0> will be shifted in a disordered manner. Combining the traditional sequential shifting method with the cross shifting method further improves the degree of randomness and enhances the degree of dynamic unit matching.

[0047] Figure 6 The schematic diagram of the sampling drive circuit of the current steering type digital-to-analog converter. The data MSB<63:0>, ULSB<63:0>, and LSB<3:0> all have their own channels. To ensure that all data can reach the switch current unit at the same time after passing through the drive circuit, the sampling clocks of the drive circuits corresponding to all channels should have as small a timing error as possible. Therefore, the embodiment of the present application passes the clock CLK through a multi-level binary tree buffer to obtain 132 clocks CLK_Drive<131:0>, which not only ensures that the clock has sufficient driving capability, but also minimizes the timing error.

[0048] In addition to introducing a binary tree clock to the sampling drive circuit, the embodiment of the present application also uses a set of new power grounds VDDC10 and VSSC to the circuit to avoid signal-related fluctuations from being introduced into the drive signal. In the sampling drive circuit, whether it is a sampling stage, a latch stage or a drive stage, the high and low levels of their respective outputs and the conversion process are directly affected by their corresponding power supplies and grounds. Essentially, the sampling stages composed of M0, M1, M2, M3, M4, and M5, the latch stages composed of INV0 and INV1, and the drive stages composed of INV2 and INV3 are all push-pull structures, so the conversion process is completed by the power ground to pull up or pull down, and the high and low levels of each fully reflect the fluctuations of the power ground. These fluctuations will enter the switch current unit with the drive signal. If the sampling drive circuit uses the same power ground VDDD10 and VSSD as the digital circuit, then the fluctuations related to the signal they carry will directly enter the switch current unit, and then greatly reduce the linearity of the output signal by coupling the cross point. Therefore, the embodiment of the present application uses a new set of power grounds VDDC10 and VSSC to avoid the original power grounds VDDD10 and VSSD with signal-related fluctuations from affecting the driving signal, thereby improving the linearity of the output signal.

[0049] A current-steering digital-to-analog converter with enhanced dynamic unit matching proposed in an embodiment of the present application, compared with a traditional current-steering digital-to-analog converter, reduces the device mismatch caused by process manufacturing and actual working environment through a shifter with enhanced randomization, a sampling drive circuit with tree-like wiring, MOS tube area selection with low mismatch characteristics, and a switch tube with dual cross-drive signals, thereby minimizing the clock error with gradient characteristics between each bit channel, enhancing the degree of dynamic unit matching, and being applicable to various communication and measurement equipment.

[0050] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims

1. A dynamic unit matching enhanced current steering type digital-to-analog converter based on pseudo-random sequence generation, comprising a high-speed parallel-to-serial interface, a decoder, a shifter and a delayer, a sampling drive circuit, a clock divider, a bandgap reference circuit and a switch current unit; characterized in that: The high-speed parallel-to-serial interface is used to convert multiple low-speed data into single-channel high-speed data, and provide the single-channel high-speed data to the decoder; The decoder is used to translate the high bits of the single-channel high-speed data into thermometer codes and the low bits into binary codes, and output the codes to the shifter and the delayer; The shifter and delayer are used to randomly shift the thermometer code, delay match the binary code, and output it to the sampling drive circuit; The sampling driver is used to resample, adjust the cross point, isolate the power domain and enhance the driving force of the digital signals sent by the shifter and the delayer, and then output them to the switch current unit; The switch current unit is used to control the signal output by the sampling drive circuit to flow to the positive phase end or the negative phase end, and convert it into a voltage signal output through a load resistor; The clock divider is used to provide different rate clocks required by the high-speed parallel-to-serial interface, decoder, shifter and sampling drive circuit; The bandgap reference circuit is used to provide the required voltage bias for the current source MOS tube, Cascode tube and Switch tube of the switch current unit.

2. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1, characterized in that: For 16-bit precision, the decoder performs thermometer decoding on the upper 6 bits to decode into a 63-bit thermometer code, performs thermometer decoding on 6 bits to decode into a 63-bit thermometer code, and performs binary decoding on the lower 4 bits to decode into a 4-bit binary code.

3. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1 or 2, characterized in that: The shifter includes a conventional sequential shifter, a cross shifter, a pseudo-random sequence generator and a shift mode selector.

4. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 3, characterized in that: The cross shifter is a shifting method in which a group of data is shifted in a disorderly manner by using multiple selectors.

5. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 3, characterized in that: The pseudo-random sequence generator is composed of a plurality of registers connected end to end, and an all-0 state avoidance circuit is fed back to the first register.

6. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 3, characterized in that: The shift mode selector connects the outputs of the conventional sequential shift and the cross shift to the selector, and the two shift modes are alternately selected by a clock.

7. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1 or 2, characterized in that: The clock of the sampling drive circuit adopts a binary tree wiring mode, and each level of the binary tree has an inverter as a buffer unit.

8. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 7, characterized in that: The sampling stage of the sampling drive circuit completes data sampling based on a push-pull structure, and the driving stage completes driving capability enhancement and cross point adjustment based on a push-pull structure, and uses a power ground different from other circuits of the chip.

9. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1 or 2, characterized in that: The current source array of the switch current unit adopts a four-quadrant random walk layout method.

10. The dynamic unit matching enhanced current steering digital-to-analog converter based on pseudo-random sequence generation according to claim 9, characterized in that: The switch tube input drive signal of the switch current unit adopts a cross wiring method.

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